On 7 June 2016 at 17:56, Kyrill Tkachov wrote:
> Ok for trunk?
>
> Thanks,
> Kyrill
>
> 2016-06-07 Kyrylo Tkachov
> James Greenhalgh
>
> * config/aarch64/arm_neon.h (vcopyq_lane_f32, vcopyq_lane_f64,
> vcopyq_lane_p8, vcopyq_lane_p16, vcopyq_lane_s8, vcopyq_lane_s16,
>
On 17 May 2016 at 12:02, James Greenhalgh wrote:
> On Tue, May 17, 2016 at 11:32:36AM +0100, Marcus Shawcroft wrote:
>> On 17 May 2016 at 10:06, James Greenhalgh wrote:
>> >
>> > Hi,
>> >
>> > This is just a simplification, it probably makes lif
On 17 May 2016 at 10:06, James Greenhalgh wrote:
>
> Hi,
>
> This is just a simplification, it probably makes life easier for register
> allocation in some corner cases and seems the right thing to do. We don't
> use the internal version elsewhere, so we're safe to delete it and change
> the types
On 17 May 2016 at 10:13, James Greenhalgh wrote:
>
> Hi,
>
> As in the ARM port [1] , the AArch64 port wants to put out "b = a" to set
> an alias. This doesn't cause us any trouble yet, as the AArch64 port doesn't
> warn for this construct - but at the same time there is no reason for us
> not to
On 11 January 2016 at 12:04, James Greenhalgh wrote:
> 2015-12-11 James Greenhalgh
>
> * config/aarch64/aarch64.c (cortexa57_tunings): Remove
> AARCH64_EXTRA_TUNE_RECIP_SQRT.
>
OK /Marcus
On 26 January 2016 at 16:04, James Greenhalgh wrote:
> 2016-01-25 James Greenhalgh
>
> * config/aarch64/aarch64.md
> (arch64_sqrdmlh_lane): Fix register
> constraints for operand 3.
> (aarch64_sqrdmlh_laneq): Likewise.
>
OK /Marcus
On 20 January 2016 at 15:22, James Greenhalgh wrote:
> gcc/
>
> 2016-01-20 James Greenhalgh
> Ramana Radhakrishnan
>
> * config/aarch64/aarch64.c (aarch64_expand_vector_init): Refactor,
> always use lane loads to construct non-constant vectors.
>
> gcc/testsuite/
On 11 January 2016 at 11:53, James Greenhalgh wrote:
>
> ---
> 2015-12-10 James Greenhalgh
>
> * config/aarch64/aarch64.c (use_rsqrt_p): Always use software
> reciprocal sqrt for -mlow-precision-recip-sqrt.
>
OK /Marcus
On 18 December 2015 at 12:13, James Greenhalgh wrote:
> Looking back at the patch just before I hit commit, the 4.9 backport was
> a little different (as we still have a CANNOT_CHANGE_MODE_CLASS there).
> We can drop the aarch64-protos.h and aarch64.h changes, and we need to
> change the sense of
On 11 January 2016 at 10:46, Alan Lawrence wrote:
> However, the test doesn't really look at whether we're using glibc vs
> musl/bionic/uclibc, only at whether we are targeting -linux-gnu or
> -none-elf.
Fair point, the test case is not aligned with the implementation.
Rather than hang the test
On 11 January 2016 at 08:12, Bilyan Borisov wrote:
> 2015-XX-XX Bilyan Borisov
>
> * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): New
> macro
> definition.
>
> gcc/testsuite/
>
> 2015-XX-XX Bilyan Borisov
>
> * gcc.target/aarch64/fesetround-checking-bare
On 10 September 2015 at 12:28, Jiong Wang wrote:
>
> TLS instruction sequences are always with fixed format, there is no need
> to use operand modifier, we can hardcode the relocation modifiers into
> instruction pattern, all those redundant checks in aarch64_print_operand
> can be removed.
>
> OK
On 14 December 2015 at 11:01, James Greenhalgh wrote:
> On Wed, Dec 09, 2015 at 01:13:20PM +0000, Marcus Shawcroft wrote:
>> On 27 November 2015 at 13:01, James Greenhalgh
>> wrote:
>>
>> > 2015-11-27 James Greenhalgh
>> >
>>
On 8 December 2015 at 21:35, Evandro Menezes wrote:
>Emit square root using the Newton series
>
>2015-12-03 Evandro Menezes
>
>gcc/
> * config/aarch64/aarch64-protos.h (aarch64_emit_swsqrt):
>Declare new
> function.
> * config/aarch64/aarch64-
On 27 November 2015 at 13:01, James Greenhalgh wrote:
> 2015-11-27 James Greenhalgh
>
> * config/aarch64/aarch64-protos.h
> (aarch64_cannot_change_mode_class): Bring back.
> * config/aarch64/aarch64.c
> (aarch64_cannot_change_mode_class): Likewise.
> * c
On 4 December 2015 at 19:42, James Greenhalgh wrote:
>
> Hi,
>
> This patch fixes a bug I spotted in the add3_pluslong insn_and_split
> pattern. We need to give register constraints, otherwise the register
> allocator can do whatever it likes. This manifests as an ICE on AArch64
> with -mabi=ilp32
On 04/12/15 14:40, Kyrill Tkachov wrote:
Ping.
This almost fell through the cracks.
https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00055.html
Thanks,
Kyrill
On 01/10/15 14:00, Kyrill Tkachov wrote:
Hi all,
As part of the SWITCHABLE_TARGET work I inadvertently changed the
behaviour of -mgeneral
On 3 December 2015 at 12:17, Eric Botcazou wrote:
>> I can understand this restriction, but...
>>
>> > + /* See the same assertion on PROBE_INTERVAL above. */
>> > + gcc_assert ((first % 4096) == 0);
>>
>> ... why isn't this a test that FIRST is aligned to PROBE_INTERVAL?
>
> Because that isn't
On 4 December 2015 at 03:34, Bin Cheng wrote:
> 2015-12-01 Bin Cheng
>
> * config/aarch64/atomics.md (atomic_store): Use predicate
> aarch64_sync_memory_operand.
>
OK /Marcus
On 17 November 2015 at 22:10, Andrew Pinski wrote:
>
> This moves the #undef from the header files to the .def files like was done
> for builtins.def (https://gcc.gnu.org/ml/gcc-patches/2015-11/msg00662.html).
>
> OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.
>
> Thanks,
On 16 November 2015 at 14:36, James Greenhalgh wrote:
> 2015-11-16 James Greenhalgh
>
> * config/aarch64/aarch64-cores.def (cortex-a35): New.
> * config/aarch64/aarch64.c (cortexa35_tunings): New.
> * config/aarch64/aarch64-tune.md: Regenerate.
> * doc/invoke.te
On 9 November 2015 at 11:34, Kyrill Tkachov wrote:
> * config/aarch64/aarch64.c (aarch64_simd_valid_immediate):
> Remove integer CONST_DOUBLE handling. It should never occur.
OK /Marcus
On 9 November 2015 at 15:45, Kyrill Tkachov wrote:
>
> On 09/11/15 15:34, Marcus Shawcroft wrote:
>>
>> On 9 November 2015 at 11:32, Kyrill Tkachov
>> wrote:
>>
>>> 2015-11-09 Kyrylo Tkachov
>>>
>>> PR target/68129
>>>
On 9 November 2015 at 11:32, Kyrill Tkachov wrote:
> 2015-11-09 Kyrylo Tkachov
>
> PR target/68129
> * config/aarch64/aarch64.h (TARGET_SUPPORTS_WIDE_INT): Define to 1.
> * config/aarch64/aarch64.c (aarch64_print_operand, CONST_DOUBLE):
> Delete VOIDmode case. Assert that mode
On 20 October 2015 at 00:40, Evandro Menezes wrote:
> In the existing targets, it seems that it's always faster to zero up a DF
> register with "movi %d0, #0" instead of "fmov %d0, xzr".
>
> This patch modifies the respective pattern.
Hi Evandro,
This patch changes the generic, u architecture i
On 20 October 2015 at 17:14, Evandro Menezes wrote:
> Kyrill,
>
> Indeed, the correct log would be:
>
> The type assigned to some insn definitions was not correct.
>
> gcc/
> * config/aarch64/aarch64.md
> (*movhf_aarch64): Change the type of "mov %0.h[0], %1.h[0] to
> "neon
On 29 October 2015 at 13:50, Kyrill Tkachov wrote:
>>> Ok for trunk?
>>
>> rtl.h exposes reg_or_subregno() already doesn't that do what we need here?
>
>
> reg_or_subregno assumes that what it's passed is REG or a SUBREG.
> It will ICE on any other rtx. Here I want to strip the subreg if it is
>
On 28 October 2015 at 10:07, Kyrill Tkachov wrote:
> Hi all,
>
> This RTL checking error occurs on aarch64 in aarch_accumulator_forwarding
> when processing an msubsi insn
> with subregs:
> (insn 15 14 16 3 (set (reg/v:SI 78 [ i ])
> (minus:SI (subreg:SI (reg/v:DI 76 [ aul ]) 0)
>
On 23 October 2015 at 13:34, H.J. Lu wrote:
> On Fri, Oct 23, 2015 at 4:54 AM, Marcus Shawcroft
> wrote:
>> Hi,
>>
>> This patch breaks the distinction between build and host. For example
>> consider a configure along these lines:
>>
>> ./configure
On 23 October 2015 at 13:34, H.J. Lu wrote:
> On Fri, Oct 23, 2015 at 4:54 AM, Marcus Shawcroft
> wrote:
>> Hi,
>>
>> This patch breaks the distinction between build and host. For example
>> consider a configure along these lines:
>>
>> ./configure
Hi,
This patch breaks the distinction between build and host. For example
consider a configure along these lines:
./configure --host=aarch64-none-linux-gnu
--target=aarch64-none-linux-gnu --build=x86_64-pc-linux-gnu
Will result in:
CXX_FOR_BUILD='g++'
CXX='aarch64-none-linux-gnu-g++'
the gcc/c
On 22 October 2015 at 14:21, Li Bin wrote:
> From: Jiangjiji
>
> * gcc/config/aarch64/aarch64.opt: Add a new option.
> * gcc/config/aarch64/aarch64.c: Add some new functions and Macros.
> * gcc/config/aarch64/aarch64.h: Modify PROFILE_HOOK and FUNCTION_PROFILER.
>
> Signed-off-by: Jiangjiji
> Si
On 20 October 2015 at 17:26, Kyrill Tkachov wrote:
> Hi Marcus,
>
> On 20/10/15 17:05, Marcus Shawcroft wrote:
>>
>> On 16 October 2015 at 13:58, Kyrill Tkachov
>> wrote:
>>>
>>> Hi all,
>>>
>>> We already support load/store-pai
On 20 October 2015 at 17:31, Kyrill Tkachov wrote:
>
> On 20/10/15 17:28, Ramana Radhakrishnan wrote:
>>
>> On Tue, Oct 20, 2015 at 4:26 PM, Marcus Shawcroft
>> wrote:
>>>
>>> On 19 October 2015 at 14:57, Kyrill Tkachov
>>> wrote:
>>&g
On 16 October 2015 at 13:58, Kyrill Tkachov wrote:
> Hi all,
>
> We already support load/store-pair operations on the D-registers when they
> contain an FP value, but the peepholes/sched-fusion machinery that
> do all the hard work currently ignore 64-bit vector modes.
>
> This patch adds support
On 16 October 2015 at 12:26, Alan Lawrence wrote:
> This enables tests bb-slp-11.c and bb-slp-26.c for AArch64. Both of these are
> currently passing on little- and big-endian.
>
> (Tested on aarch64-none-linux-gnu and aarch64_be-none-elf).
>
> OK for trunk?
>
> gcc/testsuite/ChangeLog:
>
>
On 20 October 2015 at 16:47, Kyrill Tkachov wrote:
> Here's the patch updated as per your feedback.
>
> How's this?
>
> Thanks,
> Kyrill
>
> 2015-10-20 Kyrylo Tkachov
>
> * config/aarch64/aarch64.md
> (*aarch64_fcvt2_mult): New pattern.
> * config/aarch64/aarch64-simd.md
> (*aarch64_fc
On 14 October 2015 at 13:30, Wilco Dijkstra wrote:
> Enable instruction fusion of dependent AESE; AESMC and AESD; AESIMC pairs.
> This can give up to 2x
> speedup on many AArch64 implementations. Also model the crypto instructions
> on Cortex-A57 according
> to the Optimization Guide.
>
> Passes
On 19 October 2015 at 14:57, Kyrill Tkachov wrote:
> 2015-10-19 Kyrylo Tkachov
>
> * config/aarch64/aarch64.md
> (*aarch64_fcvt2_mult): New pattern.
> * config/aarch64/aarch64-simd.md
> (*aarch64_fcvt2_mult): Likewise.
> * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle abov
On 16 October 2015 at 12:05, Ramana Radhakrishnan
wrote:
> 2015-10-15 Ramana Radhakrishnan
>
> PR target/63304
> * config/aarch64/aarch64.c (aarch64_nopcrelative_literal_loads): New.
> (aarch64_expand_mov_immediate): Use
> aarch64_nopcrelative_literal_loads.
>
On 4 January 1970 at 00:02, Benedikt Huber
wrote:
> * config/aarch64/aarch64-builtins.c: Builtins for rsqrt and rsqrtf.
> * config/aarch64/aarch64-protos.h: Declare.
> * config/aarch64/aarch64-simd.md: Matching expressions for frsqrte and
> frsqrts.
> * conf
On 20 October 2015 at 13:40, Alan Lawrence wrote:
> The test vdiv_f.c #define's NAN to (0.0 / 0.0). This produces extra scalar
> fdiv's, which complicate the scan-assembler testing. We can remove these by
> using __builtin_nan instead.
>
> Tested on AArch64 Linux.
>
> gcc/testsuite/ChangeLog:
>
On 16 October 2015 at 15:31, Benedikt Huber
wrote:
> I introduced this in revision 7 due to a request from James Greenhalgh.
> https://gcc.gnu.org/ml/gcc-patches/2015-10/msg00963.html
>
>> Given that this is all so mechanical, I'd have a preference towards
>> refactoring this to loop over some str
On 16 October 2015 at 14:59, Benedikt Huber
wrote:
> + typedef struct
> + {
> +tree type_node;
> +const char *builtin_name;
> +int function_code;
> + } builtin_decls_data;
Please address Oleg's comment.
Cheers
/Marcus
Hi,
A few more style nits:
> + builtin_decls_data bdda[] = {
New line before {
> +{double_type_node, "__builtin_aarch64_rsqrt_df",
> AARCH64_BUILTIN_RSQRT_DF},
Space after {
Space before }
> +void aarch64_emit_swrsqrt (rtx, rtx);
> +
> +tree aarch64_builtin_rsqrt (unsigned int fn, b
On 09/10/15 10:17, Ramana Radhakrishnan wrote:
This started as a Friday afternoon project ...
It turned out enabling VTV for AArch64 and ARM was a matter of fixing PR67868
which essentially comes from building libvtv with section anchors turned on.
The problem was that the flow of control from
On 12 October 2015 at 12:28, Uros Bizjak wrote:
> Remove private definitions and use equivalent global macros instead.
>
> 2015-10-12 Uros Bizjak
>
> * config/aarch/aarch64.h (AARCH64_ROUND_UP): Remove.
> (AARCH64_ROUND_DOWN): Ditto.
> * config/aarch64/aarch64.c: Use ROUND_UP instea
On 6 October 2015 at 12:29, Ramana Radhakrishnan
wrote:
> Thanks for the explanation Eric, by that explanation I do not see the need to
> adjust for TARGET_EXPR or mark_addressable in the backends.
>
> Here are the patches that I'm testing - I will apply the ARM one after
> testing finishes - m
On 27 August 2015 at 10:54, Jiong Wang wrote:
>
> As described this is the main implementaion patch.
>
> 2015-08-26 Jiong Wang
>
> gcc/
> * configure.ac: Add check for binutils global dynamic tiny code model
> relocation support.
> * configure: Regenerate.
> * config.in: Regenerate.
>
On 27 August 2015 at 10:52, Jiong Wang wrote:
> 2015-08-27 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.md (tlsgd_small): Delete this define_expand.
> (*tlsgd_small): Rename this define_insn to "tlsgd_small";
OK /Marcus
On 5 October 2015 at 14:19, Jiong Wang wrote:
> 2015-10-05 James Greenhalgh
>Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.md (tlsie_tiny_sidi): Replace "" with "w".
>
How about a test case?
/Marcus
On 22 September 2015 at 17:49, Jiong Wang wrote:
> 2015-09-22 Jiong Wang
>
> gcc/testsuite/
>* gcc.target/aarch64/tlsle12_tiny_1.c: New testcase for tiny model.
>* gcc.target/aarch64/tlsle24_tiny_1.c: Likewise.
>* gcc.target/aarch64/tlsle_sizeadj_tiny_1.c: TLS size truncation test
On 2 October 2015 at 14:01, Ramana Radhakrishnan
wrote:
>>> #undef TARGET_ASM_NAMED_SECTION
>>> -#define TARGET_ASM_NAMED_SECTION aarch64_elf_asm_named_section
>>> +#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
>>
>> Isn't it sufficient to simply remove the #define completely
On 2 October 2015 at 11:08, Ramana Radhakrishnan
wrote:
> * config/aarch64/aarch64-elf.h (TARGET_ASM_NAMED_SECTION): Use
> default_elf_asm_named_section.
> * config/aarch64/aarch64.c (aarch64_elf_asm_named_section): Delete.
> ---
> gcc/config/aarch64/aarch64-elf.h | 2 +-
On 02/10/15 09:12, James Greenhalgh wrote:
2015-10-01 James Greenhalgh
* config/aarch64/aarch64-simd.md (*aarch64_combinez): Add
alternatives for reads from memory and moves from general-purpose
registers.
(*aarch64_combinez_be): Likewise.
2015-10-01 James G
On 25/09/15 08:59, James Greenhalgh wrote:
Hi,
This patch introduces a new scheduling model for Cortex-A53.
Bootstrapped and tested on arm-none-linux-gnueabi and aarch64-none-linux-gnu
and checked with a variety of popular benchmarking and microbenchmarking
suites to show a benefit.
OK?
Than
On 28 September 2015 at 06:27, Hurugalawadi, Naveen
wrote:
> Hi Marcus,
>
> Thanks for the review and comments.
>
>>> OK and can you back port to 5 ?
>
> Please find attached the backported patch on gcc-5-branch.
>
> Regression tested on AArch64 without any issues.
>
> 2015-09-28 Andrew Pinski
On 29/09/15 00:52, Evandro Menezes wrote:
In some micro-architectures the insns to load or store pairs of vector
registers are implemented rather differently from those affecting lanes
in vector registers. Then, it's important that such insns be described
likewise differently in the scheduling m
On 28 July 2015 at 14:12, Jiong Wang wrote:
>
> The instruction sequences for preparing argument for TLS descriptor
> runtime resolver and the later function call to resolver can actually be
> hoisted out of the loop.
>
> Currently we can't because we have exposed the hard register X0 as
> destina
On 25 September 2015 at 14:19, James Greenhalgh
wrote:
> 2015-09-25 James Greenhalgh
>
> * config/arm/types.md (type): Add rotate_imm.
> * config/aarch64/aarch64.md (*ror3_insn): Split out the
> ROR immediate case.
> (*rorsi3_insn_uxtw): Likewise.
> * co
On 24 September 2015 at 07:47, Hurugalawadi, Naveen
wrote:
> Hi,
>
> Please find attached the patch that fixes an ICE for prefetch.
>
> The predicate is too lose for the constraints. Hence, the patch tightens
> up the predicate to be exactly as constraint allows, avoids a “reload”
> and allows be
On 26 August 2015 at 14:58, Jiong Wang wrote:
>
> This patch cover tlsle tiny model tests, tls size truncation for tiny &
> small model included also.
>
> All testcases pass native test.
>
> OK for trunk?
>
> 2015-08-26 Jiong Wang
>
> gcc/testsuite/
> * gcc.target/aarch64/tlsle12_tiny_1.c: Ne
On 21 September 2015 at 15:38, James Greenhalgh
wrote:
> ---
> gcc/
>
> 2015-09-21 James Greenhalgh
>
> * config/aarch64/aarch64-simd.md
>
> (aarch64_float_truncate_hi_v4sf): Rewrite as an expand.
> (aarch64_float_truncate_hi_v4sf_le): New.
> (aarch64_float_trun
On 9 September 2015 at 12:43, Matthew Wahab wrote:
> gcc/
> 2015-09-09 Matthew Wahab
>
> Backport from mainline
> 2015-08-14 Matthew Wahab
>
> PR target/67143
> * config/aarch64/atomics.md (atomic_): Replace
> 'lconst_atomic' with 'const_atomic'.
>
On 8 September 2015 at 16:03, Jiong Wang wrote:
> 2015-09-08 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.c (aarch64_print_operand): Add "CONST"
> support.
OK /Marcus
On 8 September 2015 at 16:00, Jiong Wang wrote:
>
> The concept of aarch64_symbol_context is not used in AArch64, this patch
> remove it and all relevant code.
>
> ok for trunk?
>
> 2015-09-08 Jiong. Wang
>
> gcc/
> * config/aarch64/aarch64-protos.h (aarch64_symbol_context): Delete.
> * con
On 25 August 2015 at 14:57, Alan Lawrence wrote:
> Sorry - wrong version posted. The hunk for add_options_for_arm_neon_fp16 has
> moved to the previous patch! This version also fixes some whitespace issues.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c
Hi,
Thanks for your work on this. There are a bunch of predominantly
style nits in line below. My none nit comments on this patch are:
This should be left turned off for all cores where we have not seen
benchmark numbers to indicate that this optimization is a benefit, we
can take patches for e
On 16 September 2015 at 08:40, James Greenhalgh
wrote:
>
> Hi,
>
> This patch adds expanders for copysigndf3 and copysignsf3 to the AArch64
> backend. These use the BSL/BIT/BIF insn to save us from the default
> expansion pattern.
>
> Bootstrapped on aarch64-none-linux-gnu with no issues, and chec
On 27 July 2015 at 15:33, Ramana Radhakrishnan
wrote:
> Ramana Radhakrishnan
>
> PR target/63304
> * config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Handle
> nopcrelative_literal_loads.
> (aarch64_classify_address): Likewise.
> (aarch64_constan
On 25 August 2015 at 14:12, Andre Vieira wrote:
> gcc/ChangeLog:
> 2015-08-07 Ramana Radhakrishnan
> Andre Vieira
>
> * config/aarch64/aarch64.md (*condjump): Handle functions > 1 Mib.
> (*cb1): Likewise.
> (*tb1): Likewise.
> (*cb1): Likewise.
>
On 25 August 2015 at 15:15, Jiong Wang wrote:
> 2015-08-25 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.opt (mtls-size): New entry.
> * config/aarch64/aarch64.c (initialize_aarch64_tls_size): New function.
> (aarch64_override_options_internal): Call initialize_aarch64_tls_size.
> * d
On 19 August 2015 at 15:26, Jiong Wang wrote:
> 2015-08-19 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.opt (mtls-size): New entry.
> * config/aarch64/aarch64.c (initialize_aarch64_tls_size): New function.
> (aarch64_override_options_internal): Call initialize_aarch64_tls_size.
> * d
> 2015-08-19 Marcus Shawcroft
> Jiong Wang
> gcc/
> * config/aarch64/aarch64.c (initialize_aarch64_tls_size): Set default
> tls size for tiny, small, large memory model.
> (aarch64_load_symref_appropriately): Support new symbol types.
> (aarch64
> 2015-08-19 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64-protos.h (aarch64_symbol_type): Rename
> SYMBOL_TLSLE to SYMBOL_TLSLE24.
> * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Likewise
> (aarch64_expand_mov_immediate): Likewise
> (aarch64_print_operand): Likewise
ed
> later for linker IE model to LE model optimization.
>
> 2015-06-19 Marcus Shawcroft
> Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.md (UNSPEC_GOTTINYTLS): New UNSPEC.
> (tlsie_tiny_): New define_insn.
> (tlsie_tiny_sidi): Ditto.
> * config/aarc
On 19 June 2015 at 10:15, Jiong Wang wrote:
>
> Rename test source from tlsle.c into tls.c for reuse purpose.
>
> tls.c will be used as test source file for all TLS test, we just need to
> specify different tls options in different testcases.
>
> 2015-06-19 Jiong Wang
>
> gcc/testsuite/
> * g
On 20 August 2015 at 09:31, James Greenhalgh wrote:
>
> Hi,
>
> Steve's patch in 2013 [1] to fix the MIPS newlib/libgfortran build
> causes subtle issues for an ARM/AArch64 newlib/libgfortran build. The
> problem is that ARM/AArch64 (and SH) define a stub function for
> ftruncate, which we would p
On 20 August 2015 at 09:15, James Greenhalgh wrote:
> 2015-08-19 James Greenhalgh
>
> * common/config/aarch64/aarch64-common.c
> (AARCH64_CPU_NAME_LENGTH): Delete.
> (aarch64_option_extension): New.
> (all_extensions): Likewise.
> (processor_name_to_arch
On 18 August 2015 at 10:25, Alex Velenko wrote:
>
>
> On 31/07/15 12:04, Alex Velenko wrote:
>>
>> On 29/07/15 23:14, Jeff Law wrote:
>>>
>>> On 07/28/2015 12:18 PM, Alex Velenko wrote:
On 21/04/15 06:27, Jeff Law wrote:
>
> On 04/20/2015 01:09 AM, Shiva Chen wrote:
>>
>>
On 18 August 2015 at 09:51, Matthew Wahab wrote:
> gcc/testsuite
> 2015-08-18 Matthew Wahab
>
> * gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Adjust
> dg-options to disable LSE extensions.
> * gcc.target/aarch64/atomic-op-acq_rel.c: Likewise.
> * gcc.
On 5 August 2015 at 17:46, Renlin Li wrote:
> Hi Kyrill,
>
>
> On 30/07/15 17:08, Kyrill Tkachov wrote:
>>
>> Hi Renlin,
>>
>> On 30/07/15 16:50, Renlin Li wrote:
>>>
>>> Hi all,
>>>
>>> This insn should match the following similar rtx pattern and remove the
>>> redundant zero_extend operation if
On 28 July 2015 at 16:51, Renlin Li wrote:
> 2015-07-28 Renlin Li
>
> * gcc.target/aarch64/arm_align_max_pwr.c: Make it a compile test case,
> check the assembly.
> * gcc.target/aarch64/arm_align_max_stack_pwr.c: Likewise.
Hi,
#include
#include
Test cases should not rel
On 22 July 2015 at 18:22, Szabolcs Nagy wrote:
> 2015-07-22 Szabolcs Nagy
>
> * config/aarch64/aarch64-elf-raw.h (LINK_SPEC): Handle -h, -static,
> -shared, -symbolic, -rdynamic.
OK, this should be back ported to 5 and 4.9 aswell.
Thanks
/Marcus
On 22 July 2015 at 18:13, Szabolcs Nagy wrote:
> Same as
> https://gcc.gnu.org/ml/gcc-patches/2015-04/msg01387.html
> but for AArch64.
>
> -dynamic-linker is only passed to the linker if !static && !shared.
>
> -rdynamic handling is changed too to be consistent with arm:
> only pass -export-dynami
On 21 July 2015 at 16:37, James Greenhalgh wrote:
> On Thu, Jul 16, 2015 at 04:20:59PM +0100, Kyrill Tkachov wrote:
>> +static bool
>> +aarch64_process_one_target_attr (char *arg_str, const char* pragma_or_attr)
>> +{
>> + bool ret;
>> + bool invert = false;
>> +
>> + int len = strlen (arg_str
On 7 July 2015 at 13:33, Jiong Wang wrote:
> 2015-07-06 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Mark mem as
> READONLY and NOTRAP for PIC symbol.
>
> gcc/testsuite/
> * gcc.target/aarch64/got_mem_hoist.c: New test.
Looks, OK to me. Follow t
On 6 July 2015 at 09:20, Szabolcs Nagy wrote:
> 2015-07-06 Szabolcs Nagy
>
> * gcc.target/aarch64/fnmul-1.c: New.
> * gcc.target/aarch64/fnmul-2.c: New.
> * gcc.target/aarch64/fnmul-3.c: New.
> * gcc.target/aarch64/fnmul-4.c: New.
+float
+foo_s (float a, float
On 2 July 2015 at 14:44, Christophe Lyon wrote:
> Hi,
>
> Here is the missing test for ARM/AArch64 AdvSIMD intrinsic: vget_lane.
>
> Tested on arm, armeb, aarch64 and aarch64_be targets (using QEMU).
>
> The tests all pass, expect on armeb where vgetq_lane_s64 and
> vgetq_lane_u64 fail. I haven't
On 21 May 2015 at 17:49, Jiong Wang wrote:
> 2015-05-14 Jiong Wang
> gcc/
> * config/aarch64/aarch64.c (aarch64_print_operand): Support tls_size.
> * config/aarch64/aarch64.md (tlsle): Choose proper instruction
> sequences.
> (tlsle_): New define_insn.
> (tlsle_movsym_): Ditto.
> *
On 21 May 2015 at 17:44, Jiong Wang wrote:
>
> This patch add -mtls-size option for AArch64. This option let user to do
> finer control on code generation for various TLS model on AArch64.
>
> For example, for TLS LE, user can specify smaller tls-size, for example
> 4K which is quite usual, to let
On 20 May 2015 at 12:19, Jiong Wang wrote:
>
> Similar to the rename from SYMBOL_SMALL_TPREL to SYMBOL_TLSLE, this
> patch rename the rtl pattern name.
>
> ok for trunk?
>
> 2015-05-19 Jiong Wang
> gcc/
> * config/aarch64/aarch64.md (tlsle_small): Rename to tlsle.
> (tlsle_small_): Rename t
On 20 May 2015 at 12:21, Jiong Wang wrote:
>
> Add new unspec name UNSPEC_TLSLE, use it for all tlsle pattern.
>
> ok for trunk?
>
> 2015-05-19 Jiong Wang
>
> gcc/
> * config/aarch64/aarch64.md (UNSPEC_TLSLE): New enumeration.
> (tlsle): Use new unspec name.
> (tlsle_): Ditto.
OK /Marcus
On 20 May 2015 at 11:56, Jiong Wang wrote:
> 2015-05-19 Marcus Shawcroft
> Jiong Wang
>
> gcc/
> * config/aarch64/aarch64-protos.h (arch64_symbol_type): Rename
> SYMBOL_SMALL_TPREL to SYMBOL_TLSLE.
> (aarch64_symbol_context): Ditto.
> *
On 22 June 2015 at 17:17, Matthew Wahab wrote:
> Hello,
>
> The documentation for the ARMv8.1 +rdma option doesn't mention that enabling
> it
> also implies enabling Adv.SIMD. This patch fixes that.
>
> The documentation for the -march and -mcpu options are also a little messy,
> this
> patch trie
On 26 June 2015 at 10:23, Jiong Wang wrote:
> OK. Reworked this patch. Removed those redundant memory model check by
> adding new symbol classification. Patch splitted into two:
>
> * [1/2] Rename SYMBOL_SMALL_GOT to SYMBOL_SMALL_GOT_4G
> * [2/2] Implement -fpic for -mcmodel=small
>
> This is
On 26 June 2015 at 10:32, Jiong Wang wrote:
>
> This patch respin https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01804.html.
>
> A new symbol classification "SYMBOL_SMALL_GOT_28K" added to represent symbol
> which needs go through GOT table and it's under -fpic/-mcmodel-small. the
> "_28K"
> suffi
On 23 June 2015 at 09:49, James Greenhalgh wrote:
>
> Hi,
>
> This final patch adds support for the new command line option
> "-moverride". The purpose of this command line is to allow expert-level users
> of the compiler, and those comfortable with experimenting with the compiler,
> *unsupported*
On 23 June 2015 at 09:49, James Greenhalgh wrote:
>
> Hi,
>
> If we want to overwrite parts of this structure, we're going to need it
> to be more malleable than it is presently.
>
> Run through and remove const from each of the members, create a non-const
> tuning structure we can modify, and set
On 23 June 2015 at 09:49, James Greenhalgh wrote:
>
> Hi,
>
> The FMA steering pass should be enabled through the tuning structures
> rather than be an intrinsic property of the core. This patch moves
> the control of the pass to the tuning structures - turning it off for
> everything other than
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