On 14 October 2015 at 13:30, Wilco Dijkstra <wdijk...@arm.com> wrote: > Enable instruction fusion of dependent AESE; AESMC and AESD; AESIMC pairs. > This can give up to 2x > speedup on many AArch64 implementations. Also model the crypto instructions > on Cortex-A57 according > to the Optimization Guide. > > Passes regression tests. > > ChangeLog: > 2015-10-14 Wilco Dijkstra <wdijk...@arm.com> > > * gcc/config/aarch64/aarch64.c (cortexa53_tunings): Add AES fusion. > (cortexa57_tunings): Likewise. > (cortexa72_tunings): Likewise. > (arch_macro_fusion_pair_p): Add support for AES fusion. > * gcc/config/aarch64/aarch64-fusion-pairs.def: Add AES_AESMC entry.
These AArch64 changes are OK.... > * gcc/config/arm/aarch-common.c (aarch_crypto_can_dual_issue): > Allow virtual registers before reload so early scheduling works. > * gcc/config/arm/cortex-a57.md (cortex_a57_crypto_simple): Use > correct latency and pipeline. > (cortex_a57_crypto_complex): Likewise. > (cortex_a57_crypto_xor): Likewise. > (define_bypass): Add AES bypass. ... but wait for Ramana or Kyrill to respond on these changes before you commit. Cheers /Marcus
