This patch repurposes the code letter 's' to 'x', and 'S' to 'J'.
Also it introduces new CODE letters 'x', 's', 'S', and 'N'.
gcc/ChangeLog:
* config/arc/arc-protos.h (arc_output_addsi): Remove declaration.
(split_addsi): Likewise.
* config/arc/arc.cc (arc_print_operand):
gcc/
* common/config/arc/arc-common.cc (arc_option_optimization_table):
Remove mbbit_peephole.
* config/arc/arc.md (UNSPEC_ARC_DIRECT): Remove.
(store_direct): Likewise.
(BBIT peephole2): Likewise.
* config/arc/arc.opt (mbbit-peephole): Ignore option
The LSL16 instruction is only available if SWAP (-mswap) option is
turned on.
gcc/ChangeLog:
* config/arc/arc.cc (arc_split_mov_const): Use LSL16 only when
SWAP option is enabled.
* config/arc/arc.md (ashlsi2_cnt16): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/c
gcc/ChangeLog:
* doc/extend.texi (ARC Built-in Functions): Update documentation
with missing builtins.
---
gcc/doc/extend.texi | 55 +
1 file changed, 55 insertions(+)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index d701b4d1
Current ARC's TLS Local Dynamic model is using two anchors to access
data, namely `.tdata` and `.tbss`. This implementation is unnecessary
complicated. However, the TLS Local Dynamic model has better results
using Global Dynamic model and anchors.
gcc/ChangeLog;
* config/arc/arc.cc (arc_c
ARC has enter_s/leave_s instructions which can save/restore the entire
function context. It is not needed the millicode thunks anylonger when
compiling for size, thus, make their usage optional.
gcc/
* common/config/arc/arc-common.cc (arc_option_optimization_table):
Remove millico
gcc/
* config/arc/arc.cc (arc_check_short_reg_p): New function.
(arc_address_cost): Replace satisfies_constraint_Rcq with the
above new function.
(arc_output_addsi): Likewise.
(split_addsi): Likewise.
(split_subsi): Likewise.
* config/arc/arc.
gcc/Changelog:
* config/arc/arc.md (smaxsi3): Remove Rcw.
(sminsi3): Likewise.
(addsi3_mixed): Likewise.
(add_f_2): Likewise.
(subsi3_insn): Likewise.
(sub_f): Likewise.
(sub_n): Likewise.
(bset): Likewise.
(bxor): Likewise.
gcc/
* common/config/arc/arc-common.cc (arc_option_optimization_table):
Remove Rcq and Rcw options.
* config/arc/arc.opt (mRcq): Ignore option, preserve it for
backwards compatibility.
(mRcw): Likewise.
* doc/invoke.texi (mRcw, mRcq): Update document
gcc/ChangeLog:
* config/arc/arc.md(mulsi3_700): Remove Rcr.
(mulsi3_highpart): Likewise.
(umulsi3_highpart_i): Likewise.
(umulsi3_highpart_int): Likewise.
(macd): Likewise.
(macdu): Likewise.
* config/arc/constraints.md (Rcr): Remove it.
gcc
The enter pattern instruction contains the necessary information for
the dwarf machinery to generate the appropriate dwarf code. This
patch is fixing the register offsets related to CFA, and adds a test.
gcc/
* config/arc/arc.cc (arc_save_callee_enter): Use negative offsets.
gcc/testsuit
Max page size is defined in the ARC's BFD file, and the common page
size is also set by the appropriate binutils macros. Remove them from
LINK_SPEC.
2022-10-06 Claudiu Zissulescu
* config/arc/linux.h (LINK_SPEC): Remove max-page-size and
common-pave-size.
Signed-off-by: Claudi
Add mtune and mcpu options for ARCHS release 310a type CPU. The
mtune=release31a is designed to be used as an alternative to the
mcpu=hs4x_rel31 option.
ARCHS4x release 31a uses DSP instructions which are implemented a bit
different than mpy9. Hence, use safer mpy2 option.
gcc/
* config/ar
From: Claudiu Zissulescu
The ARC soft udivmodsi4 algorithm and as well as using umodsi3
for reduced register set configurations are wrong.
libgcc/
* config/arc/lib2funcs.c (udivmodsi4): Update AND mask.
* config/arc/lib1funcs.S (umodsi3): Don't use it for RF16
configurati
The stack pointer adjustment in interrupt epilogue is happening after
restoring the ZOL registers which is wrong. Fixing this.
gcc/
* config/arc/arc.cc (arc_expand_epilogue): Adjust the frame
pointer first when in interrupts.
gcc/testsuite/
* gcc.target/arc/interrupt-13.c:
The stack pointer adjustment in interrupt epilogue is happening after
restoring the ZOL registers which is wrong. Fixing this.
gcc/
* config/arc/arc.cc (arc_expand_epilogue): Adjust the frame
pointer first when in interrupts.
gcc/testsuite/
* gcc.target/arc/interrupt-13.c:
If the movcc comparison is not valid it triggers an assert in the
current implementation. This behavior is not needed as we can FAIL
the movcc expand pattern.
gcc/
* config/arc/arc.cc (gen_compare_reg): Return NULL_RTX if the
comparison is not valid.
* config/arc/arc.md (m
Add DWARF 2 CFA column which tracks the return address from a signal
handler context. This value must not correspond to a hard register
and must be out of the range of DWARF_FRAME_REGNUM().
gcc/
* config/arc/arc.h (DWARF_FRAME_REGNUM): Update definition.
(DWARF_FRAME_RETURN_COLUMN
When accumulator registers are available in a processor, they need to
be save onto stack durring interrupts. We were already doing so, but
the stack size was wrongly computed in the case other than ARC600.
gcc/
* config/arc/arc.c (arc_compute_frame_size): Remove condition when
co
The (u)maddsihi4 patterns are using the ARC's VMAC2H(U)
instruction with null destination, however, VMAC2H(U) doesn't
rewrite the accumulator. This patch solves the destination issue
of VMAC2H by replacing it with DMACH(U) instruction.
gcc/
* config/arc/arc.md (maddhisi4): Use a single m
Update assembly output test pattern. Take into consideration also for
which platform we do execute the test (baremetal or linux).
gcc/testsuite/ChangeLog:
* gcc.target/arc/add_n-combine.c: Update test patterns.
* gcc.target/arc/builtin_eh.c: Update test for linux platforms.
The ZOL pattern is missing modes which may lead to errors during
var_tracking. Add them.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (doloop_end): Add missing mode.
(loop_end): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 8
1 f
ARC backend is defaulting to -fcommon. This is not anylonger needed, remove it.
gcc/
2021-08-12 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_option_init_struct): Remove
fno-common reference.
* config/arc/arc.c (arc_override_options): Remove overriding of
Hi Bernhard,
Please find attached my latest patch, it includes (hopefully) all your
feedback.
Thank you for comments,
Claudiu
>From 03075b3d9194120d7adb3cdc2aa0f58e3ea9dd1d Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu
Date: Wed, 21 Oct 2020 16:11:43 +0300
Subject: [PATCH] arc: Add --with
Hi,
I would have written [[:space:]]* instead of [[:space:]]+ to handle
potentially missing space, at least after the comma but also before the
comma to avoid surprises for new names in the future.
Furthermore | alone would be [[:blank:]]* but as you prefer.
grep ... > /dev/null would be grep -
ARC processor can use LP instruction to implement zero overlay loops.
The current inplementation doesn't handle the unlikely situation when
the loop iterator is located in memory. Refurbish the loop_end insn
pattern into a define_insn_and_split pattern.
This patch is also backported to gcc11.
gc
Rework the (u)maddhisi4 patterns and use VMAC2H(U) instruction instead
of the 64bit MAC(U) instruction.
This fixes the next execute.exp failures:
arith-rand-ll.c -O2 execution test
arith-rand-ll.c -O3 execution test
pr78726.c -O2 execution test
pr78726.c -O3 executio
ARCv2HS can use a limited number of instructions to implement 64bit
moves. The VADD2 is used as a 64bit move, the LDD/STD are 64 bit loads
and stores. All those instructions are not baseline, hence we need to
provide alternatives when they are not available or cannot be generate
due to instruction
Thank you for your input.
I have made an update using grep's ERE. Please let me know if it is ok.
//Claudiu
>From 3f598e0fc9bc88c3f40f3e381c2955ab36e77ce0 Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu
Date: Wed, 21 Oct 2020 16:11:43 +0300
Subject: [PATCH] arc: Add --with-fpu support for ARC
Hi Jeff,
I would like to add spport for selecting the ARCv2 FPU extension at
configuration-time.
The --with-fpu configuration option is ignored when -mfpu compiler
option is specified.
My concern is using `grep -P` when configuring. Is that ok?
Thanks,
Claudiu
gcc/
-mm-dd Claudiu Zissules
The millicode thunks are not reduced register set safe. Disable them
for CPUs having this option on.
gcc/
2021-06-04 Claudiu Zissulescu
* config/arc/arc.c (arc_override_options): Disable millicode
thunks when RF16 is on.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/
This is a respin of an older series of three patches which I have
merged into one. The new (committed) patch is keeping the obsolete
options int .opt file marking them accrodingly for backwards
compatibility.
Remove the following obsolete options:
- munalign-prob-threshold
- malign-call
- mmixed-c
Right, we can consider this cpu switch missing in gcc11.
Best,
Claudiu
From: Vineet Gupta
Sent: Wednesday, June 2, 2021 8:36 PM
To: Claudiu Zissulescu ; gcc-patches@gcc.gnu.org
Cc: linux-snps-...@lists.infradead.org
Subject: Re: [PATCH] ARC: gcc driver default
Approved.
//Claudiu
From: Vineet Gupta
Sent: Tuesday, June 1, 2021 10:42 PM
To: gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu ;
linux-snps-...@lists.infradead.org ; Vineet
Gupta
Subject: [PATCH] ARC: gcc driver default to hs38_linux
arc700 is legacy and ther
Looks good :) You can go ahead and commit it.
Thank you for your contribution,
Claudiu
From: Kewen.Lin
Sent: Wednesday, June 2, 2021 10:43 AM
To: Claudiu Zissulescu
Cc: g...@amylaar.uk ; andrew.burg...@embecosm.com
; gcc-patches@gcc.gnu.org
Subject: [PATCH 02/1
Hi Kewen,
Maybe it is best just to remove the pattern entirely, I couldn't exercise it
myself. I was secretly hopping someone could do it.
Please can you submit a patch which removes it if it is not too much trouble?
Thanks,
Claudiu
From: Kewen.Lin
Sent: Wednesd
Hi,
Indeed, the split condition needs to be populated. However, I doubt that the
pattern in question is used by the compiler. Do you have an example where it is
exercised?
Thanks,
Claudiu
From: Kewen Lin
Sent: Wednesday, June 2, 2021 8:04 AM
To: gcc-patches@gcc
gcc/
2021-05-18 Claudiu Zissulescu
* config/arc/simdext.md (negv2si2): Remove round bracket.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/simdext.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index
Textual cleanup of the simdext.md file. Format the output assembly
instructions.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/simdext.md: Format and cleanup file.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/simdext.md | 730 +-
1 file
Add vector negate, reduc_plus_scal, vec_duplicate, vector
min/max/mult/div patterns. Besides vector negate and reduction
patterns, all the others are emulated using scalar instructions. The
reason is taking advantage of the double load/store instructions as
well as enabling the autovectorizer to f
Disable movmisalign patterns when aligned access is required.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/simdext.md (movmisalignv2hi): Allow misaligned access
only when munaligned-access option is on.
(movmisalign): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/
2021-05-10 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_handle_option): Remove dot
from string.
* config/arc/arc.c (arc_reorg): Remove underscore from string.
Signed-off-by: Claudiu Zissulescu
---
gcc/common/config/arc/arc-common.c | 2 +-
gcc/config/
ARCv2 ISA introduces special clz/ctz instructions. This patch is
adding support for them when available.
Corner case:
movr0,0x0 : (w0) r0 <= 0x *
ffsr1,r0 : (w0) r1 <= 0x001f *
flsr2,r0 : (w0) r2 <= 0x *
gcc/
2021-05-10 Claudiu Zissulescu
Add alternative register name r26 for gp register, and add
alternative register name r27 for fp register.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Add r26 and r27.
---
gcc/config/arc/arc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/
The arguments of __builtin_arc_sr are swapped in documentation. Fix it.
gcc/
2021-05-10 Claudiu Zissulescu
* doc/extend.texi (__builtin_arc_sr): Swap arguments.
Signed-off-by: Claudiu Zissulescu
---
gcc/doc/extend.texi | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
Remove unused function.
gcc/
2021-03-09 Claudiu Zissulescu
* config/arc/arc.c (arc_attr_type): Remove function.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.
From: Claudiu Zissulescu
The compiler can match mpyd.eq r0,r1,r0 as a predicated instruction,
which is incorrect. The mpyd(u) instruction takes as input two 32-bit
registers, returning into a double 64-bit even-odd register pair. For
the predicated case, the ARC instruction decoder expects the
d
Back port for gcc10
The adc/sbc patterns were unecessary spliting, remove that and
associated functions.
gcc/
2020-12-11 Claudiu Zissulescu
* config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
it.
(arc_sets_cc_p): Likewise.
(arc_need_delay): Likewise.
gcc/
2021-01-05 Claudiu Zissulescu
* config/arc/arc.md (maddsidi4_split): Use ACC_REG_FIRST.
(umaddsidi4_split): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/arc/ar
Generate MAC(U) instruction instead of MACD(U) when the destination
register is already choosen as ACCL register.
gcc/
2020-12-29 Claudiu Zissulescu
* config/arc/arc.md (maddsidi4_split): Skip macd gen, use mac insn
instead.
(macd): Update register letters.
(uma
The ARC code contains code which should only work with the old reload
pass. Such code is found in arc_secondary_reload hook, however it was
not properly quarded. Reverse the if-condition predicate such that
req_equiv_mem is called when lra is not in progress.
gcc/
2020-12-29 Claudiu Zissulescu
The REGNO_OK_FOR_BASE_P is using reg_renumber array. However, it is
not always defined. Use it only when it is defined.
gcc/
2020-12-29 Claudiu Zissulescu
* config/arc/arc.h (REGNO_OK_FOR_BASE_P): Check if defined
reg_renumber.
Signed-off-by: Claudiu Zissulescu
---
gcc/confi
gcc/testsuite
2020-12-29 Claudiu Zissulescu
* gcc.target/arc/loop-3.c: Update test pattern.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/loop-3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/arc/loop-3.c
b/gcc/tes
We need an temporary register when moving data from a cached memory to
an uncached memory. Fix this issue and add a test for it.
gcc/
2020-12-29 Claudiu Zissulescu
* config/arc/arc.c (prepare_move_operands): Use a temporary
registers when we have cached mem-to-uncached mem move
Update movdi, movdf and mov vectors not to use predicated vadd2
instructions. vadd2 is used as a "fast" move in these patterns. This
fixes a number of failures in dejagnu.
gcc/
2020-12-29 Claudiu Zissulescu
* config/arc/arc.md (movdi_insn): Update pattern, no predicated
vadd2 u
From: Claudiu Zissulescu
Replace/update ARC700 cache hazard detection. The next situations are
handled:
- There are 2 stores back2back, then 3 loads in next 3 or 4 instructions.
if 3 loads in 3 instructions then we insert 2 nops after stores.
if 3 loads in 4 instructions then we insert
From: Claudiu Zissulescu
BRcc instructions are generated quite late in the compilation
process. These instructions combines a compare with a regular
conditional branch if the result of the compare is not used
anylonger. However, when compiling for size, it is better to avoid
BRcc instructions whi
The adc/sbc patterns were unecessary spliting, remove that and
associated functions.
gcc/
2020-12-11 Claudiu Zissulescu
* config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
it.
(arc_sets_cc_p): Likewise.
(arc_need_delay): Likewise.
* config/ar
From: Claudiu Zissulescu
ARC MYP7+ instructions add MAC instructions for vector and scalar data
types. This patch adds a madd pattern for 16it datum that is using the
32bit MAC instruction, and dot_prod patterns for v4hi vector
types. The 64bit moves are also upgraded by using vadd2 instuction.
From: Claudiu Zissulescu
The compiler can match mpyd.eq r0,r1,r0 as a predicated instruction,
which is incorrect. The mpyd(u) instruction takes as input two 32-bit
registers, returning into a double 64-bit even-odd register pair. For
the predicated case, the ARC instruction decoder expects the
d
Backport to gcc9:
Enable big-endian suffixed dynamic linker per glibc multi-abi support.
And to avoid a future churn and version pairingi hassles, also allow
arc700 although glibc for ARC currently doesn't support it.
gcc/
-xx-xx Vineet Gupta
* config/arc/linux.h: GLIBC_DYNAMIC_LIN
Use HOST_WIDE_INT_PRINT_DEC macro instead of %ld for format printing.
Committed as obvious.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.c (arc_print_operand): Use
HOST_WIDE_INT_PRINT_DEC macro.
---
gcc/ChangeLog| 5 +
gcc/config/arc/arc.c | 6 +++---
2 fil
Committed as obvious.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
---
gcc/ChangeLog| 6 +-
gcc/config/arc/arc.h | 6 +++---
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 928c7
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