> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc
> (riscv_subset_list::riscv_subset_list): Init m_allow_adding_dup.
Reviewed-by: Christoph Müllner
Thanks!
> ---
> gcc/common/config/riscv/riscv-common.cc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
On Wed, Apr 2, 2025 at 5:35 AM Jeff Law wrote:
>
>
> Segher -- there's a combine question near the end...
I've created PR119587 to keep track of this issue.
BR
Christoph
>
>
> On 3/23/25 8:43 PM, Bohan Lei wrote:
> > The combine pass can generate an index like (and:DI (mult:DI (reg:DI)
> > (con
On Mon, Mar 24, 2025 at 3:44 AM Bohan Lei wrote:
>
> The combine pass can generate an index like (and:DI (mult:DI (reg:DI)
> (const_int scale)) (const_int mask)) when XTheadMemIdx is available.
> LRA may pull it out, and thus a splitter is needed when Zba is not
> available.
>
> A similar splitter
On Wed, Feb 5, 2025 at 1:29 PM Richard Biener wrote:
>
> The PR shows fold-mem-offsets taking ages and a lot of memory computing
> DU/UD chains as that requires the RD problem. The issue is not so much
> the memory required for the pruned sets but the high CFG connectivity
> (and that the CFG is
On Thu, Nov 28, 2024 at 8:37 AM Richard Biener
wrote:
> On Mon, Nov 25, 2024 at 3:28 AM Philipp Tomsich
> wrote:
> >
> > Pushed to master with the following fixups:
> > - new timevar added
> > - nits addressed
> > - whitespace fixes
>
> The pass seems to be disabled by default everywhere -
Eleftheriou
Signed-off-by: Christoph Müllner
---
gcc/doc/invoke.texi | 3 +-
gcc/opts.cc | 1 +
.../aarch64/avoid-store-forwarding-6.c| 29 +++
.../aarch64/bitfield-bitint-abi-align16.c | 28
e-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
Ensure that shuffle masks are VECTOR_CSTs.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr118487.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118487.c | 18 ++
gcc/tree-ssa-forwpr
value.
gcc/ChangeLog:
* tree-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
Eliminate redundant calls to to_constant().
Signed-off-by: Christoph Müllner
---
gcc/tree-ssa-forwprop.cc | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/tree-ssa
On Tue, Jan 14, 2025 at 2:35 PM Richard Biener wrote:
>
> On Tue, 14 Jan 2025, Christoph Müllner wrote:
>
> > On Tue, Jan 14, 2025 at 1:46 PM Richard Biener wrote:
> > >
> > > On Tue, 14 Jan 2025, Christoph Müllner wrote:
> > >
> > > > As
On Tue, Jan 14, 2025 at 1:46 PM Richard Biener wrote:
>
> On Tue, 14 Jan 2025, Christoph Müllner wrote:
>
> > As reported in PR117079, commit ab18785840d7b8 broke the test pr105493.c.
> > When looking at the generated code, we can see that the generated code
> >
.
This patch adjusts the test condition to fit how the function gets
vectorized after ab18785840d7b8 (and probably further related changes).
Signed-off-by: Christoph Müllner
PR target/117079
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr105493.c: Fix expected vectorization
---
gcc
: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118149.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
b/gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
index f471877f661..c9a427c4a07 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa
PR118149.
PR 118149
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr118149-2.c: New test.
* gcc.dg/tree-ssa/pr118149.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c | 37 ++
gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
-10.c: Rename dg-additional-options
to dg-options and add -msse2 to it.
* gcc.dg/tree-ssa/vector-11.c: Likewise.
* gcc.dg/tree-ssa/vector-8.c: Rename dg-additional-options
to dg-options.
* gcc.dg/tree-ssa/vector-9.c: Likewise.
Signed-off-by: Christoph Müllner
On Fri, Dec 20, 2024 at 4:51 PM Christoph Müllner
wrote:
>
> On Fri, Dec 20, 2024 at 4:27 PM Jakub Jelinek wrote:
> >
> > On Fri, Dec 20, 2024 at 04:22:19PM +0100, Christoph Müllner wrote:
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.dg/tree-
On Fri, Dec 20, 2024 at 4:27 PM Jakub Jelinek wrote:
>
> On Fri, Dec 20, 2024 at 04:22:19PM +0100, Christoph Müllner wrote:
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c
> > @@ -0,0 +1,37 @@
> > +/* { dg-do compile } */
> > +/* { d
-10.c: Rename dg-additional-options
to dg-options and add -msse2 to it.
* gcc.dg/tree-ssa/vector-11.c: Likewise.
* gcc.dg/tree-ssa/vector-8.c: Rename dg-additional-options
to dg-options.
* gcc.dg/tree-ssa/vector-9.c: Likewise.
Signed-off-by: Christoph Müllner
PR118149.
PR 118149
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr118149-2.c: New test.
* gcc.dg/tree-ssa/pr118149.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c | 37 ++
gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
On Fri, Dec 20, 2024 at 4:07 PM Jakub Jelinek wrote:
>
> On Fri, Dec 20, 2024 at 03:56:41PM +0100, Christoph Müllner wrote:
> > > Also, why are you using dg-additional-options in tree-ssa/ ? I think the
> > > default there is just -pedantic-errors which you don't
On Fri, Dec 20, 2024 at 3:38 PM Jakub Jelinek wrote:
>
> On Fri, Dec 20, 2024 at 02:55:51PM +0100, Christoph Müllner wrote:
> > A recent bugfix (eee2891312) for PR117830 also addressed PR118149.
> > This patch adds two test cases for PR118149.
> > These tests are diffe
PR118149.
PR 118149
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr118149-2.c: New test.
* gcc.dg/tree-ssa/pr118149.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/tree-ssa/pr118149-2.c | 36 ++
gcc/testsuite/gcc.dg/tree-ssa/pr118149.c
orwprop.cc (get_vect_selector_index_map):
(recognise_vec_perm_simplify_seq):
(calc_perm_vec_perm_simplify_seqs):
(process_vec_perm_simplify_seq_list):
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/vector-11.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.d
/config/riscv/riscv-common.cc (riscv_get_valid_option_values):
Skip adding mtune entries that are already in the list.
Signed-off-by: Christoph Müllner
---
gcc/common/config/riscv/riscv-common.cc | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/gcc/common
ingly.
Tested on x86-64.
PR117728
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/satd-hadamard.c: Restrict to aarch64 and x86-64.
* gcc.dg/tree-ssa/vector-8.c: Likewise.
* gcc.dg/tree-ssa/vector-9.c: Likewise.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg
On Thu, Nov 21, 2024 at 1:34 PM Sam James wrote:
>
> The default on trunk is --enable-checking=yes,extra (when gcc/DEV-PHASE
> contains "experimental"), otherwise it's --enable-checking=release.
>
> I personally do most testing with --enable-checking=yes,rtl,extra but
> you can do less than that i
On Thu, Nov 21, 2024 at 1:17 PM Richard Biener wrote:
>
> On Thu, 21 Nov 2024, Christoph Müllner wrote:
>
> > This extends forwprop by yet another VEC_PERM optimization:
> > It attempts to blend two isomorphic vector sequences by using the
> > redundancy in the lane uti
On Tue, Nov 19, 2024 at 2:35 PM Richard Biener
wrote:
>
> On Sat, Nov 16, 2024 at 12:00 AM Christoph Müllner
> wrote:
> >
> > This extends forwprop by yet another VEC_PERM optimization:
> > It attempts to blend two isomorphic vector sequences by using the
> > r
arch64/sve/satd-hadamard.c: New test.
Signed-off-by: Christoph Müllner
---
Changes in v6:
* Use 'unsigned int' instead of of unsigned HWI for vector indices
* Remove hash maps and replace functionality with vec<>
* Inline get_tree_def () and eliminate redundant checks
* Ensure s
On Thu, Nov 14, 2024 at 3:55 PM Christoph Müllner
wrote:
>
> On Thu, Nov 14, 2024 at 3:07 PM Richard Biener wrote:
> >
> > On Thu, 14 Nov 2024, Christoph Müllner wrote:
> >
> > > This extends forwprop by yet another VEC_PERM optimization:
> > >
hadamard.c: New test.
Signed-off-by: Christoph Müllner
---
Changes in v5:
* Improve coding style.
Changes in v4:
* Fix test condition for writing to the dump file
* Use gimple UIDs instead on expensive walks for comparing ordering.
* Ensure to not blend across assignments to SSA_NAMES.
* Restr
On Fri, Nov 15, 2024 at 10:41 PM Andrew Pinski wrote:
>
> On Fri, Nov 15, 2024 at 1:30 PM Christoph Müllner
> wrote:
> >
> > This extends forwprop by yet another VEC_PERM optimization:
> > It attempts to blend two isomorphic vector sequences by using the
> > redu
hadamard.c: New test.
Signed-off-by: Christoph Müllner
---
Changes from v3:
* Fix test condition for writing to the dump file
* Use gimple UIDs instead on expensive walks for comparing ordering.
* Ensure to not blend across assignments to SSA_NAMES.
* Restrict list to fix-sized vector with 8 en
On Thu, Nov 14, 2024 at 3:07 PM Richard Biener wrote:
>
> On Thu, 14 Nov 2024, Christoph Müllner wrote:
>
> > This extends forwprop by yet another VEC_PERM optimization:
> > It attempts to merge two isomorphic vector sequences by using the
> > redundancy in the lane uti
-10.c: New test.
* gcc.dg/tree-ssa/vector-11.c: New test.
* gcc.dg/tree-ssa/vector-8.c: New test.
* gcc.dg/tree-ssa/vector-9.c: New test.
* gcc.target/aarch64/sve/satd-hadamard.c: New test.
Signed-off-by: Christoph Müllner
---
Changes from v2:
* Moved code to tree-ssa-fo
On Wed, Oct 30, 2024 at 11:26 AM Christoph Müllner
wrote:
>
> On Fri, Oct 18, 2024 at 1:08 PM Richard Biener wrote:
> >
> > On Fri, 18 Oct 2024, Tamar Christina wrote:
> >
> > > > -Original Message-
> > > > From: Richard Biener
> >
tree-vect-perm-simplify.cc: New file.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/satd-hadamard.c: New test.
* gcc.target/aarch64/sve/satd-hadamard.c: New test.
Signed-off-by: Christoph Müllner
---
Manolis Tsamis was the patch's initial author before I took it over.
Chang
On Fri, Oct 18, 2024 at 1:08 PM Richard Biener wrote:
>
> On Fri, 18 Oct 2024, Tamar Christina wrote:
>
> > > -Original Message-
> > > From: Richard Biener
> > > Sent: Friday, October 18, 2024 11:03 AM
> > > To: Tamar Christina
>
-14.c: New test.
* gcc.target/aarch64/sve/slp-perm-14.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/vect/slp-perm-14.c | 42 +++
.../gcc.target/aarch64/sve/slp-perm-14.c | 3 +
gcc/tree-vect-slp.cc | 248 ++
3 fil
: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.dg/vect/slp-perm-13.c | 29 +++
.../gcc.target/aarch64/sve/slp-perm-13.c | 4 +++
gcc/tree-vect-slp.cc | 21 +-
3 files changed, 53 insertions(+), 1 deletion(-)
create
On Wed, Sep 18, 2024 at 3:55 PM Jeff Law wrote:
>
>
>
> On 9/10/24 10:09 AM, Christoph Müllner wrote:
>
> >> But if the generated code is just moving bits, why can't we use the
> >> standard movXX patterns for the data movement? Clearly there's
On Tue, Sep 10, 2024 at 5:25 PM Jeff Law wrote:
>
>
>
> On 9/8/24 3:28 PM, Christoph Müllner wrote:
> > On Sat, Sep 7, 2024 at 7:08 PM Jeff Law wrote:
> >>
> >>
> >>
> >> On 9/6/24 5:32 AM, Jin Ma wrote:
> >>> In th
On Sat, Sep 7, 2024 at 7:08 PM Jeff Law wrote:
>
>
>
> On 9/6/24 5:32 AM, Jin Ma wrote:
> > In the process of DF to SI, we generally use "unsigned_fix" rather than
> > "truncate" for conversion. Although this has no effect in general,
> > unexpected ICE often occurs when precise semantic analysis
On Wed, Aug 7, 2024 at 4:48 PM Jeff Law wrote:
>
>
>
> On 8/7/24 12:27 AM, Christoph Müllner wrote:
> > Test file xtheadfmemidx-medany.c has been added in b79cd204c780 as a
> > test case that provoked an ICE when loading DFmode registers via two
> > SImode register
y.c: Likewise.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/constraints.md | 9 +
gcc/config/riscv/riscv.md| 4 ++--
.../gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c| 3 ++-
.../gcc.target/riscv/xtheadfmemidx-zfa-me
: Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr116131.c: New test.
Reported-by: Patrick O'Neill
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/thead.cc | 88 -
gcc/config/riscv/thead.md | 417 --
gcc/tests
gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c: ...here.
* gcc.target/riscv/xtheadfmemidx-zfa-medany.c: New test.
Signed-off-by: Christoph Müllner
---
...any.c => xtheadfmemidx-xtheadfmv-medany.c} | 5 ++-
.../riscv/xtheadfmemidx-zfa-medany.c | 39 +++
2 files changed,
On Tue, Aug 6, 2024 at 12:29 AM Patrick O'Neill wrote:
>
> This fixes typos in function names and executed code.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-target-attr.cc (num_occurences_in_str): Rename...
> (num_occurrences_in_str): here.
> (riscv_process_target_attr): Up
), jeffreya...@gmail.com wrote:
> >> >
> >> >
> >> > On 7/25/24 9:06 AM, Christoph Müllner wrote:
> >> >> Ok, also to backport to GCC 14?
> >> > Yes, of course.
> >>
> >> I'm OK with that, but according to the latest status report
>
On Mon, Jul 29, 2024 at 5:26 AM Jiawei wrote:
>
> This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
> which depend on the base RISC-V Profiles support[2].
>
> [1]
> https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
> [2] https://gcc.gnu.org/p
SI (reg:DI))) for RV32.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr116131.c: New test.
Reported-by: Patrick O'Neill
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/thead.cc | 13 +
gcc/testsuite/gcc.target/riscv/pr116131.c | 15 +++
2 fi
On Thu, Jul 25, 2024 at 5:19 PM Palmer Dabbelt wrote:
>
> On Thu, 25 Jul 2024 08:10:25 PDT (-0700), jeffreya...@gmail.com wrote:
> >
> >
> > On 7/25/24 9:06 AM, Christoph Müllner wrote:
> >> Ok, also to backport to GCC 14?
> > Yes, of course.
>
>
Ok, also to backport to GCC 14?
On Thu, Jul 25, 2024 at 4:56 PM Jeff Law wrote:
>
>
>
> On 7/24/24 9:15 AM, Christoph Müllner wrote:
> > auto_inc_dec (-O3) performs optimizations like the following
> > if RVV and XTheadMemIdx is enabled.
> >
> > (insn 2
Fix mode test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr116033.c: New test.
Reported-by: Patrick O'Neill
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/thead.cc | 6 ++
gcc/testsuite/gcc.target/riscv/pr116033.c | 16
2 f
On Wed, Jul 24, 2024 at 3:57 PM Jeff Law wrote:
>
>
>
> On 7/24/24 7:31 AM, Christoph Müllner wrote:
> > When enabling XTheadMemIdx, we enable the pre- and post-modify
> > addressing modes in the RISC-V backend.
> > Unfortunately, the auto_inc_dec pass will th
* gcc.target/riscv/pr116033-3.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv.h| 6 ++--
gcc/testsuite/gcc.target/riscv/pr116033-1.c | 40 +
gcc/testsuite/gcc.target/riscv/pr116033-2.c | 40 +
gcc/testsu
Is it OK to backport to GCC 14 (patch applies cleanly, test is running)?
On Wed, Jul 24, 2024 at 9:25 AM Kito Cheng wrote:
>
> LGTM :)
>
> On Wed, Jul 24, 2024 at 3:16 PM Christoph Müllner
> wrote:
> >
> > It is possible that the Zba optimization pattern zero_exten
gcc.target/riscv/pr116035-2.c: New test.
Reported-by: Patrick O'Neill
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/bitmanip.md| 2 +-
gcc/testsuite/gcc.target/riscv/pr116035-1.c | 29 +
gcc/testsuite/gcc.target/riscv/pr116035-2.c | 26
gt; Signed-off-by: Edwin Lu
> ---
> gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Christoph Müllner
In my defense, I tested the following combinations:
= Summary of gcc testsuite =
* gcc.target/riscv/target-attr-12.c: New test.
* gcc.target/riscv/target-attr-13.c: New test.
* gcc.target/riscv/target-attr-14.c: New test.
* gcc.target/riscv/target-attr-15.c: New test.
(cherry picked from commit aa8e2de78cae4dca7f9b0efe0685f3382f9ecb9a)
Signed-off-by: Christoph Müllner
---
tring): Replace duplicated code by a call to
riscv_set_arch_by_subset_list.
(cherry picked from commit 85fa334fbcaa8e4b98ab197a8c9410dde87f0ae3)
Signed-off-by: Christoph Müllner
---
gcc/common/config/riscv/riscv-common.cc | 32 +
1 file changed, 6 insertions(+
d1a3fd6341a4)
Signed-off-by: Christoph Müllner
---
gcc/common/config/riscv/riscv-common.cc | 17 +++
gcc/config/riscv/riscv-subset.h | 5
gcc/config/riscv/riscv-target-attr.cc | 3 ++
gcc/testsuite/gcc.target/riscv/pr115554.c | 2 --
.../gcc.target/
from commit 5ef0b7d2048a7142174ee3e8e021fc1a9c3e3334)
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv-target-attr.cc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-target-attr.cc
b/gcc/config/riscv/riscv-target-attr.cc
index 19eb7b
isaligned.c: Remove
"-fno-fat-lto-objects" from skip condition.
* gcc.target/riscv/pr93202.c: Likewise.
(cherry picked from commit 0717d50fc4ff983b79093bdef43b04e4584cc3cd)
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c | 2 +-
On Tue, Jul 16, 2024 at 4:45 AM Kito Cheng wrote:
>
> On Tue, Jul 16, 2024 at 1:09 AM Christoph Müllner
> wrote:
> >
> > On Mon, Jul 15, 2024 at 11:10 AM Kito Cheng wrote:
> > >
> > > LGTM, and could you backport this to the GCC 14 branch as well?
> &g
On Tue, Jul 9, 2024 at 8:50 PM Christoph Müllner
> wrote:
> >
> > The target-arch attribute handling in RISC-V is only a few months old,
> > but already saw a rewrite (9941f0295a14), which addressed an important
> > issue. This rewrite introduced a hash table in the back
64:
https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/aarch64/aarch64.cc;h=7f0cc47d0f071de9297068baa85c6d5fc4d7fa5b;hb=HEAD#l19408
So, my assumption was that it should be fine for RISC-V as well.
However, I won't insist on this patch.
>
> On Tue, Jul 9, 2024 at 8:48 PM Christ
riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch):
Allow adding enabled extensions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr115554.c: Change expected fail to expected pass.
* gcc.target/riscv/target-attr-16.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/commo
:
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch):
Replace new + std::unique_ptr by alloca().
(riscv_process_one_target_attr): Likewise.
(riscv_process_target_attr): Likewise.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv-target
: New test.
* gcc.target/riscv/target-attr-13.c: New test.
* gcc.target/riscv/target-attr-14.c: New test.
* gcc.target/riscv/target-attr-15.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/common/config/riscv/riscv-common.cc | 113 +-
gcc/con
ff-by: Christoph Müllner
---
gcc/config/riscv/riscv-target-attr.cc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-target-attr.cc
b/gcc/config/riscv/riscv-target-attr.cc
index e59cc53f23c6..3d7753f64574 100644
--- a/gcc/config/riscv/riscv-target-attr.cc
while
analysing a build issue with a patchset to introduce optimized string
processing routines for RISC-V in glibc. See also:
https://sourceware.org/pipermail/libc-alpha/2024-June/157627.html
Christoph Müllner (6):
RISC-V: testsuite: Properly gate LTO tests
RISC-V: Deduplicate arch subset list proce
tring): Replace duplicated code by a call to
riscv_set_arch_by_subset_list.
Signed-off-by: Christoph Müllner
---
gcc/common/config/riscv/riscv-common.cc | 32 +
1 file changed, 6 insertions(+), 26 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
aligned.c: Remove
"-fno-fat-lto-objects" from skip condition.
* gcc.target/riscv/pr93202.c: Likewise.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c | 2 +-
gcc/testsuite/gcc.target/riscv/pr93202.c | 2 +-
2 files
Hi Jeff,
the test should probably also be skipped on -Oz:
=== gcc: Unexpected fails for rv64imafdc lp64d medlow ===
FAIL: gcc.target/riscv/zbs-ext-2.c -Oz scan-assembler-times andi\t 1
FAIL: gcc.target/riscv/zbs-ext-2.c -Oz scan-assembler-times andn\t 1
FAIL: gcc.target/ris
On Sat, Jun 15, 2024, 08:25 Kito Cheng wrote:
> Oooops, thanks for catching that! It's LGTM:)
>
Also OK for the GCC 14 branch?
> Christoph Müllner 於 2024年6月15日 週六 04:58 寫道：
>
>> I triggered an ICE on Ubuntu 24.04 when compiling code that uses
>> function attribu
v-target-attr.cc
(riscv_target_attr_parser::parse_arch):
Fix allocation size of buffer.
(riscv_process_one_target_attr): Likewise.
(riscv_process_target_attr): Likewise.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv-target-attr.cc | 6 +++---
1 file changed, 3 insertions
ver, we need to set options to the
defaults without '-ansi', because the included test file uses the
'asm' keyword, which is not part of ANSI C.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmpmemsi-1.c: Drop options.
* gcc.target/riscv/cpymemsi-1.c: Likewise
On Thu, May 16, 2024 at 10:03 AM Kito Cheng wrote:
>
> Just one minor question
>
> > diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> > b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> > index 983b564ccaf..aee54d9aa00 100644
> > --- a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> > +++ b
On Wed, May 15, 2024 at 10:22 PM Patrick O'Neill wrote:
>
>
> On 5/14/24 22:00, Christoph Müllner wrote:
>
> On Fri, May 10, 2024 at 6:01 AM Patrick O'Neill wrote:
>
> Hi Christoph,
>
> cpymemsi-1.c fails on a subset of newlib targets.
>
> "
si-1.c: Drop march-string.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.target/riscv/cpymemsi-1.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
index 983b564ccaf..aee54d9aa00 1
On Wed, May 15, 2024 at 3:05 PM Jeff Law wrote:
>
>
>
> On 5/15/24 12:48 AM, Christoph Müllner wrote:
> > Emitting a DI pattern won't find a match for rv32 and manifests in
> > the failing test case gcc.target/riscv/cmo-zicboz-zic64-1.c.
> > Let's fix th
On Sat, May 11, 2024 at 12:32 AM Jeff Law wrote:
>
>
>
> On 5/7/24 11:17 PM, Christoph Müllner wrote:
> > The RISC-V cpymemsi expansion is called, whenever the by-pieces
> > infrastructure will not take care of the builtin expansion.
> > The code emitted by the by-p
We had an issue when expanding via cmo-zero for RV32.
This was fixed upstream, but we don't have a RV32 test.
Therefore, this patch introduces such a test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32.
Signed-off-by: Christoph Mü
On Wed, May 15, 2024 at 9:14 AM Kito Cheng wrote:
>
> LGTM :)
Jeff already committed a fix before, which also disables the test for rv32.
I'll send up a follow-up patch to enable the test for rv32.
>
> On Wed, May 15, 2024 at 2:48 PM Christoph Müllner
> wrote:
> >
On Thu, May 9, 2024 at 4:50 PM Jeff Law wrote:
>
>
>
> On 5/7/24 11:52 PM, Christoph Müllner wrote:
> > GCC has a generic cmpmemsi expansion via the by-pieces framework,
> > which shows some room for target-specific optimizations.
> > E.g. for comparing two ali
ttern.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv-string.cc | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index a4c7f27d904..488e781aea3 100644
--- a/gcc/config/riscv/riscv-string.cc
msi): New cmpmem expansion.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmpmemsi-1.c: New test.
* gcc.target/riscv/cmpmemsi-2.c: New test.
* gcc.target/riscv/cmpmemsi-3.c: New test.
* gcc.target/riscv/cmpmemsi.c: New test.
Signed-off-by: Christoph Müllner
---
-string.cc (riscv_expand_block_clear_zicboz_zic64b):
Fix expansion for rv32.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv-string.cc | 5 ++-
.../gcc.target/riscv/cmo-zicboz-zic64-1.
s
might be the issue?
Thanks,
Christoph
>
> Thanks,
>
> Patrick
>
> On 5/7/24 22:52, Christoph Müllner wrote:
> > cpymemsi expansion was available for RISC-V since the initial port.
> > However, there are not tests to detect regression.
> > This patch adds suc
On Wed, May 8, 2024 at 3:48 PM Jeff Law wrote:
>
>
>
> On 5/8/24 1:36 AM, Christoph Müllner wrote:
> > The lshr3_zero_extend_4 pattern targets bit extraction
> > with zero-extension. This pattern represents the canonical form
> > of zero-extensions of a logical
On Mon, May 6, 2024 at 11:43 PM Vineet Gupta wrote:
>
>
>
> On 5/6/24 13:40, Christoph Müllner wrote:
> > The combiner attempts to optimize a zero-extension of a logical right shift
> > using zero_extract. We already utilize this optimization for those cases
>
On Mon, May 6, 2024 at 11:24 PM Jeff Law wrote:
>
>
>
> On 5/6/24 2:40 PM, Christoph Müllner wrote:
> > The combiner attempts to optimize a zero-extension of a logical right shift
> > using zero_extract. We already utilize this optimization for those cases
> > that r
arget/riscv/pr111501.c: New test.
* gcc.target/riscv/zero-extend-rshift-32.c: New test.
* gcc.target/riscv/zero-extend-rshift-64.c: New test.
* gcc.target/riscv/zero-extend-rshift.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv.md
rget/riscv/sign-extend-rshift.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/iterators.md | 4 +
gcc/config/riscv/riscv.md | 25 ++--
.../gcc.target/riscv/extend-shift-helpers.h | 20 +++
.../gcc.target/riscv/sign-extend-rshift-3
onfig/riscv/riscv.md (*lshrsi3_zero_extend_2): Rename to...
(*lshrsi3_extend_2):...this and add support for sign-extensions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sign-extend-1.c: Test sraiw 24 and sraiw 16.
Signed-off-by: Christoph Müllner
---
gcc/confi
We already optimize a sign-extension of a right-shift by 31 in
si3_extend. Let's add a test for that (similar to
zero-extend-1.c).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sign-extend-1.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.target/riscv/sign-ext
scv/cmpmemsi-1.c: New test.
* gcc.target/riscv/cmpmemsi-2.c: New test.
* gcc.target/riscv/cmpmemsi-3.c: New test.
* gcc.target/riscv/cmpmemsi.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-string
: Christoph Müllner
---
gcc/testsuite/gcc.target/riscv/cpymemsi-1.c | 9 +
gcc/testsuite/gcc.target/riscv/cpymemsi-2.c | 42
gcc/testsuite/gcc.target/riscv/cpymemsi-3.c | 43 +
gcc/testsuite/gcc.target/riscv/cpymemsi.c | 22 +++
4 files changed
.
(riscv_expand_block_clear): New RISC-V block-clear expansion function.
* config/riscv/riscv.md (setmem): New setmem expansion.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicboz-zic64-1.c: New test.
Signed-off-by: Christoph Müllner
---
gcc/config/riscv/riscv-protos.h
/cmo-zicbop-1.c: Likewise.
* gcc.target/riscv/cmo-zicbop-2.c: Likewise.
* gcc.target/riscv/cmo-zicboz-1.c: Likewise.
* gcc.target/riscv/cmo-zicboz-2.c: Likewise.
Signed-off-by: Christoph Müllner
---
gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 6 +++---
gcc/testsuite/gcc.t
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