Seems CI still fail:
https://github.com/ewlu/gcc-precommit-ci/issues/3282#issue-3030037257
Executing on host:
/home/ewlu/precommit-08/_work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/build/build-gcc-newlib-stage2/gcc/xgcc
-B/home/ewlu/pre
commit-08/_work/gcc-precommit-ci/gcc-precommit-
On Mon, Apr 28, 2025 at 07:27:31PM +0200, Josef Melcr wrote:
> As for the attribute, I am honestly not too sure about what to do, as clang
> is
> not consistent in with its own indexing, be it with the unknown values, or
> with
> 'this'. I've tried to remain consistent with GCC's indexing style. I
On Wed, Apr 30, 2025 at 12:00 AM Andrew MacLeod wrote:
>
>
> On 4/28/25 17:26, Andrew MacLeod wrote:
> > I have committed this patch to trunk after bootstrap/regression
> > testing again on trunk.
> >
> > I'll get to gcc14/15 once I flush the current queue.
> >
> > Andrew
> >
> > On 1/23/25 04:39,
On Wed, Apr 30, 2025 at 12:00 AM Andrew MacLeod wrote:
>
>
> On 4/28/25 17:26, Andrew MacLeod wrote:
> > I have committed this patch to trunk after bootstrap/regression
> > testing again on trunk.
> >
> > I'll get to gcc14/15 once I flush the current queue.
> >
> > Andrew
> >
> >
> > On 4/17/25 06
On Wed, Apr 30, 2025 at 12:00 AM Andrew MacLeod wrote:
>
>
> On 3/28/25 10:36, Andrew MacLeod wrote:
> > On 3/28/25 03:19, Richard Biener wrote:
> >> On Fri, Mar 28, 2025 at 12:28 AM Andrew MacLeod
> >> wrote:
> >>> This patch fixes both 119471 and the remainder of 110992.
> >>>
> >>> At issue is
On Tue, Apr 29, 2025 at 4:25 PM Andrew Pinski wrote:
>
> When we have an empty function, things can go wrong with
> cfi_startproc/cfi_endproc and a few other things like exceptions. So if
> the only thing the function does is a call to __builtin_unreachable,
> let's expand that to a __builtin_trap
---
gcc/sreal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/sreal.h b/gcc/sreal.h
index 8700807a131..c5aef1f3a82 100644
--- a/gcc/sreal.h
+++ b/gcc/sreal.h
@@ -118,7 +118,7 @@ public:
return min;
}
- /* Global minimum sreal can hold. */
+ /* Global maximum
On Tue, Apr 29, 2025 at 3:53 PM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 9:34 PM Richard Biener
> wrote:
> >
> > On Tue, Apr 29, 2025 at 2:33 PM H.J. Lu wrote:
> > >
> > > On Tue, Apr 29, 2025 at 6:46 PM Richard Biener
> > > wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wro
Because MIPS function symbol is generated in the prologue function,
this nop generation should be done in prologue.
OK for trunk?
PR target/99217
gcc/ChangeLog:
* config/mips/mips.cc (mips_start_function_definition):
Implements the functionality of '-fpatchable-function-e
On 29/04/2025 08:55, Jonathan Wakely wrote:
On Mon, 28 Apr 2025, 21:37 François Dumont, wrote:
Much better indeed, there is only the aligned_storage adaptation left.
It will simplify my big versioned namespace patch to use cxx11
abi, very
nice !
libstdc++: [_GLIBCX
Hi,
As we will be landing patches for extends, this will become a separate
patch series.
I would prefer, if you could commit per layout, and start with layout_right
(default)
I try to provide prompt responses, so if that works better for you, you can
post a patch
only with this layout first, as mo
Although we already try to set the mode needed to FRM_DYN after a function call,
there are still some corner cases where both FRM_DYN and FRM_DYN_CALL may appear
on incoming edges.
Therefore, we use TARGET_MODE_CONFLUENCE to tell GCC that FRM_DYN, FRM_DYN_CALL,
and FRM_DYN_EXIT modes are compatib
LGTM
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2025-04-29 11:35
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong; pan2.li;
vineetg
CC: Kito Cheng
Subject: [PATCH] RISC-V: Allow different dynamic floating point mode to be
merged [PR119832]
Although we already try to set
The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-19.c: set the march to rv64
Kind of surprise that this change doesn't make any of the existing frm tests
fail(given we have many frm tests).
No comment from myside.
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, April 29, 2025 11:35 AM
To: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; pal...@dabbelt.com
Random-typo-spotting-mode activated:
On Sat, 19 Apr 2025, Andrew Pinski wrote:
> +++ b/gcc/testsuite/gcc.dg/tree-ssa/calloc-10.c
> +/* zeroing out via a CONSTRUCTOR should be treated similarly as a msmet and
"memset"
> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/calloc-11.c
> b/gcc/testsuite/gc
Thanks Robin for help.
> as I suggested initializes total with an estimate of the mode size (total = 8
> for me) before we get to riscv_rtx_cost. This makes the rest of the
> costs (which we assume to be relative to 4) inaccurate.
I see, that explains how cost value 8 comes from.
> Then we sho
On Tue, Apr 29, 2025 at 11:52 PM Jonathan Wakely wrote:
> On Tue, 29 Apr 2025 at 14:55, Tomasz Kaminski wrote:
> >
> >
> >
> > On Tue, Apr 29, 2025 at 2:55 PM Luc Grosheintz
> wrote:
> >>
> >> This implements std::extents from according to N4950 and
> >> contains partial progress towards PR107
The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-19.c: set the march to rv64
LGTM, but pending for the spec ratified, also a minor comment is the
link seems dead, we may use
https://github.com/riscv/riscv-isa-manual/pull/1907 instead
On Fri, Mar 21, 2025 at 8:56 AM Mingzhu Yan wrote:
>
> This patch support svrsw60t59b extension[1].
> To enable GCC to recognize and process
Hi Dongyan:
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c
> b/gcc/testsuite/gcc.target/riscv/arch-46.c
> new file mode 100644
> index ..fb2bdf72597f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-46.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile } */
> +/* { dg-optio
> -Original Message-
> From: Jan Hubicka
> Sent: Wednesday, April 30, 2025 4:11 AM
> To: gcc-patches@gcc.gnu.org; Liu, Hongtao ;
> ro...@nextmovesoftware.com; ubiz...@gmail.com
> Subject: Make ix86 cost of VEC_SELECT equivalent to SUBREG same as of
> SUBREG
>
> Hi,
> this patch (partly
On 3/28/25 05:25, Jakub Jelinek wrote:
On Fri, Mar 28, 2025 at 08:12:35AM +0100, Richard Biener wrote:
On Thu, Mar 27, 2025 at 8:14 PM Andrew MacLeod wrote:
This patch backports the ASSUME support that was rewritten in GCC 15.
Its slightly more complicated than the port to GCC 14 was in that
On 4/28/25 17:26, Andrew MacLeod wrote:
I have committed this patch to trunk after bootstrap/regression
testing again on trunk.
I'll get to gcc14/15 once I flush the current queue.
Andrew
On 1/23/25 04:39, Richard Biener wrote:
On Wed, Jan 22, 2025 at 12:49 AM Andrew MacLeod
wrote:
This p
On 4/28/25 17:26, Andrew MacLeod wrote:
I have committed this patch to trunk after bootstrap/regression
testing again on trunk.
I'll get to gcc14/15 once I flush the current queue.
Andrew
On 4/17/25 06:44, Richard Biener wrote:
On Wed, Apr 16, 2025 at 10:55 PM Andrew MacLeod
wrote:
This
On 3/28/25 10:36, Andrew MacLeod wrote:
On 3/28/25 03:19, Richard Biener wrote:
On Fri, Mar 28, 2025 at 12:28 AM Andrew MacLeod
wrote:
This patch fixes both 119471 and the remainder of 110992.
At issue is we do not recognize that if
"a * b != 0" , then neither "a" nor "b" can be zero.
On Tue, 29 Apr 2025 at 14:55, Tomasz Kaminski wrote:
>
>
>
> On Tue, Apr 29, 2025 at 2:55 PM Luc Grosheintz
> wrote:
>>
>> This implements std::extents from according to N4950 and
>> contains partial progress towards PR107761.
>>
>> If an extent changes its type, there's a precondition in the s
AREG, DREG, CREG and AD_REGS are kept in ix86_class_likely_spilled_p to
avoid the following regressions with
$ make check RUNTESTFLAGS="--target_board='unix{-m32,}'"
FAIL: gcc.dg/pr105911.c (internal compiler error: in lra_split_hard_reg_for, at
lra-assigns.cc:1863)
FAIL: gcc.dg/pr105911.c (test
SSE_FIRST_REG was added to CLASS_LIKELY_SPILLED_P, which became
TARGET_CLASS_LIKELY_SPILLED_P, for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=40470
Since RA has been improved and xmm0 is a commonly used register, remove
SSE_FIRST_REG from ix86_class_likely_spilled_p to improve xmm0 codegen:
1.
SMALL_REGISTER_CLASSES was added by
commit c98f874233428d7e6ba83def7842fd703ac0ddf1
Author: James Van Artsdalen
Date: Sun Feb 9 13:28:48 1992 +
Initial revision
which became TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P. It is false from
day 1 for i386. Since x86-64 doubles the number of
> > so gain is the difference of runtime of integer variant compared to
> > vector vairant and cost are the extra int->see and sse->int conversions
> > needed?
> >
> > If you scale everything by a BB frequency, you will get a weird
> > behaviour if chain happens to consist only of instructions in
Hi,
as noticed by Martin Jambor, I introduced a bug while simplifying
cs_interesting_for_ipcp_p and reversed condition for
flag_profile_partial_training. Also I noticed that we probably want to
consider calls with unintialized counts for cloning so the pass does somehting
with -fno-guess-branch-pr
> > > I am generally trying to get rid of remaing uses of REG_FREQ since the
> > > 1 based fixed point arithmetics iot always working that well.
> > >
> > > You can do the sums in profile_count type (doing something reasonable
> > > when count is uninitialized) and then convert it to sreal for
Hi,
this patch (partly) solves problem in PR119900 where changing ix86_size_cost
of chap SSE instruction from 2 bytes to 4 bytes regresses imagemagick with PGO
(119% on core and 54% on Zen)
There is an interesting chain of problems
1) the train run of the SPEC2017 imagick is wrong and it does not
Currently the GLIBCXX_ENABLE_ATOMIC_BUILTINS macro checks for a variety
of __atomic built-ins for bool, short and int. If all those checks pass,
then it defines _GLIBCXX_ATOMIC_BUILTINS and uses the definitions from
config/cpu/generic/atomicity_builtins/atomicity.h for the non-inline
versions of __
> > I am generally trying to get rid of remaing uses of REG_FREQ since the
> > 1 based fixed point arithmetics iot always working that well.
> >
> > You can do the sums in profile_count type (doing something reasonable
> > when count is uninitialized) and then convert it to sreal for the final
On Tue, 2025-04-29 at 21:51 +0200, Marc Poulhiès wrote:
> Having both an enum and a variable with the same name triggers an
> error with
> gcc 5.
>
> exploded-graph.h:351:29: error: ‘status’ is not a class, namespace,
> or enumeration
>
> gcc/analyzer/ChangeLog:
> * exploded-graph.h (set_
Hi,
In an earlier change, a wrapper function was added to set
CONSTRUCTOR_ZERO_PADDING_BITS on all CONSTRUCTOR nodes. This removes all
the old generated calls to built-in memset and memcpy as zero padding is
now taken care of by the middle-end.
The remaining constructors that weren't getting zero
This is a non-standard feature test macro only used internally, so use
the new no_stdname property for it.
libstdc++-v3/ChangeLog:
* include/bits/version.def (make_obj_using_allocator): Use
no_stdname.
* include/bits/version.h: Regenerate.
---
Tested x86_64-linux. Pushed
Having both an enum and a variable with the same name triggers an error with
gcc 5.
exploded-graph.h:351:29: error: ‘status’ is not a class, namespace, or
enumeration
gcc/analyzer/ChangeLog:
* exploded-graph.h (set_status): Rename parameter.
* constraint-manager.cc (bound::ensu
s/padwidht/padwidth/ in the summary line
On 26/04/25 06:56 +0200, Tomasz Kamiński wrote:
The _Padding_sink was behaving incorrectly, when the predicated width (based on
predicted?
code units count) was higher than _M_maxwidth, but lower than _M_padwidth.
In this case _M_update() returned w
On Tue, Apr 29, 2025 at 02:47:21PM +0100, Alice Carlotti wrote:
> This demonstrates a clear benefit to make the makefile rules automatic. I
> thought this might be quite tricky, but it turns out to be fairly
> straightforward.
Actually, it turns out I missed at least one more thing that's needed,
This adds an automatic downloader for the latest test results from
the mailing list archive and supports diffing test_summary to it.
Useful if you don't want to run your own baseline.
contrib/ChangeLog:
* diffsummary.py: New file.
---
contrib/diffsummary.py | 104
Pengfei Li writes:
> This patch transforms RTL expressions of the form (subreg (not X)) into
> (not (subreg X)) if the subreg is an operand of another binary logical
> operation. This transformation can expose opportunities to combine more
> logical operations.
>
> For example, it improves the cod
Konstantinos Eleftheriou writes:
> During the base register initialization, when we are eliminating the load
> instruction, we were calling `emit_move_insn` on registers of the same
> size but of different mode in some cases, causing an ICE.
>
> This patch fixes this, by adding a check for the mod
Jennifer Schmitz writes:
> If -msve-vector-bits=128, SVE loads and stores (LD1 and ST1) with a
> ptrue predicate can be replaced by neon instructions (LDR and STR),
> thus avoiding the predicate altogether. This also enables formation of
> LDP/STP pairs.
>
> For example, the test cases
>
> svfloat
0x67 prefix is applied before segment register. That is in
rep movsq %gs:(%esi), (%edi)
the address is %gs + %esi. In case Pmode != word_mode (x32 with a default
-maddress-mode=short) instructions should not allow segment override prefixes.
Also, remove explicit addr32 prefix from asm templa
> On 29 Apr 2025, at 14:03, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jennifer Schmitz writes:
>> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
>> index f7bccf532f8..1c06b8528e9 100644
>> --- a/gcc/config/aarch64/
On Tue, Apr 29, 2025 at 4:11 PM Jonathan Wakely wrote:
> This will hardly make a dent in the very slow compile times for
> but it seems worth doing anyway.
>
> libstdc++-v3/ChangeLog:
>
> * include/bits/regex_compiler.h: Replace _GLIBCXX17_CONSTEXPR
> with constexpr and disable d
When we have an empty function, things can go wrong with
cfi_startproc/cfi_endproc and a few other things like exceptions. So if
the only thing the function does is a call to __builtin_unreachable,
let's expand that to a __builtin_trap instead. For most targets that
is one instruction wide so it wo
This will hardly make a dent in the very slow compile times for
but it seems worth doing anyway.
libstdc++-v3/ChangeLog:
* include/bits/regex_compiler.h: Replace _GLIBCXX17_CONSTEXPR
with constexpr and disable diagnostics with pragmas.
(_AnyMatcher::operator()): Use const
On Tue, 29 Apr 2025 at 13:56, Luc Grosheintz wrote:
>
> Implements the parts of layout_left that don't depend on any of the
> other layouts.
>
> libstdc++/ChangeLog:
N.B. this needs to be libstdc++-v3/Changelog with "-v3", or the git
hooks will reject it. Similarly in patches 6/10 to 10/10.
Ther
On Tue, Apr 29, 2025 at 2:55 PM Luc Grosheintz
wrote:
> This implements std::extents from according to N4950 and
> contains partial progress towards PR107761.
>
> If an extent changes its type, there's a precondition in the standard,
> that the value is representable in the target integer type.
On Tue, Apr 29, 2025 at 9:34 PM Richard Biener
wrote:
>
> On Tue, Apr 29, 2025 at 2:33 PM H.J. Lu wrote:
> >
> > On Tue, Apr 29, 2025 at 6:46 PM Richard Biener
> > wrote:
> > >
> > > On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
>
The following adds checks that when we search for a vector stmt
insert location we arrive at one where all required operand defs
are dominating the insert location. At the moment any such
failure only blows up during SSA verification.
There's the long-standing issue that we do not verify there
ex
This also improves consistency of the compile commands, and eliminates
an ALL_SPPFLAGS typo.
gcc/ChangeLog:
* config/aarch64/t-aarch64: Use $(COMPILE) and $(POSTCOMPILE)
diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64
index
59571948479c0857df2cca70b18df6c5d9a72
On Tue, 29 Apr 2025 at 13:54, Luc Grosheintz wrote:
>
> This implements std::extents from according to N4950 and
> contains partial progress towards PR107761.
>
> If an extent changes its type, there's a precondition in the standard,
> that the value is representable in the target integer type. T
The following makes get_later_stmt handle stmts from different
basic-blocks in the case they are orderd and otherwise asserts.
Bootstrap/regtest running on x86_64-unknown-linux-gnu.
* tree-vectorizer.h (get_later_stmt): Robustify against
stmts in different BBs, assert when they ar
The change to gcc/configure is a hack to illustrate where we need extra
arguments available. If the rest of the change is desirable, then we
could define a new variable to include these extra directories.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index
6dbe880c9d45369a0128d79f5fa30ca07faf953
This might miss some dependencies when doing an incremental build where
the previous build did not include generated dependency files, and the
.cc file has not subsequently changed (but another dependency has).
gcc/ChangeLog:
* config/aarch64/t-aarch64: Remove explicit .o dependencies.
This RFC series shows the steps that I believe are relevant to using automatic
make depencies, and optionally automatic make rules, in the aarch64 backend. I
believe the same steps and caveats would apply to other backends as well.
This builds upon the work by Tom Tromey in 2013 (see e.g. [1]), w
I see, let the vec_dup enter the rtx_cost again to append the total to vmv, I
have a try testing. For example with below change:
+ switch (rcode)
+ {
+ case VEC_DUPLICATE:
+ *total += get_vector_costs ()->regmove->GR2VR * COSTS_N_INSNS
(1);
+ break;
+
On Tue, Apr 29, 2025 at 2:33 PM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 6:46 PM Richard Biener
> wrote:
> >
> > On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wrote:
> > >
> > > On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
> > > wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 10:48 AM H.J. Lu wr
On Tue, 29 Apr 2025 at 13:54, Luc Grosheintz wrote:
>
> This implements std::extents from according to N4950 and
> contains partial progress towards PR107761.
>
> If an extent changes its type, there's a precondition in the standard,
> that the value is representable in the target integer type. T
LGTM, and pushed to the trunk :)
On Mon, Apr 28, 2025 at 10:04 AM 曾治金 wrote:
>
> Hi, according to Jeff's requirement
> (https://gcc.gnu.org/pipermail/gcc-patches/2025-April/681864.html), I divide
> the change of riscv_register_move_cost into separate patch. Please help to
> review. Thanks.
>
>
From: yulong
This commit adds testcases for Xsfvcp.
Co-Authored by: Jiawei Chen
Co-Authored by: Shihua Liao
Co-Authored by: Yixuan Chen
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test.
On Tue, 29 Apr 2025 at 13:59, Luc Grosheintz wrote:
>
> Creates a nearly empty header mdspan and adds it to the build-system and
> Doxygen config file.
>
> libstdc++-v3/ChangeLog:
>
> * doc/doxygen/user.cfg.in: Add .
> * include/Makefile.am: Ditto.
> * include/Makefile.in:
From: yulong
This version is same as v5, but rebase to trunk, send out to trigger CI.
This commit adds intrinsics support for Xsfvcp extension.
Diff with V4: Delete the sifive_vector.h file.
Co-Authored by: Jiawei Chen
Co-Authored by: Shihua Liao
Co-Authored by: Yixuan Chen
gcc/ChangeLog:
Seems like the testcase will fail
https://github.com/ewlu/gcc-precommit-ci/issues/3278#issuecomment-2837806049
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c
> b/gcc/testsuite/gcc.target/riscv/predef-19.c
> index 2b90702192b..b29e60f9b99 100644
> --- a/gcc/testsuite/gcc.target/riscv/pr
Implements the tests for layout_stride and for the features of the other
two layouts that depend on layout_stride.
libstdc++/ChangeLog:
* testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add
tests for layout_stride.
* testsuite/23_containers/mdspan/layouts/ctor
Implements a suite of tests for the currently implemented parts of
layout_left. The individual tests are templated over the layout type, to
allow reuse as more layouts are added.
libstdc++/ChangeLog:
* testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: New test.
* testsu
Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look
OK for trunk/15/14?
-- >8 --
In r15-123 and r14-11434 we unconditionally set processing_template_decl
when substituting the context of an UNBOUND_CLASS_TEMPLATE, in order to
handle instantiation of the dependently scoped friend dec
Named loops (C2y) could not previously be compiled with
-O1 and -ggdb2 or higher because the label preceding
a loop (or switch) could not be found when using such
command lines.
This could be observed by compiling
gcc/gcc/testsuite/gcc.dg/c2y-named-loops-1.c with
the provoking command line (or any
Implements the remaining parts of layout_left and layout_right; and all
of layout_stride.
libstdc++/ChangeLog:
* include/std/mdspan(layout_stride): New class.
Signed-off-by: Luc Grosheintz
---
libstdc++-v3/include/std/mdspan | 227
1 file changed, 227 i
Implements the parts of layout_left that don't depend on any of the
other layouts.
libstdc++/ChangeLog:
* include/std/mdspan (layout_left): New class.
Signed-off-by: Luc Grosheintz
---
libstdc++-v3/include/std/mdspan | 179
1 file changed, 179 insertion
A prior commit added std::extents, this commit adds the tests. The bulk
is focussed on testing the constructors. These are split into three
groups:
1. the ctor from other extents and the copy ctor,
2. the ctor from a pack of integer-like objects,
3. the ctor from shapes, i.e. span and array.
For
Creates a nearly empty header mdspan and adds it to the build-system and
Doxygen config file.
libstdc++-v3/ChangeLog:
* doc/doxygen/user.cfg.in: Add .
* include/Makefile.am: Ditto.
* include/Makefile.in: Ditto.
* include/precompiled/stdc++.h: Ditto.
* inclu
Adds tests for layout_right and for the parts of layout_left that depend
on layout_right.
libstdc++/ChangeLog:
* testsuite/23_containers/mdspan/layouts/class_mandate_neg.cc: Add
tests for layout_stride.
* testsuite/23_containers/mdspan/layouts/ctors.cc: Add tests for
This implements std::extents from according to N4950 and
contains partial progress towards PR107761.
If an extent changes its type, there's a precondition in the standard,
that the value is representable in the target integer type. This
precondition is not checked at runtime.
The precondition fo
Implement the parts of layout_left that depend on layout_right; and the
parts of layout_right that don't depend on layout_stride.
libstdc++/ChangeLog:
* include/std/mdspan (layout_right): New class.
Signed-off-by: Luc Grosheintz
---
libstdc++-v3/include/std/mdspan | 147 +++
Uses the FTM infrastructure to create an internal feature testing macro
for partial availability of mdspan; which is then used to hide the
contents of the header mdspan when compiling against a standard prior to
C++23.
libstdc++-v3/ChangeLog:
* include/bits/version.def: Add internal featu
This patch series follows up on:
https://gcc.gnu.org/pipermail/libstdc++/2025-April/061078.html
As agreed, I'm appending commits that add the layouts to this patch
series. Each layout is added in a separate commit and tests are added in
the immediately following commit.
Changes since v4 to std::e
Fixed https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119317
Tested on AArch64 using the test case provided by the bug
reporter:
int fun()
{
main:
while(1)
continue main;
}
Without the fix, this program failed to compile:
test.c: In function ‘fun’:
test.c:5:14: error: ‘continue’ statement
On Tue, Apr 29, 2025 at 6:49 PM Uros Bizjak wrote:
>
> On Tue, Apr 29, 2025 at 12:41 PM H.J. Lu wrote:
> >
> > On Tue, Apr 29, 2025 at 5:52 PM Uros Bizjak wrote:
> > >
> > > MOVS instructions allow segment override of their source operand, e.g.:
> > >
> > > rep movsq %gs:(%rsi), (%rdi)
> > >
On Tue, Apr 29, 2025 at 6:46 PM Richard Biener
wrote:
>
> On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wrote:
> >
> > On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
> > wrote:
> > >
> > > On Tue, Apr 29, 2025 at 10:48 AM H.J. Lu wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 4:25 PM Richard Biener
Jennifer Schmitz writes:
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index f7bccf532f8..1c06b8528e9 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -6416,13 +6416,30 @@ aarch64_stack_protect_canary_mem (machine_mode mode,
I see, let the vec_dup enter the rtx_cost again to append the total to vmv, I
have a try testing. For example with below change:
+ switch (rcode)
+ {
+ case VEC_DUPLICATE:
+ *total += get_vector_costs ()->regmove->GR2VR * COSTS_N_INSNS (1);
+ break;
+
On Tue, Apr 29, 2025 at 12:58 PM Tomasz Kaminski
wrote:
>
>
> On Tue, Apr 29, 2025 at 9:28 AM Tomasz Kamiński
> wrote:
>
>> These patch makes following changes to _Pres_type values:
>> * _Pres_esc is replaced with separate _M_debug flag.
>> * _Pres_s, _Pres_p do not overlap with _Pres_none.
>>
On Tue, Apr 29, 2025 at 9:28 AM Tomasz Kamiński wrote:
> These patch makes following changes to _Pres_type values:
> * _Pres_esc is replaced with separate _M_debug flag.
> * _Pres_s, _Pres_p do not overlap with _Pres_none.
> * hexadecimal presentation use same values for pointer, integer
>
On Tue, Apr 29, 2025 at 12:41 PM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 5:52 PM Uros Bizjak wrote:
> >
> > MOVS instructions allow segment override of their source operand, e.g.:
> >
> > rep movsq %gs:(%rsi), (%rdi)
> >
> > where %rsi is the address of the source location (with %gs segmen
On Tue, Apr 29, 2025 at 12:32 PM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
> wrote:
> >
> > On Tue, Apr 29, 2025 at 10:48 AM H.J. Lu wrote:
> > >
> > > On Tue, Apr 29, 2025 at 4:25 PM Richard Biener
> > > wrote:
> > > >
> > > > On Tue, Apr 29, 2025 at 9:39 AM H.J. Lu wr
Hi all,
Here is the updated patch that address some of the @Jeff Law comments .
P8700 don't have a vector engine and we support the insns type till
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv.md#L358
and schedule module enabled the same .
---
gcc/config/riscv/mips
On Tue, Apr 29, 2025 at 5:52 PM Uros Bizjak wrote:
>
> MOVS instructions allow segment override of their source operand, e.g.:
>
> rep movsq %gs:(%rsi), (%rdi)
>
> where %rsi is the address of the source location (with %gs segment override)
> and %rdi is the address of the destination location
The following makes PRE handle &ptr->field the same as VN by
treating it as a POINTER_PLUS_EXPR when possible and thus as
'nary'. To facilitate this the patch splits out vn_pp_nary_for_addr
and adds const overloads for vec::last. The patch also avoids
handling an effective zero offset as POINTER_
On Tue, Apr 29, 2025 at 5:56 PM Richard Biener
wrote:
>
> On Tue, Apr 29, 2025 at 10:48 AM H.J. Lu wrote:
> >
> > On Tue, Apr 29, 2025 at 4:25 PM Richard Biener
> > wrote:
> > >
> > > On Tue, Apr 29, 2025 at 9:39 AM H.J. Lu wrote:
> > > >
> > > > For targets, like x86, which define TARGET_PROMO
在 2025-4-29 13:03, LIU Hao 写道:
This fixes a long-standing issue that GCC used to assume 16-byte stack alignment on i686-w64-mingw32,
which is not always the case for callbacks from system libraries.
CC Zeb Figura
This patch looks a bit risky. The overall effect of `__attribute__((__force_ali
On Tue, Apr 29, 2025 at 5:30 PM Uros Bizjak wrote:
>
> On Tue, Apr 29, 2025 at 9:56 AM H.J. Lu wrote:
> >
> > Don't expand UNSPEC_TLS_LD_BASE to a call so that the RTL local copy
> > propagation pass can eliminate multiple __tls_get_addr calls.
>
> __tls_get_addr needs to be called with 16-byte a
On Tue, 29 Apr 2025 at 10:37, Tomasz Kaminski wrote:
>
>
>
> On Tue, Apr 29, 2025 at 10:58 AM Jonathan Wakely wrote:
>>
>> This will hardly make a dent in the very slow compile times for
>> but it seems worth doing anyway.
>>
>> libstdc++-v3/ChangeLog:
>>
>> * include/bits/regex_compiler
On Tue, Apr 29, 2025 at 10:48 AM H.J. Lu wrote:
>
> On Tue, Apr 29, 2025 at 4:25 PM Richard Biener
> wrote:
> >
> > On Tue, Apr 29, 2025 at 9:39 AM H.J. Lu wrote:
> > >
> > > For targets, like x86, which define TARGET_PROMOTE_PROTOTYPES to return
> > > true, all integer arguments smaller than in
MOVS instructions allow segment override of their source operand, e.g.:
rep movsq %gs:(%rsi), (%rdi)
where %rsi is the address of the source location (with %gs segment override)
and %rdi is the address of the destination location.
The testcase improves from (-O2 -mno-sse -mtune=generic):
1 - 100 of 132 matches
Mail list logo
