[PATCH 1/3 v3] vect: generate suitable convert insn for int -> int, float -> float and int <-> float.

I wrap a part of code about indirect conversion. The API refers to supportable_narrowing/widening_operations. BRs, Lin gcc/ChangeLog: PR target/107432 * tree-vect-generic.cc (expand_vector_conversion): Support convert for int -> int, float -> float and int <-> fl

[PATCH v2] Implement -fassume-sane-operator-new [PR110137]

This patch implements the flag -fassume-sane-operator-new as suggested in PR110137. When the flag is enabled, it is assumed that operator new does not modify global memory. See the previous email for more context. Issues raised has been fixed, except that it remains not very well integrated wi

[PATCH v1] Test: Move target independent test cases to gcc.dg/torture

From: Pan Li The test cases of pr115387 are target independent, at least x86 and riscv are able to reproduce. Thus, move these cases to the gcc.dg/torture. The below test suites are passed. 1. The rv64gcv fully regression test. 2. The x86 fully regression test. gcc/testsuite/ChangeLog:

Re: [PATCH] Fix ICE in rtl check due to CONST_WIDE_INT in CONST_VECTOR_DUPLICATE_P

On Tue, Jun 11, 2024 at 01:36:35PM +0800, liuhongt wrote: > In theory, const_wide_int can also be handle with extra check for each > components of the HOST_WIDE_INT array, and the check is need for both > shift and bit_and operands. > I assume the optimization opportnunity is rare, so the patch ju

Re: [PATCH] jit: Ensure ssize_t is defined.

Hi I can’t seem to get a review of this one-line patch. Could a global reviewer help? Thanks, FX ping**3 > Le 11 mai 2024 à 17:16, FX Coudert a écrit : > > Hi, > > On some targets it seems that ssize_t is not defined by any of the headers > transitively included by . This leads to a boo

[PATCH] Fix ICE in rtl check due to CONST_WIDE_INT in CONST_VECTOR_DUPLICATE_P

In theory, const_wide_int can also be handle with extra check for each components of the HOST_WIDE_INT array, and the check is need for both shift and bit_and operands. I assume the optimization opportnunity is rare, so the patch just add extra check to make sure GET_MODE_INNER (mode) can fix into

Re: [PATCH] AVX-512: Pacify -Wshift-overflow=2. [PR115409]

On Mon, Jun 10, 2024 at 2:37 PM Collin Funk wrote: > > A shift of 31 on a signed int is undefined behavior. Since unsigned > int is 32-bits wide this change fixes it and silences the warning. Ok. > > gcc/ChangeLog: > > PR target/115409 > * config/i386/avx512fp16intrin.h (_mm512_co

[committed] [RISC-V] Drop dead test

This test is no longer useful. It doesn't test what it was originally intended to test and there's really no way to recover it sanely. We agreed in the patchwork meeting last week that if we want to test Zfa that we'll write a new test for that. Similarly if we want to do deeper testing of t

Re: [PATCH v3 0/3] RISC-V: Add basic Zaamo and Zalrsc support

On 6/10/24 3:46 PM, Patrick O'Neill wrote: The A extension has been split into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags Ratification: https://jira.riscv.org/

Re: [PATCH v3 0/3] RISC-V: Add basic Zaamo and Zalrsc support

On 6/10/24 6:15 PM, Andrea Parri wrote: On Mon, Jun 10, 2024 at 02:46:54PM -0700, Patrick O'Neill wrote: The A extension has been split into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Zaamo/Zalrsc spec: https://github.com/risc

Re: [PATCH] c-family: Introduce the -Winvalid-noreturn flag from clang with extra tuneability

On 6/10/24 03:13, Julian Waters wrote: Hi Jason, Thanks for the reply. I'm a little bit overwhelmed with university at the moment, would it be ok if I delay implementing this a little bit? Sure, we're still early in GCC 15 development, no time pressure. On Tue, Jun 4, 2024 at 1:04 AM Jason M

Re: [PATCH] c++: remove Concepts TS code

On 6/10/24 11:13, Marek Polacek wrote: On Mon, Jun 10, 2024 at 10:22:11AM -0400, Patrick Palka wrote: On Fri, 7 Jun 2024, Marek Polacek wrote: @@ -3940,9 +3936,6 @@ find_parameter_packs_r (tree *tp, int *walk_subtrees, void* data) parameter pack (14.6.3), or the type-specifier-seq of

RE: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

Got it, thanks. Let me prepare the patch after test. Pan -Original Message- From: Jeff Law Sent: Tuesday, June 11, 2024 9:42 AM To: Li, Pan2 ; Sam James Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com Subject: Re: [PATCH v1] Widening

Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

On 6/10/24 7:28 PM, Li, Pan2 wrote: Hi Sam, This testcases ICEs for me on x86-64 too (without your patch) with just -O2. Can you move it out of the riscv suite? (I suspect the other fails on x86-64 too). Sure thing, but do you have any suggestion about where should I put these 2 cases? T

RE: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

Hi Sam, > This testcases ICEs for me on x86-64 too (without your patch) with just -O2. > Can you move it out of the riscv suite? (I suspect the other fails on x86-64 > too). Sure thing, but do you have any suggestion about where should I put these 2 cases? There are sorts of sub-directories un

RE: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

Thank a lot, Jeff. Pan -Original Message- From: Jeff Law Sent: Tuesday, June 11, 2024 4:15 AM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com Subject: Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI m

Re: [x86 PATCH] PR target/115397: AVX512 ternlog vs. -m32 -fPIC constant pool.

On Mon, Jun 10, 2024 at 3:20 PM Roger Sayle wrote: > > > This patch fixes PR target/115397, a recent regression caused by my > ternlog patch that results in an ICE (building numpy) with -m32 -fPIC. > The problem is that ix86_broadcast_from_constant, which calls > get_pool_constant, doesn't handle

Re: [PATCH v3 0/3] RISC-V: Add basic Zaamo and Zalrsc support

On Mon, Jun 10, 2024 at 02:46:54PM -0700, Patrick O'Neill wrote: > The A extension has been split into two parts: Zaamo and Zalrsc. > This patch adds basic support by making the A extension imply Zaamo and > Zalrsc. > > Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags > Ratifica

[pushed] modula2: Fix typos, grammar, and a link

Pushed. Gerald gcc: * doc/gm2.texi (Documentation): Fix typos, grammar, and a link. --- gcc/doc/gm2.texi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/doc/gm2.texi b/gcc/doc/gm2.texi index 8661fcb8728..c532339fbb8 100644 --- a/gcc/doc/gm2.texi +++ b/gcc/d

[pushed] wwwdocs: news: Use https for our Wiki

Pushed. Gerald --- htdocs/news.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/htdocs/news.html b/htdocs/news.html index 5f652d90..de92bdf6 100644 --- a/htdocs/news.html +++ b/htdocs/news.html @@ -384,7 +384,7 @@ The Vtable Verification Feature is now in GCC [2013

[PATCH v3 1/3] RISC-V: Add basic Zaamo and Zalrsc support

From: Edwin Lu There is a proposal to split the A extension into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Proposal: https://github.com/riscv/riscv-zaamo-zalrsc/tags gcc/ChangeLog: * common/config/riscv/riscv-common.cc:

[PATCH v3 0/3] RISC-V: Add basic Zaamo and Zalrsc support

The A extension has been split into two parts: Zaamo and Zalrsc. This patch adds basic support by making the A extension imply Zaamo and Zalrsc. Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags Ratification: https://jira.riscv.org/browse/RVS-1995 v2: Rebased and updated some te

[PATCH v3 3/3] RISC-V: Add Zalrsc amo-op patterns

All amo patterns can be represented with lrsc sequences. Add these patterns as a fallback when Zaamo is not enabled. gcc/ChangeLog: * config/riscv/sync.md (atomic_): New expand pattern. (amo_atomic_): Rename amo pattern. (atomic_fetch_): New lrsc sequence pattern.

[PATCH v3 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support

Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A. gcc/ChangeLog: * doc/sourcebuild.texi: Add docs for atomic extension testsuite infra. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A. * gcc.target/risc

[to-be-committed] [RISC-V] Improve (1 << N) | C for rv64

Another improvement for generating Zbs instructions. In this case we're looking at stuff like (1 << N) | C where N varies and C is a single bit constant. In this pattern the (1 << N) happens in SImode, but is zero extended out to DImode before the bit manipulation. The fact that we're modify

Re: [PATCH] Move array_bounds warnings into it's own pass.

pushed as 74ee12ff68243bb177fb8653474dff80c3792139 fyi, the 2 testcases depending on the VRP flag were: c-c++-common/Warray-bounds-2.c   (-warray-bounds  -fno-tree-vrp :-P) and g++.dg/warn/string1.C   (-O1 -Wall) Andrew On 6/10/24 16:12, Jeff Law wrote: On 6/10/24 1:24 PM, Andrew MacLeod w

Re: [PATCH] Move array_bounds warnings into it's own pass.

On 6/10/24 16:12, Jeff Law wrote: Does anyone have any issues with any of this? No, in fact, quite the opposite.  I think we very much want the warning out of VRP into its own little pass that we can put wherever it makes sense in the pipeline rather than having it be tied to VRP. I'd p

Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

On 6/10/24 8:49 AM, pan2...@intel.com wrote: When enabled the PHI handing for COND_EXPR, we need to insert the gcall to replace the PHI node. Unfortunately, I made a mistake that insert the gcall to before the last stmt of the bb. See below gimple, the PHI is located at no.1 but we insert

Re: [PATCH] Move array_bounds warnings into it's own pass.

On 6/10/24 1:24 PM, Andrew MacLeod wrote: The array bounds warning pass was originally attached to the VRP pass because it wanted to leverage the context sensitive ranges available there. With ranger, we can make it a pass of its own for very little cost. This patch does that. It removes th

RE: [PATCH] aarch64: Improve popcount for bytes [PR113042]

> -Original Message- > From: Kyrylo Tkachov > Sent: Monday, June 10, 2024 12:26 AM > To: Andrew Pinski (QUIC) ; gcc- > patc...@gcc.gnu.org > Subject: Re: [PATCH] aarch64: Improve popcount for bytes > [PR113042] > > Hi Andrew > > -Original Message- > From: Andrew Pinski

[PATCH] Move array_bounds warnings into it's own pass.

The array bounds warning pass was originally attached to the VRP pass because it wanted to leverage the context sensitive ranges available there. With ranger, we can make it a pass of its own for very little cost.  This patch does that. It removes the array_bounds_checker from VRP and makes it

[PATCH v2] aarch64: Improve popcount for bytes [PR113042]

For popcount for bytes, we don't need the reduction addition after the vector cnt instruction as we are only counting one byte's popcount. This changes the popcount extend to cover all ALLI rather than GPI. Changes since v1: * v2 - Use ALLI iterator and combine all into one pattern. Add new

Re: [PATCH v2] Target-independent store forwarding avoidance.

On 6/10/24 12:27 PM, Philipp Tomsich wrote: This change is what I briefly hinted as "the complete solution" that we had on the drawing board when we briefly talked last November in Santa Clara. I haven't any recollection of that part of the discussion, but I was a bit frazzled as you probab

Re: [PATCH v2] Target-independent store forwarding avoidance.

On Mon, 10 Jun 2024 at 20:03, Jeff Law wrote: > > > > On 6/10/24 1:55 AM, Manolis Tsamis wrote: > > >> > > There was an older submission of a load-pair specific pass but this is > > a complete reimplementation and indeed significantly more general. > > Apart from being target independant, it addre

Re: [PATCH v2] Target-independent store forwarding avoidance.

On 6/10/24 1:55 AM, Manolis Tsamis wrote: There was an older submission of a load-pair specific pass but this is a complete reimplementation and indeed significantly more general. Apart from being target independant, it addresses a number of important restrictions and can handle multiple st

Re: [PATCH] ifcvt: Clarify if_info.original_cost.

Robin Dapp writes: >> Is there any way we can avoid using pattern_cost here? Using it means >> that we can make use of targetm.insn_cost for the jump but circumvent >> it for the condition, giving a bit of a mixed metric. >> >> (I realise there are existing calls to pattern_cost in ifcvt.cc, >>

Re: [PATCH v3 6/6] aarch64: Add DLL import/export to AArch64 target

Thanks for the update. Parts 1-5 look good to me. Some minor comments below about part 6: Evgeny Karpov writes: > This patch reuses the MinGW implementation to enable DLL import/export > functionality for the aarch64-w64-mingw32 target. It also modifies > environment configurations for MinGW. >

Re: [PATCH v2 2/3] RISC-V: Add Zalrsc and Zaamo testsuite support

On 6/7/24 16:04, Jeff Law wrote: On 6/3/24 3:53 PM, Patrick O'Neill wrote: Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A. * gcc.target/riscv/amo-table-a-6-amo-

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

On 6/10/24 8:52 AM, Li, Pan2 wrote: Not sure if below float eq implement in sail-riscv is useful or not, but looks like some special handling for nan, as well as snan. https://github.com/riscv/sail-riscv/blob/master/c_emulator/SoftFloat-3e/source/f32_eq.c Yes, but it's symmetrical, which is

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

On 6/10/24 10:16 AM, Demin Han wrote: Hi， I‘m on vacation rencently. I will return in a few days and summit new patch with the test. No problem. Enjoy your vacation, this can certainly wait until you return. jeff

Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

On 6/10/24 8:49 AM, pan2...@intel.com wrote: From: Pan Li When enabled the PHI handing for COND_EXPR, we need to insert the gcall to replace the PHI node. Unfortunately, I made a mistake that insert the gcall to before the last stmt of the bb. See below gimple, the PHI is located at no.

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

Hi， I‘m on vacation rencently. I will return in a few days and summit new patch with the test. Regards， Demin 发件人: Jeff Law 发送时间: 星期一, 六月 10, 2024 9:49 下午 收件人: Robin Dapp ; Demin Han ; 钟居哲 ; gcc-patches 抄送: kito.cheng ; Li, Pan2 主题: Re: [PATCH 1/5] RISC-

[PING][PATCH v2] docs: Update function multiversioning documentation

On Tue, Apr 30, 2024 at 05:10:45PM +0100, Andrew Carlotti wrote: > Add target_version attribute to Common Function Attributes and update > target and target_clones documentation. Move shared detail and examples > to the Function Multiversioning page. Add target-specific details to > target-spec

Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

pan2...@intel.com writes: > From: Pan Li > > When enabled the PHI handing for COND_EXPR, we need to insert the gcall > to replace the PHI node. Unfortunately, I made a mistake that insert > the gcall to before the last stmt of the bb. See below gimple, the PHI > is located at no.1 but we ins

[PUSHED] Fix pr115388.c: plain char could be unsigned by default [PR115415]

This is a simple fix to the testcase as plain `char` could be unsigned by default on some targets (e.g. aarch64 and powerpc). Committed as obvious after quick test of the testcase on both aarch64 and x86_64. gcc/testsuite/ChangeLog: PR testsuite/115415 PR tree-optimization/11538

Re: [PATCH] c++: remove Concepts TS code

On Mon, Jun 10, 2024 at 10:22:11AM -0400, Patrick Palka wrote: > On Fri, 7 Jun 2024, Marek Polacek wrote: > > @@ -3940,9 +3936,6 @@ find_parameter_packs_r (tree *tp, int *walk_subtrees, > > void* data) > > parameter pack (14.6.3), or the type-specifier-seq of a type-id that > > is a pack

RE: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

Not sure if below float eq implement in sail-riscv is useful or not, but looks like some special handling for nan, as well as snan. https://github.com/riscv/sail-riscv/blob/master/c_emulator/SoftFloat-3e/source/f32_eq.c Pan -Original Message- From: Jeff Law Sent: Monday, June 10, 2024

[PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match

From: Pan Li When enabled the PHI handing for COND_EXPR, we need to insert the gcall to replace the PHI node. Unfortunately, I made a mistake that insert the gcall to before the last stmt of the bb. See below gimple, the PHI is located at no.1 but we insert the gcall (aka no.9) to the end of

Re: [PATCH] htdocs/contribute.html: correct disctinct->distinct spelling

On Sat, 2 Dec 2023, Jonny Grant wrote: > Correct a spelling mistake this page: > https://gcc.gnu.org/contribute.html Superseded by Author: Jonathan Grant Date: Sat Jun 8 21:26:04 2024 +0200 *: Correct spelling which I just pushed. Gerald

Re: [PATCH] htdocs: correct spelling and use https in examples

On Wed, 6 Dec 2023, Jonny Grant wrote: > ChangeLog: > > htdocs: correct spelling and use https in examples. I noticed this hasn't been applied yet, so went ahead and pushed (nearly all of) it. Just the "use https in examples" part feels orthogonal, so better a separate issue, and I'm not

[PATCH v3 0/2] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Hi, Changes in v3: Droped special case for thumb1_extendqisi2 as it's only thumb1_extendhisi2 that causes problem for gen_rtx_SIGN_EXTEND. Changes in v2: Updated the patch to also fix the Cortex-M55 issue reported in PR115253 and updated the commit message to mention the PR number. Initial iss

[PATCH v3 1/2] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Properly handle zero and sign extension for Armv8-M.baseline as Cortex-M23 can have the security extension active. Currently, there is an internal compiler error on Cortex-M23 for the epilog processing of sign extension. This patch addresses the following CVE-2024-0151 for Armv8-M.baseline. gcc/C

[PATCH v3 2/2] testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

For Armv8.1-M, the clearing of the registers is handled differently than for Armv8-M, so update the test case accordingly. gcc/testsuite/ChangeLog: PR target/115253 * gcc.target/arm/cmse/extend-return.c: Update test case condition for Armv8.1-M. Signed-off-by: Torbjörn SV

Re: [PATCH v2] vect: Merge loop mask and cond_op mask in fold-left, reduction [PR115382].

Robin Dapp writes: >> Actually, as Richard mentioned in the PR, it would probably be better >> to use prepare_vec_mask instead. It should work in this context too >> and would avoid redundant double masking. > > Attached is v2 that uses prepare_vec_mask. > > Regtested on riscv64 and armv8.8-a+sve

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

On 6/10/24 1:33 AM, Robin Dapp wrote: But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0? target = (a == b) ? x : y target = (a != b) ? y : x Are equivalent, even for IEEE IIRC. Yes, that should be fine. My concern was not that we do a canonicalization but that we might

[to-be-committed][RISC-V] Generate bclr more often for rv64

Another of Raphael's patches to improve our ability to safely generate a Zbs instruction, bclr in this instance. In this case we have something like ~(1 << N) & C where N is variable, but C is a constant. If C has 33 or more leading zeros, then no matter what bit we clear via bclr, the result

[PATCH v2] vect: Merge loop mask and cond_op mask in fold-left, reduction [PR115382].

> Actually, as Richard mentioned in the PR, it would probably be better > to use prepare_vec_mask instead. It should work in this context too > and would avoid redundant double masking. Attached is v2 that uses prepare_vec_mask. Regtested on riscv64 and armv8.8-a+sve via qemu. Bootstrap and regt

Re: [PATCH] Rearrange SLP nodes with duplicate statements. [PR98138]

On Mon, 10 Jun 2024, Manolis Tsamis wrote: > On Wed, Jun 5, 2024 at 11:07 AM Richard Biener wrote: > > > > On Tue, 4 Jun 2024, Manolis Tsamis wrote: > > > > > This change adds a function that checks for SLP nodes with multiple > > > occurrences > > > of the same statement (e.g. {A, B, A, B, ...}

Re: [PATCH v2 1/2] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Hi, So, you talk about gen_thumb1_extendhisi2, but there is also gen_thumb1_extendqisi2. Will it actually be cleaner if the block is indented one level? The comment can be added in the "if (TARGET_THUMB1)" block regardless to indicate that gen_rtx_SIGN_EXTEND can't be used. gen_rtx_SIGN_EX

Re: [PATCH] internal-fn: Force to reg if operand doesn't match.

Richard Biener writes: > On Mon, Jun 10, 2024 at 9:35 AM Robin Dapp wrote: >> >> Hi, >> >> despite looking good on cfarm185 and Linaro's pre-commit CI >> gcc-15-638-g7ca35f2e430 now appears to have caused several >> regressions on arm-eabi cortex-m55 as found by Linaro's CI: >> >> https://linaro.

Re: [PATCH v2 1/2] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Hi Andre, Thanks for the review! Please see my questions below. On 2024-06-10 12:37, Andre Vieira (lists) wrote: Hi Torbjorn, Thanks for this, I have some comments below. On 07/06/2024 09:56, Torbjörn SVENSSON wrote: Properly handle zero and sign extension for Armv8-M.baseline as Cortex-M23

Re: [PATCH] fixincludes: bypass the math_exception fix on __cplusplus

Hi FX, >> However, please note that the comment states >> * This should be bypassed on __cplusplus, but some supposedly C++ >> * aware headers, such as Solaris 8 and 9, don't wrap their struct >> It's "such as Solaris 8 and 9", so there may well be others. > > I know, but that was 24 years

Re: [PATCH] fixincludes: bypass the math_exception fix on __cplusplus

> However, please note that the comment states > * This should be bypassed on __cplusplus, but some supposedly C++ > * aware headers, such as Solaris 8 and 9, don't wrap their struct > It's "such as Solaris 8 and 9", so there may well be others. I know, but that was 24 years ago, and I cou

Re: [PATCH] libstdc++: Introduce scale factor in 30_threads/future/members/poll.cc [PR98678]

On Mon, 10 Jun 2024 at 12:54, Rainer Orth wrote: > > 30_threads/future/members/poll.cc consistently FAILs on Solaris/x86 > (both 32 and 64-bit): > > FAIL: 30_threads/future/members/poll.cc -std=gnu++17 execution test I see this one failing under x86_64-linux under high load. So I think we might

[PATCH] libstdc++: Introduce scale factor in 30_threads/future/members/poll.cc [PR98678]

30_threads/future/members/poll.cc consistently FAILs on Solaris/x86 (both 32 and 64-bit): FAIL: 30_threads/future/members/poll.cc -std=gnu++17 execution test /vol/gcc/src/hg/master/local/libstdc++-v3/testsuite/30_threads/future/members/poll.cc:95: int main(): Assertion 'wait_until_sys_min < (re

Re: [PATCH] Rearrange SLP nodes with duplicate statements. [PR98138]

On Wed, Jun 5, 2024 at 11:07 AM Richard Biener wrote: > > On Tue, 4 Jun 2024, Manolis Tsamis wrote: > > > This change adds a function that checks for SLP nodes with multiple > > occurrences > > of the same statement (e.g. {A, B, A, B, ...}) and tries to rearrange the > > node > > so that there a

[PATCH] tree-optimization/115388 - wrong DSE in irreductible regions

The following fixes a latent bug in DSE with regarding to variant array accesses where the code avoiding bogus DSE in loops fails to handle irreducible regions. For those we need to make sure backedges are marked and discover a header for the irreducible region to check invariantness. Bootstrappe

Re: [PATCH] fixincludes: bypass the math_exception fix on __cplusplus

Hi FX, > The fixincludes fix “math_exception” is being applied overly broadly, > including many targets which don’t need it, like darwin (and probably all > non-glibc targets). I’m not sure if it is still needed on any target, but > because I can’t be absolutely positive about that, I don’t want t

Re: [PATCH] aarch64: Add fcsel to cmov integer and csel to float cmov [PR98477]

Andrew Pinski writes: > This patch adds an alternative to the integer cmov and one to floating > point cmov so we avoid in some more moving > > PR target/98477 > > gcc/ChangeLog: > > * config/aarch64/aarch64.md (*cmov_insn[GPI]): Add 'w' > alternative. > (*cmov_insn[GPF]):

Re: [PATCH] aarch64: Add vector floating point trunc pattern

Pengxuan Zheng writes: > This patch is a follow-up of r15-1079-g230d62a2cdd16c to add vector floating > point trunc pattern for V2DF->V2SF and V4SF->V4HF conversions by renaming the > existing aarch64_float_truncate_lo_ pattern to the > standard > optab one, i.e., trunc2. This allows the vectoriz

Re: [PATCH] internal-fn: Force to reg if operand doesn't match.

On Mon, Jun 10, 2024 at 9:35 AM Robin Dapp wrote: > > Hi, > > despite looking good on cfarm185 and Linaro's pre-commit CI > gcc-15-638-g7ca35f2e430 now appears to have caused several > regressions on arm-eabi cortex-m55 as found by Linaro's CI: > > https://linaro.atlassian.net/browse/GNU-1252 > >

Re: [PATCH v2 1/2] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Hi Torbjorn, Thanks for this, I have some comments below. On 07/06/2024 09:56, Torbjörn SVENSSON wrote: Properly handle zero and sign extension for Armv8-M.baseline as Cortex-M23 can have the security extension active. Currently, there is a internal compiler error on Cortex-M23 for the epilog p

Re: [patch, rs6000, middle-end 0/1] v1: Add implementation for different targets for pair mem fusion

Ajit Agarwal writes: > On 10/06/24 3:20 pm, Richard Sandiford wrote: >> Ajit Agarwal writes: >>> On 10/06/24 2:52 pm, Richard Sandiford wrote: Ajit Agarwal writes: > On 10/06/24 2:12 pm, Richard Sandiford wrote: >> Ajit Agarwal writes: >>> + >>> + rt

Re: [patch, rs6000, middle-end 0/1] v1: Add implementation for different targets for pair mem fusion

Hello Richard: On 10/06/24 3:20 pm, Richard Sandiford wrote: > Ajit Agarwal writes: >> Hello Richard: >> >> On 10/06/24 2:52 pm, Richard Sandiford wrote: >>> Ajit Agarwal writes: On 10/06/24 2:12 pm, Richard Sandiford wrote: > Ajit Agarwal writes: >> + >> +

Re: [patch, rs6000, middle-end 0/1] v1: Add implementation for different targets for pair mem fusion

Hello Richard: On 10/06/24 3:20 pm, Richard Sandiford wrote: > Ajit Agarwal writes: >> Hello Richard: >> >> On 10/06/24 2:52 pm, Richard Sandiford wrote: >>> Ajit Agarwal writes: On 10/06/24 2:12 pm, Richard Sandiford wrote: > Ajit Agarwal writes: >> + >> +

Re: [PATCH v2 1/2] driver: Use -as/ld/objcopy as final fallback instead of native ones for cross

Richard Sandiford 于2024年6月6日周四 17:54写道： > > YunQiang Su writes: > > YunQiang Su 于2024年5月29日周三 10:02写道： > >> > >> Richard Sandiford 于2024年5月29日周三 05:28写道： > >> > > >> > YunQiang Su writes: > >> > > If `find_a_program` cannot find `as/ld/objcopy` and we are a cross > >> > > toolchain, > >> > >

Re: [patch, rs6000, middle-end 0/1] v1: Add implementation for different targets for pair mem fusion

Ajit Agarwal writes: > Hello Richard: > > On 10/06/24 2:52 pm, Richard Sandiford wrote: >> Ajit Agarwal writes: >>> On 10/06/24 2:12 pm, Richard Sandiford wrote: Ajit Agarwal writes: > + > + rtx set = single_set (insn); > + if (set == NULL_RTX) >>

Re: [PATCH] vect: Merge loop mask and cond_op mask in fold-left, reduction.

Richard Sandiford writes: > Robin Dapp writes: >> Hi, >> >> currently we discard the cond-op mask when the loop is fully masked >> which causes wrong code in >> gcc.dg/vect/vect-cond-reduc-in-order-2-signed-zero.c >> when compiled with >> -O3 -march=cascadelake --param vect-partial-vector-usage=2

Re: [patch, rs6000, middle-end 0/1] v1: Add implementation for different targets for pair mem fusion

Hello Richard: On 10/06/24 2:52 pm, Richard Sandiford wrote: > Ajit Agarwal writes: >> On 10/06/24 2:12 pm, Richard Sandiford wrote: >>> Ajit Agarwal writes: + +rtx set = single_set (insn); +if (set == NULL_RTX) + return false; >>>

[PATCH] tree-optimization/115395 - wrong-code with SLP reduction in epilog

When we continue a non-SLP reduction from the main loop in the epilog with a SLP reduction we currently fail to handle an adjustment by the initial value because that's not a thing with SLP. As long as we have the possibility to mix SLP and non-SLP we have to handle it though. Bootstrapped and tes

Re: [patch, rs6000, middle-end 0/1] v1: Add implementation for different targets for pair mem fusion

Ajit Agarwal writes: > On 10/06/24 2:12 pm, Richard Sandiford wrote: >> Ajit Agarwal writes: >>> + >>> + rtx set = single_set (insn); >>> + if (set == NULL_RTX) >>> + return false; >>> + >>> + rtx op0 = SET_SRC (set); >>> +

[PATCH v2 0/6] Add DLL import/export implementation to AArch64

The patch series has been successfully verified by patchwork, after resolving the issue with the mailing client. https://patchwork.sourceware.org/project/gcc/list/?series=34865 The x86_64-w64-mingw32 build has been tested, and no regressions have been detected after applying the patch series. htt

[COMMITTED 29/30] ada: Storage_Error in indirect call to function returning limited type

From: Javier Miranda At runtime the code generated by the compiler reports the exception Storage_Error in an indirect call through an access-to-subprogram variable that references a function returning a limited tagged type object. gcc/ada/ * sem_ch6.adb (Might_Need_BIP_Task_Actuals): Ad

[COMMITTED 25/30] ada: Resolve compilation issues with container aggregates in draft ACATS B tests

From: Gary Dismukes This change set addresses compilation problems encountered in the draft versions of the following ACATS B tests for container aggregates: B435001 (container aggregates with Assign_Indexed) B435002 (container aggregates with Add_Unnamed) B435003 (container aggregates with Add_

[COMMITTED 24/30] ada: Missing style check for extra parentheses in operators

From: Justin Squirek This patch fixes an issue in the compiler whereby wrapping an operand of a boolean operator resulted in a failure to detect whether or not they were unnecessary for the -gnatyx style checks. gcc/ada/ * ali.adb (Get_Nat): Remove unnecessary parentheses. * exp

Re: [PATCH] vect: Merge loop mask and cond_op mask in fold-left, reduction.

Robin Dapp writes: > Hi, > > currently we discard the cond-op mask when the loop is fully masked > which causes wrong code in > gcc.dg/vect/vect-cond-reduc-in-order-2-signed-zero.c > when compiled with > -O3 -march=cascadelake --param vect-partial-vector-usage=2. > > This patch ANDs both masks ins

[COMMITTED 21/30] ada: Unreferenced warning on abstract subprogram

From: Justin Squirek This patch modifies the unreferenced entity warning in the compiler to avoid noisily warning about unreferenced abstract subprogram. gcc/ada/ * sem_warn.adb (Warn_On_Unreferenced_Entity): Add a condition to ignore warnings on unreferenced abstract subprogram

[COMMITTED 26/30] ada: For freezing, treat an extension or delta aggregate like a regular aggregate.

From: Steve Baird Extend existing special freezing rules for regular aggregates to also apply to extension and delta aggregates. gcc/ada/ * freeze.adb (Should_Freeze_Type.Is_Dispatching_Call_Or_Aggregate): Treat an extension aggregate or a delta aggregate like a regular

[COMMITTED 14/30] ada: Remove incorrect assertion in run-time

From: Ronan Desplanques There is a special case of file paths on Windows that are absolute but don't start with a drive letter: UNC paths. This patch removes an assertion in System.OS_Lib.Normalize_Pathname that failed to take this case into account. It also renames a local subprogram of Normaliz

Re: [patch, rs6000, middle-end 0/1] v1: Add implementation for different targets for pair mem fusion

Hello Richard: On 10/06/24 2:12 pm, Richard Sandiford wrote: > Ajit Agarwal writes: >> + >> + rtx set = single_set (insn); >> + if (set == NULL_RTX) >> +return false; >> + >> + rtx op0 = SET_SRC (set); >> + rtx_co

[COMMITTED 28/30] ada: Derived type with convention C must override convention C_Pass_By_Copy

From: Gary Dismukes If a type DT is derived from a record type T with convention C_Pass_By_Copy and explicitly specifies convention C (via aspect or pragma), then type DT should not be treated as a type with convention C_Pass_By_Copy. Any parameters of the derived type should be passed by referen

[COMMITTED 23/30] ada: Iterator filter ignored on formal loop

From: Justin Squirek This patch fixs an issue where iterator filters for formal container and formal container element loops got silently ignored and remained unexpanded. gcc/ada/ * exp_ch5.adb (Expand_Formal_Container_Element_Loop): Add expansion of filter condition. (E

[COMMITTED 12/30] ada: Cleanup repeated code in expansion of stream attributes

From: Piotr Trojanek In expansion of various attributes, in particular for the Input/Output and Read/Write attributes, we can use constants that are already used for expansion of many other attributes. gcc/ada/ * exp_attr.adb (Expand_N_Attribute_Reference): Use constants declare

[COMMITTED 20/30] ada: Further refine 'Super attribute

From: Justin Squirek This patch adds the restriction on 'Super such that it cannot apply to objects whose parent type is an interface. gcc/ada/ * sem_attr.adb (Analyze_Attribute): Add check for interface parent types. Tested on x86_64-pc-linux-gnu, committed on master. --- gc

[COMMITTED 27/30] ada: Minor code adjustment to "not Present" test

From: Gary Dismukes This is just changing a "not Present (...)" test to "No (...)" to address a CB complaint from gnatcheck. gcc/ada/ * sem_aggr.adb (Resolve_Iterated_Association): Change "not Present" to "No" in test of Add_Named_Subp. Tested on x86_64-pc-linux-gnu, committed

[COMMITTED 22/30] ada: Crash checking accessibility level on private type

From: Justin Squirek This patch fixes an issue in the compiler whereby calculating a static accessibility level on a private type with an access discriminant resulted in a compile time crash when No_Dynamic_Accessibility_Checks is enabled. gcc/ada/ * accessibility.adb (Accessibility_Lev

[COMMITTED 13/30] ada: Fix incorrect lower bound presumption in gnatlink

From: Ronan Desplanques This patch fixes a subprogram in gnatlink that incorrectly assumed that the strings it is passed as arguments all have a lower bound of 1. gcc/ada/ * gnatlink.adb (Check_File_Name): Fix incorrect assumption. Tested on x86_64-pc-linux-gnu, committed on master. -

[COMMITTED 15/30] ada: Fix usage of SetThreadIdealProcessor

From: Ronan Desplanques This patches fixes the way the run-time library checks the return value of SetThreadIdealProcessor. gcc/ada/ * libgnarl/s-taprop__mingw.adb (Set_Task_Affinity): Fix usage of SetThreadIdealProcessor. Tested on x86_64-pc-linux-gnu, committed on master. --

[COMMITTED 17/30] ada: Remove streaming facilities from generics for formal containers

From: Yannick Moy The dependency on Ada.Streams is problematic for light runtimes. As these streaming facilities are in fact not used in formal containers, remove the corresponding dead code. gcc/ada/ * libgnat/a-chtgfo.adb (Generic_Read, Generic_Write): Remove. * libgnat/a-chtg

[COMMITTED 08/30] ada: Enable inlining for subprograms with multiple return statements

From: Piotr Trojanek With the support for forward GOTO statements in the GNATprove backend, we can now inline subprograms with multiple return statements in the frontend. Also, fix inconsistent source locations in the inlined code, which were now triggering assertion violations in the code for G

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