On Mon, Jun 10, 2024 at 02:46:54PM -0700, Patrick O'Neill wrote: > The A extension has been split into two parts: Zaamo and Zalrsc. > This patch adds basic support by making the A extension imply Zaamo and > Zalrsc. > > Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags > Ratification: https://jira.riscv.org/browse/RVS-1995 > > v2: > Rebased and updated some testcases that rely on the ISA string. > > v3: > Regex-ify temp registers in added testcases. > Remove unintentional whitespace changes. > Add riscv_{a|ztso|zaamo|zalrsc} docs to sourcebuild.texi (and move core-v bi > extension doc into appropriate section). > > Edwin Lu (1): > RISC-V: Add basic Zaamo and Zalrsc support > > Patrick O'Neill (2): > RISC-V: Add Zalrsc and Zaamo testsuite support > RISC-V: Add Zalrsc amo-op patterns
While providing a proper/detailed review of the series goes above my "GCC internals" skills, I've applied the series and checked that the generated code for some atomic operations meet expectations (expecta- tions which, w/ "only Zaamo", are arguably quite low as mentioned in v2 and elsewhere): Tested-by: Andrea Parri <and...@rivosinc.com> Andrea P.S. Unrelated to the changes at stake, but perhaps worth mentioning: w/ and w/o these changes, the following #include <stdatomic.h> void foo(atomic_flag *x) { atomic_flag_clear_explicit(x, memory_order_seq_cst); } ... gets mapped to foo: fence rw,rw sb zero,0(a0) fence rw,rw ret (w/o and w/ Ztso) while the current psABI spec is suggesting slightly "less synchronization", respectively, (w/o Ztso) foo: fence rw,w <- "release" fence sb zero,0(a0) fence rw,rw ret (w/ Ztso) foo: sb zero,0(a0) fence rw,rw ret