Re: [PATCH] gcc: Introduce -fhardened

On Fri, Sep 15, 2023 at 5:09 PM Marek Polacek via Gcc-patches wrote: > > Bootstrapped/regtested on x86_64-pc-linux-gnu, powerpc64le-unknown-linux-gnu, > and aarch64-unknown-linux-gnu; ok for trunk? > > -- >8 -- > In > I proposed -

Re: [PATCH] [RFC] New early __builtin_unreachable processing.

On Fri, Sep 15, 2023 at 4:45 PM Andrew MacLeod wrote: > > Ive been looking at __builtin_unreachable () regressions. The > fundamental problem seems to be a lack of consistent expectation for > when we remove it earlier than the final pass of VRP.After looking > through them, I think this pro

Re: [PATCH] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]

I think it's not make too much sense to back port GCC14's change to GCC 13, removing phase 6 optimization is reasonable to me, so LGTM :) On Mon, Sep 18, 2023 at 2:44 PM juzhe.zh...@rivai.ai wrote: > > Thanks for fixing it. > I am ok remove phase 6 optimization which has many latent bugs (in GCC

Re: Re: [PATCH V2] internal-fn: Support undefined rtx for uninitialized SSA_NAME

Thanks Richard. Address comments on V3: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630699.html juzhe.zh...@rivai.ai From: Richard Sandiford Date: 2023-09-17 23:29 To: Juzhe-Zhong CC: gcc-patches; rguenther Subject: Re: [PATCH V2] internal-fn: Support undefined rtx for uninitial

Re: [PATCH] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]

Thanks for fixing it. I am ok remove phase 6 optimization which has many latent bugs (in GCC 14 kito has refactored it) there. But I think we need kito's more comments about that. juzhe.zh...@rivai.ai From: Li Xu Date: 2023-09-18 12:19 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli

Re: [PATCH] Harmonize headers between both dg-extract-results scripts

On Thu, Sep 14, 2023 at 04:24:33PM +0200, Paul Iannetta wrote: > Hi, > > This is a small patch so that both dg-extract-results.py and > dg-extract-results.sh share the same header. In particular, it fixes > the fact that the regexp r'^Test Run By (\S+) on (.*)$' was never > matched in the python

[PATCH] rs6000: Skip empty inline asm in rs6000_update_ipa_fn_target_info [PR111366]

Hi, PR111366 exposes one thing that can be improved in function rs6000_update_ipa_fn_target_info is to skip the given empty inline asm string, since it's impossible to adopt any hardware features (so far HTM). Since this rs6000_update_ipa_fn_target_info related approach exists in GCC12 and later,

[PATCH] rs6000: Use default target option node for callee by default [PR111380]

Hi, As PR111380 (and the discussion in related PRs) shows, for now how function rs6000_can_inline_p treats the callee without any target option node is wrong. It considers it's always safe to inline this kind of callee, but actually its target flags are from the command line options (target_optio

PATCH v6 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces.

This new version of patch 6 use improve ree pass for rs6000 target using defined ABI interfaces. Bootstrapped and regtested on power64-linux-gnu. Review comments incorporated. Thanks & Regards Ajit ree: Improve ree pass for rs6000 target using defined abi interfaces For rs6000 target we see r

[PATCH] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412]

From: xuli vsetvl pass has been refactored in gcc14, and the optimization is more reasonable than releases/gcc-13. This problem does not exist in gcc14. Phase 6 of gcc13 is an optimization patch. Due to lack of consideration, there will be some hidden bugs, so we decided to remove phase 6. Altho

Ping [PATCH V4 2/2] rs6000: use mtvsrws to move sf from si p9

Hi, I would like to have a ping. BR, Jeff (Jiufu Guo) Jiufu Guo writes: > Hi, > > As mentioned in PR108338, on p9, we could use mtvsrws to implement > the bitcast from SI to SF (or lowpart DI to SF). > > For code: > *(long long*)buff = di; > float f = *(float*)(buff); > > "sldi 9,3,32

Ping [PATCH V4 1/2] rs6000: optimize moving to sf from highpart di

Hi, I would like to have a ping. BR, Jeff (Jiufu Guo) Jiufu Guo writes: > Hi, > > Currently, we have the pattern "movsf_from_si2" which was trying > to support moving high part DI to SF. > > The pattern looks like: XX:SF=bitcast:SF(subreg(YY:DI>>32),0) > It only accepts the "ashiftrt" for

Ping [PATCH] rs6000: mark tieable between INT and FLOAT

Hi, I would like to have a ping. BR, Jeff (Jiufu Guo) Jiufu Guo writes: > Hi, > > For PowerPC, some INT mode and FLOAT modes can be marked as tieable, > for example: DI<->DF. > One note SFmode is special, it would only tieable with itself. > > I updated previous patch more reasonable: > ht

[pushed] doc: GTY((cache)) documentation tweak

Applying to trunk as obvious (explaining existing behavior). -- 8< -- gcc/ChangeLog: * doc/gty.texi: Add discussion of cache vs. deletable. --- gcc/doc/gty.texi | 7 +++ 1 file changed, 7 insertions(+) diff --git a/gcc/doc/gty.texi b/gcc/doc/gty.texi index 15f9fa07405..1dfe4652644

Re: [PATCH v1] RISC-V: Support VLS mode for vec_set

LGTM On Mon, Sep 18, 2023 at 11:27 AM Pan Li via Gcc-patches wrote: > > From: Pan Li > > This patch would like to add the VLS support vec_set, both INT > and FP are included. > > Give sample code as below: > > typedef long long vl_t \ > __attribute__((vector_size(2 * sizeof (long long; > >

Re: [pushed] c++: [[no_unique_address]] and cv-qualified type

On 9/5/23 23:19, Jason Merrill wrote: Tested x86_64-pc-linux-gnu, applying to trunk. -- 8< -- We were checking for overlap using same_type_p and therefore allocating two Empty subobjects at the same offset because one was cv-qualified. This gives the warning at the location of the class name r

[PATCH v1] RISC-V: Support VLS mode for vec_set

From: Pan Li This patch would like to add the VLS support vec_set, both INT and FP are included. Give sample code as below: typedef long long vl_t \ __attribute__((vector_size(2 * sizeof (long long; vl_t init_vl (vl_t v, unsigned index, unsigned value) { v[index] = value; return v;

Re: [PATCH] c++: non-dependent assignment checking [PR63198, PR18474]

On 9/17/23 14:51, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? Patch generatde with -w to avoid noisy whitespace changes. -- >8 -- This patch makes us recognize and check non-dependent simple assigments ahead of time, like we already do f

[Committed] RISC-V: Remove redundant codes of VLS patterns[NFC]

Consider those VLS patterns are the same VLA patterns. Now extend VI -> V_VLSI and VF -> V_VLSF. Then remove the redundant codes of VLS patterns. gcc/ChangeLog: * config/riscv/autovec-vls.md (3): Deleted. (copysign3): Ditto. (xorsign3): Ditto. (2): Ditto. *

Re: [PATCH] c++: optimize tsubst_template_decl for function templates

On 9/17/23 15:13, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- r14-2655-g92d1425ca78040 made instantiate_template avoid redundantly performing a specialization lookup when instantiating a function or alias template. This patch ap

Re: [PATCH] c++: constness of decltype of NTTP object [PR98820]

On 9/16/23 18:00, Patrick Palka wrote: On Sat, 16 Sep 2023, Jason Merrill wrote: On 9/15/23 13:55, Patrick Palka wrote: This corrects decltype of a (class) NTTP object as per [dcl.type.decltype]/1.2 and [temp.param]/6 in the type-dependent case. In the non-dependent case (nontype-class8.C) we

Re: [PATCH] c++: overeager type completion in convert_to_void [PR111419]

On 9/16/23 17:41, Patrick Palka wrote: On Sat, 16 Sep 2023, Jason Merrill wrote: On 9/15/23 12:03, Patrick Palka wrote: Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- Here convert_to_void always completes the type of an INDIRECT_REF or VAR_DECL expre

[PATCH V3] internal-fn: Support undefined rtx for uninitialized SSA_NAME

According to PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 As Richard and Richi suggested, we recognize uninitialized SSA_NAME and convert it into SCRATCH rtx if the target predicate allows SCRATCH. It can help to reduce redundant data move instructions of targets like RISC-V. Bootstr

RE: [PATCH v1] RISC-V: Bugfix for scalar move with merged operand

> I must be missing something. Doesn't insn 10 broadcast the immediate > 0x2 to both elements of r142?!? What am I missing? Thanks Jeff for comments. The insn 10 is VECTOR_SCALAR_MOV, aka vmv.s.x from the asm code. Pan -Original Message- From: Jeff Law Sent: Sunday, September 17, 2

[r14-4046 Regression] FAIL: 23_containers/vector/bool/110807.cc -std=gnu++17 (test for excess errors) on Linux/x86_64

On Linux/x86_64, 3a0e01f6bb1d6ec444001f2caea6ef43a4a83e3a is the first bad commit commit 3a0e01f6bb1d6ec444001f2caea6ef43a4a83e3a Author: Jonathan Wakely Date: Fri Sep 1 21:27:57 2023 +0100 libstdc++: Add support for running tests with multiple -std options caused FAIL: 23_containers/

[PATCH] Remove xfail from gcc.dg/tree-ssa/20040204-1.c

So the xfail was there because at one point the difference from having logical-op-non-short-circuit set to 1 or 0 made a difference in being able to optimizing a conditional way. This has not been true for over 10 years in this case so instead of keeping on adding to the xfail list, removing it is

[PATCH] MATCH: Make zero_one_valued_p non-recusive fully

So it turns out VN can't handle any kind of recusion for match. In this case we have `b = a & -1` and we try to match a as being zero_one_valued_p and VN returns b as being the value and we just go into an infinite loop at this point. OK? Bootstrapped and tested on x86_64-linux-gnu with no regress

[PATCH][_Hashtable] Avoid redundant usage of rehash policy

libstdc++: [_Hashtable] Avoid redundant usage of rehash policy Bypass usage of __detail::__distance_fwd and check for need to rehash when assigning an initializer_list to an unordered_multimap or unordered_multiset. libstdc++-v3/ChangeLog:     * include/bits/hashtable_policy.h     (_Insert_ba

Re: gcc-patches From rewriting mailman settings (Was: [Linaro-TCWG-CI] gcc patch #75674: FAIL: 68 regressions)

Hi all, On Tue, Sep 12, 2023 at 05:00:07PM +0200, Mark Wielaard wrote: > Adding Jeff to CC who is the official gcc-patches mailinglist admin. > [...] > Yes, it is expected for emails that come from domains with a dmarc > policy. That is because the current settings of the gcc-patches > mailinglis

[PATCH] Trivial typo fix in variadic

Fix all occurences of varadic, except for Rust (will be part of another change). gcc/ChangeLog: * config/nvptx/nvptx.h (struct machine_function): Fix typo in variadic. * config/nvptx/nvptx.cc (nvptx_function_arg_advance): Adjust to use fixed name. (nvptx_declare_function_

[PATCH] c++: optimize tsubst_template_decl for function templates

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- r14-2655-g92d1425ca78040 made instantiate_template avoid redundantly performing a specialization lookup when instantiating a function or alias template. This patch applies the same optimization to tsubst_tem

[PATCH] c++: non-dependent assignment checking [PR63198, PR18474]

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for trunk? Patch generatde with -w to avoid noisy whitespace changes. -- >8 -- This patch makes us recognize and check non-dependent simple assigments ahead of time, like we already do for compound assignments. This means the

[PATCH 1/2 v3] Ada: Synchronized private extensions are always limited

Hi Arno, I have added the required “Signed-off-by” tag to the patch and to the change log entry below. I believe for all other aspects I have followed the instructions. For getting the patch applied it states "If you do not have write access and a patch of yours has been approved, but not commi

Re: [PATCH 2/2 v3] Ada: Finalization of constrained subtypes of unconstrained synchronized private extensions

Hi Gary, Thanks for finding that! I have made the recommended change and attached the revised patch, which is also rebased on trunk. Additionally, I have added the “Signed-off-by” tag for legal compliance to the patch, as well as the change log entry as follows: -- Begin change log entry –

Re: [PATCH] tree-optimization/111294 - backwards threader PHI costing

On 9/14/23 07:23, Richard Biener via Gcc-patches wrote: This revives an earlier patch since the problematic code applying extra costs to PHIs in copied blocks we couldn't make any sense of prevents a required threading in this case. Instead of coming up with an artificial other costing the fo

Re: RFC: Introduce -fhardened to enable security-related flags

> From: Sam James > Date: Sun, 17 Sep 2023 05:00:37 +0100 > Hans-Peter Nilsson via Gcc-patches writes: > > >> Date: Tue, 29 Aug 2023 15:42:27 -0400 > >> From: Marek Polacek via Gcc-patches > > > >> Surely, there must be no ABI impact, the option cannot cause > >> severe performance issues, > >

Re: [RFC PATCH 2/2] RISC-V: Update testsuite for type-changed builtins

On 9/6/23 20:17, Tsukasa OI wrote: From: Tsukasa OI This commit replaces the type of the builtin used in the testsuite. Even without this commit, it won't cause any test failures but changed so that no confusion occurs. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbc32.c: Make sig

Re: [PATCH 1/2] RISC-V: Make bit manipulation value / round number and shift amount types for builtins unsigned

On 9/11/23 19:28, Tsukasa OI wrote: From: Tsukasa OI For bit manipulation operations, input(s) and the manipulated output are better to be unsigned like other target-independent builtins like __builtin_bswap32 and __builtin_popcount. Although this is not completely compatible as before (as

Re: [PATCH v1] RISC-V: Bugfix for scalar move with merged operand

On 9/17/23 01:42, Pan Li via Gcc-patches wrote: From: Pan Li Given below example for VLS mode void test (vl_t *u) { vl_t t; long long *p = (long long *)&t; p[0] = p[1] = 2; *u = t; } The vec_set will simplify the insn to vmv.s.x when index is 0, without merged operand. That

Re: [PATCH V2] internal-fn: Support undefined rtx for uninitialized SSA_NAME

Juzhe-Zhong writes: > According to PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 > > As Richard and Richi suggested, we recognize uninitialized SSA_NAME and > convert it > into SCRATCH rtx if the target predicate allows SCRATCH. > > It can help to reduce redundant data move instructions

Re: Re: [PATCH] internal-fn: Convert uninitialized SSA_NAME into SCRATCH rtx[PR110751]

Thanks Richard. Address comment in V2: [PATCH V2] internal-fn: Support undefined rtx for uninitialized SSA_NAME (gnu.org) juzhe.zh...@rivai.ai From: Richard Sandiford Date: 2023-09-17 18:29 To: Juzhe-Zhong CC: gcc-patches; rguenther Subject: Re: [PATCH] internal-fn: Convert uninitialized SS

[PATCH V2] internal-fn: Support undefined rtx for uninitialized SSA_NAME

According to PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 As Richard and Richi suggested, we recognize uninitialized SSA_NAME and convert it into SCRATCH rtx if the target predicate allows SCRATCH. It can help to reduce redundant data move instructions of targets like RISC-V. gcc/Cha

Re: [AArch64][testsuite] Adjust vect_copy_lane_1.c for new code-gen

Prathamesh Kulkarni writes: > Hi, > After 27de9aa152141e7f3ee66372647d0f2cd94c4b90, there's a following > regression: > FAIL: gcc.target/aarch64/vect_copy_lane_1.c scan-assembler-times > ins\\tv0.s\\[1\\], v1.s\\[0\\] 3 > > This happens because for the following function from vect_copy_lane_1.c:

Re: [pushed] [RA]: Improve cost calculation of pseudos with equivalences

On 9/14/23 09:28, Vladimir Makarov via Gcc-patches wrote: I've committed the following patch.  The reason for this patch is explained in its commit message. The patch was successfully bootstrapped and tested on x86-64, aarch64, and ppc64le. ra-equiv-cost.patch_ZN7cObject4dropEP12cOwnedOb

Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

On 9/12/23 00:18, Lehua Ding wrote: Hi Jeff, On 2023/9/12 11:47, Jeff Law wrote: But that condition is _not_ generally sufficient to prevent these insns from existing during sched1.  ie, a pass between split1 and sched1 could create these patterns and successfully match them.  That in turn

[PATCH v2] c++: Catch indirect change of active union member in constexpr [PR101631]

Ping for https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629084.html -- >8 -- This patch adds checks for attempting to change the active member of a union by methods other than a member access expression. To be able to properly distinguish `*(&u.a) = ` from `u.a = `, this patch redoes t

Re: [PATCH] AArch64: Improve immediate expansion [PR105928]

Wilco Dijkstra writes: > Support immediate expansion of immediates which can be created from 2 MOVKs > and a shifted ORR or BIC instruction. Change aarch64_split_dimode_const_store > to apply if we save one instruction. > > This reduces the number of 4-instruction immediates in SPECINT/FP by 5%.

Re: [PATCH] internal-fn: Convert uninitialized SSA_NAME into SCRATCH rtx[PR110751]

Juzhe-Zhong writes: > According to PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751 > > As Richard and Richi suggested, we recognize uninitialized SSA_NAME and > convert it > into SCRATCH rtx if the target predicate allows SCRATCH. > > It can help to reduce redundant data move instructions

[r14-4046 Regression] FAIL: 23_containers/vector/bool/110807.cc -std=gnu++17 (test for excess errors) on Linux/x86_64

On Linux/x86_64, 3a0e01f6bb1d6ec444001f2caea6ef43a4a83e3a is the first bad commit commit 3a0e01f6bb1d6ec444001f2caea6ef43a4a83e3a Author: Jonathan Wakely Date: Fri Sep 1 21:27:57 2023 +0100 libstdc++: Add support for running tests with multiple -std options caused FAIL: 23_containers/vec

[PATCH v1] RISC-V: Bugfix for scalar move with merged operand

From: Pan Li Given below example for VLS mode void test (vl_t *u) { vl_t t; long long *p = (long long *)&t; p[0] = p[1] = 2; *u = t; } The vec_set will simplify the insn to vmv.s.x when index is 0, without merged operand. That will result in some problems in DCE, aka: 1: 137[DI] = a