On 05/12/2022 10:40, Jørgen Kvalsvik wrote:
> This patch adds support in gcc+gcov for modified condition/decision
> coverage (MC/DC) with the -fprofile-conditions flag. MC/DC is a type of
> test/code coverage and it is particularly important in the avation and
> automotive industries for safety-cri
Hi, I have checked SDnode in LLVM which is a similiar data structure with RTX
in GCC.
The SDnode in LLVM occupy 80bytes.
Can we have some tool to test the memory consuming of the whole GCC with
extended-size RTX?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-11 04:42
To: juzhe.zhong; ja
On 4/10/23 1:49 PM, Harald Anlauf via Fortran wrote:
Dear all,
when comparing formal and actual arguments of a procedure, there was no
check of rank for derived types from intrinsic module ISO_C_BINDING.
This could lead to a wrong resolution of generic procedures with dummy
argument of related t
Another feasible solution: Maybe we can drop supporting segment intrinsics
in upstream GCC.
We let the downstream companies support segment in their own downstream GCC ?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-11 04:42
To: juzhe.zhong; jakub
CC: gcc-patches; kito.cheng; palmer; rich
I don't know, maybe we can try to ask rvv-intrinsic-doc define so many tuple
types and try to
make them reduce the api && tuple types?
I am going to remove all FP16 vector to see whether we can reduce machine modes
<= 256.
I think it may be probably helping to fix that.
juzhe.zh...@rivai.ai
Gerald Pfeifer writes:
> On Thu, 6 Apr 2023, Arsen Arsenović wrote:
>> maintainer-scripts/ChangeLog:
>>
>> * update_web_docs_git: Add updated Texinfo to PATH
>
> Do we really need to adjust PATH, or could we just introduce a MAKEINFO
> variable, something like
>
> if [ x${MAKEINFO}x = x
On Thu, 6 Apr 2023, Arsen Arsenović wrote:
> I must ask that whoever decides to apply/update the script tests
> texi2any with a simple example, like
>
> echo @node Top | ~/texinfo/install-git/bin/makeinfo --html -o -
>
> ... before updating; this should be a representative enough smoke test.
>
On Thu, 6 Apr 2023, Arsen Arsenović wrote:
> maintainer-scripts/ChangeLog:
>
> * update_web_docs_git: Add updated Texinfo to PATH
Do we really need to adjust PATH, or could we just introduce a MAKEINFO
variable, something like
if [ x${MAKEINFO}x = xx ]; then
if [ -x /home/gccadmin/t
On Mon, 10 Apr 2023 at 17:57, Jeff Law wrote:
>
>
>
> On 4/9/23 23:07, Lin Sinan via Gcc-patches wrote:
> > From: Sinan Lin
> >
> > there is no need to split an xori/ori with an small constant. take the test
> > case `int foo(int idx) { return idx|3; }` as an example,
> >
> > rv64im_zba generates
On 4/9/23 21:11, Kito Cheng wrote:
I think one keypoint here is -fzero-call-used-regs=* emit zeroing
instruction before return, that means there won't be any vector
operations between return and zeroing instructions, so we don't need
to restore the vcsr after zeroing.
Oh yea, makes perfect
Dear all,
when comparing formal and actual arguments of a procedure, there was no
check of rank for derived types from intrinsic module ISO_C_BINDING.
This could lead to a wrong resolution of generic procedures with dummy
argument of related types, see PR. This was likely an oversight.
The attac
On 4/10/23 09:22, juzhe.zh...@rivai.ai wrote:
Yeah, aarch64 already has 178, RVV has much more types than aarch64...
You can see intrinsic doc:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/tuple-type-for-seg-load-store/auto-generated/intrinsic_funcs/02_vector_unit-stride_segmen
On 4/10/23 09:33, juzhe.zh...@rivai.ai wrote:
I saw many redundant scalar modes:
E_CDImode, /* machmode.def:267 */
#define HAVE_CDImode
#ifdef USE_ENUM_MODES
#define CDImode E_CDImode
#else
#define CDImode (complex_mode ((complex_mode::from_int) E_CDImode))
#endif
E_CTImode
On 4/10/23 09:18, Jakub Jelinek wrote:
On Mon, Apr 10, 2023 at 08:54:12AM -0600, Jeff Law wrote:
This is likely going to be very controversial. It's going to increase the
size of two of most heavily used data structures in GCC (rtx and trees).
The first thing I would ask is whether or not w
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-10 Patrick O'Neill
* sync.md (mem_thread_fence_1): Change fence depending on the
given memory model.
Signed-off-by: Patrick O'Neill
---
v3
These tests cover basic cases to ensure the atomic mappings follow the
strengthened Table A.6 mappings that are compatible with Table A.7.
2023-04-10 Patrick O'Neill
* amo-table-a-6-amo-add-1.c: New test.
* amo-table-a-6-amo-add-2.c: Likewise.
* amo-table-a-6-amo-add-3.c:
This change brings atomic loads in line with table A.6 of the ISA
manual.
2023-04-10 Patrick O'Neill
* sync.md (atomic_load): Implement atomic load mapping.
Signed-off-by: Patrick O'Neill
---
v3 Changelog:
* Add this patch
---
gcc/config/riscv/sync.md | 27 ++-
This change makes atomic stores strictly stronger than table A.6 of the
ISA manual. This mapping makes the overall patchset compatible with
table A.7 as well.
2023-04-10 Patrick O'Neill
PR target/89835
* sync.md (atomic_store): Use simple store instruction in
combination
This patch enforces SEQ_CST for atomic compare_exchange ops.
Replace Fence/LR.aq/SC.aq pairs with SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-10 Patrick O'Neill
* sync.md: Change FENCE/LR.aq/SC.aq into sequentially
consistent LR.aqrl/SC.rl pai
Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs
as needed.
Atomic compare and exchange ops provide success and failure memory
models. C++17 and later place no restrictions on the relative strength
of each model, so ensure we cover both by using a model that enforces
the ord
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2023-04-10 Patrick O'Neill
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.rl pair.
Signed-off-by: Patrick O'Neill
---
libgcc/config/riscv/at
This patch sets the relevant .rl bits on amo operations.
2023-04-10 Patrick O'Neill
* riscv.cc (riscv_print_operand): change behavior of %A to
include release bits.
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 7 ++-
1 file changed, 6 insertions(+), 1 del
Atomic operations with the appropriate bits set already enfore release
semantics. Remove unnecessary release fences from atomic ops.
This change brings AMO ops in line with table A.6 of the ISA manual.
2023-04-10 Patrick O'Neill
* riscv.cc (riscv_memmodel_needs_amo_acquire): Change func
Remove references to MEMMODEL_SYNC_* models by converting via
memmodel_base().
2023-04-10 Patrick O'Neill
* riscv.cc: Remove MEMMODEL_SYNC_* cases and sanitize memmodel
input with memmodel_base
Signed-off-by: Patrick O'Neill
---
gcc/config/riscv/riscv.cc | 11 +++
1 fi
This patchset aims to make the RISCV atomics implementation stronger
than the recommended mapping present in table A.6 of the ISA manual.
https://github.com/riscv/riscv-isa-manual/blob/c7cf84547b3aefacab5463add1734c1602b67a49/src/memory.tex#L1083-L1157
The current mapping in GCC is not internal
On 4/9/23 23:07, Lin Sinan via Gcc-patches wrote:
From: Sinan Lin
there is no need to split an xori/ori with an small constant. take the test
case `int foo(int idx) { return idx|3; }` as an example,
rv64im_zba generates:
ori a0,a0,3
ret
but, rv64im_zba_zbs generates:
I saw many redundant scalar modes:
E_CDImode, /* machmode.def:267 */
#define HAVE_CDImode
#ifdef USE_ENUM_MODES
#define CDImode E_CDImode
#else
#define CDImode (complex_mode ((complex_mode::from_int) E_CDImode))
#endif
E_CTImode, /* machmode.def:267 */
#define HAVE_C
Yeah, aarch64 already has 178, RVV has much more types than aarch64...
You can see intrinsic doc:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/tuple-type-for-seg-load-store/auto-generated/intrinsic_funcs/02_vector_unit-stride_segment_load_store_instructions_zvlsseg.md
api number e
On Mon, Apr 10, 2023 at 08:54:12AM -0600, Jeff Law wrote:
> This is likely going to be very controversial. It's going to increase the
> size of two of most heavily used data structures in GCC (rtx and trees).
>
> The first thing I would ask is whether or not we really need the full matrix
> in pr
ARM SVE has：svint8_t, svint8x2_t, svint8x3_t, svint8x4_t
As far as I known, they don't have tuple type for partial vector.
However, for RVV not only has vint8m1_t, vint8m1x2_t, vint8m1x3_t,
vint8m1x4_t, vint8m1x5_t, vint8m1x6_t, vint8m1x7_t, vint8m1x8_t
But also, we have vint8mf8_t, vint8mf8x2_t,
On Mon, Apr 10, 2023 at 10:48:08PM +0800, juzhe.zh...@rivai.ai wrote:
> * rtl.h (struct GTY): Ditto.
> --- a/gcc/rtl.h
> +++ b/gcc/rtl.h
> @@ -313,7 +313,7 @@ struct GTY((desc("0"), tag("0"),
>ENUM_BITFIELD(rtx_code) code: 16;
>
>/* The kind of value the expression has. */
> -
Since RVV has much more types than aarch64.
You can see rvv-intrinsic doc there are so many rvv intrinsics:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/tuple-type-for-seg-load-store/auto-generated/intrinsic_funcs/02_vector_unit-stride_segment_load_store_instructions_zvlsseg.md
Th
On 4/10/23 04:56, Lin Sinan wrote:
From: Sinan Lin
tell gcc that zbkb has these two spn to enable some optimizations. e.g.
1) the rrotate_expr could match to rotrm3 during expand; 2) hook up
__builtin_bswap64 with `rev8` in zbkb64.
---
gcc/config/riscv/bitmanip.md | 6 +++---
1 file chang
On 4/10/23 08:48, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
According RVV ISA:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-type-register-vtype
We have LMUL: 1/8, 1/4, 1/2, 1, 2, 4, 8
Also, for segment instructions, we have tuple type for NF = 2 ~ 8.
For example,
From: Juzhe-Zhong
According RVV ISA:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-type-register-vtype
We have LMUL: 1/8, 1/4, 1/2, 1, 2, 4, 8
Also, for segment instructions, we have tuple type for NF = 2 ~ 8.
For example, for LMUL = 1/2, SEW = 32, we have vint32mf2_t,
we w
From: Sinan Lin
tell gcc that zbkb has these two spn to enable some optimizations. e.g.
1) the rrotate_expr could match to rotrm3 during expand; 2) hook up
__builtin_bswap64 with `rev8` in zbkb64.
---
gcc/config/riscv/bitmanip.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
Sorry, it's my question. I still have some questions that I haven't
understood, so I haven't replied to the email yet.:-(
在 2023/4/10 下午5:04, Xi Ruoyao 写道:
Ping. Or maybe I've lost some replies here because my mail server
crashed several days ago :).
On Wed, 2023-03-29 at 02:01 +0800, Xi Ruo
Hi Jeff,
on 2023/4/10 10:09, Jiufu Guo via Gcc-patches wrote:
> Hi,
>
> In this test case (float128-cmp2-runnable.c), the instruction
> xscmpexpqp is used to support a few builtins e.g.
> __builtin_vsx_scalar_cmp_exp_qp_eq on _Float128.
> This instruction handles the whole 128bits of the vector,
Ping. Or maybe I've lost some replies here because my mail server
crashed several days ago :).
On Wed, 2023-03-29 at 02:01 +0800, Xi Ruoyao wrote:
> LoongArch backend used to save all GARs for a function with variable
> arguments. But sometimes a function only accepts variable arguments
> for
>
On Sat, Apr 08, 2023 at 06:25:32PM -0600, Jeff Law wrote:
>
>
> On 4/6/23 08:21, Eric Botcazou wrote:
>
> > > So, perhaps just in the return op0; case add further code for
> > > WORD_REGISTER_OPERATIONS and sub-word modes which will call nonzero_bits
> > > again for the word mode and decide if i
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