Re: [PATCH] [x86] define builtins for "shared" avxneconvert-avx512bf16vl builtins.

On Fri, Nov 18, 2022 at 3:50 PM Jakub Jelinek wrote: > > On Fri, Nov 18, 2022 at 09:45:22AM +0800, liuhongt via Gcc-patches wrote: > > This should fix incorrect error when call those builtin with > > -mavxneconvert and w/o -mavx512bf16 -mavx512vl. > > > > Bootstrapped and regtested on x86_64-pc-li

Re: [PATCH] [x86] define builtins for "shared" avxneconvert-avx512bf16vl builtins.

On Fri, Nov 18, 2022 at 09:45:22AM +0800, liuhongt via Gcc-patches wrote: > This should fix incorrect error when call those builtin with > -mavxneconvert and w/o -mavx512bf16 -mavx512vl. > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} > Ready to push to trunk. > > gcc/ChangeLog: > >

Re: [PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Thu, Nov 17, 2022 at 07:15:05PM -0500, Marek Polacek wrote: > > --- gcc/cp/decl.cc.jj 2022-11-16 14:44:43.692339668 +0100 > > +++ gcc/cp/decl.cc 2022-11-17 20:53:44.102011594 +0100 > > @@ -5600,6 +5600,57 @@ groktypename (cp_decl_specifier_seq *typ > >return type; > > } > > > > +/*

[PATCH] tree-optimization/107647 - avoid FMA from SLP with -ffp-contract=off

Only with -ffp-contract=fast we can synthesize FMA operations like vfmaddsub231ps, so properly guard the transform in SLP pattern detection. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. PR tree-optimization/107647 * tree-vect-slp-patterns.cc (addsub_pattern::recogn

Re: [PATCH] RISC-V: Note that __builtin_riscv_pause() implies Xgnuzihintpausestate

Wait, what's Xgnuzihintpausestate??? On Fri, Nov 18, 2022 at 12:30 PM Palmer Dabbelt wrote: > > gcc/ChangeLog: > > * doc/extend.texi (__builtin_riscv_pause): Imply > Xgnuzihintpausestate. > --- > gcc/doc/extend.texi | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > >

Re: [PATCHv2, rs6000] Enable have_cbranchcc4 on rs6000

Hi David, 在 2022/11/17 21:24, David Edelsohn 写道: > This is better, but the pattern should be near and after the existing > cbranch4 patterns earlier in the file, not the *cbranch pattern.  It > doesn't match the comment. Sure, I will put it after existing "cbranch4" patterns. > > Why are you u

Re: Re: [PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.

Thank you very much for your example! I have sent a new patch according to your guide. "Jeff Law" wrote: > > On 11/17/22 02:53, Yixuan Chen wrote: > > 2022-11-17 Yixuan Chen > > > > * gcc/testsuite/gcc.dg/pr25521.c: Add compile option > > "-msmall-data-limit=0

[PATCH] optimize the testcase for architectures that use ".srodata"

2022-11-18 Yixuan Chen * gcc.dg/pr25521.c: optimize the testcast for architectures that use ".srodata" testsuite/gcc.dg/pr25521.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/pr25521.c b/gcc/testsuite/gcc.dg/pr25521.c index 74fe2ae6626..6336

Re: [PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.

Thank you very much for your patient explanation！ Palmer Dabbelt 于2022年11月18日 周五13:02写道： > On Thu, 17 Nov 2022 19:30:23 PST (-0800), oriachi...@gmail.com wrote: > > Got it, I used to regard this test case as targeting at test if the const > > data would use the ".rodata" section. > > Sorry, I'm n

Re: [PATCH] RISC-V: Add support for AIA ISA extensions (Ssaia and Smaia)

On Thu, 17 Nov 2022 18:12:23 PST (-0800), christoph.muell...@vrull.eu wrote: From: Christoph Müllner This patch adds support for the two AIA ISA extensions Ssaia and Smaia. They are not relelvant for the compiler, but the assembler might want to validate the CSRs. Therefore, all this patch does

Re: [PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.

On Thu, 17 Nov 2022 19:30:23 PST (-0800), oriachi...@gmail.com wrote: Got it, I used to regard this test case as targeting at test if the const data would use the ".rodata" section. Sorry, I'm not quite sure what you're trying to say here. Here's a dump of how I see things: In some targets

Re: [PATCH 2/7] riscv: riscv-cores.def: Add T-Head XuanTie C906

On Thu, 17 Nov 2022 20:50:19 PST (-0800), gcc-patches@gcc.gnu.org wrote: On Sun, Nov 13, 2022 at 10:46:31PM +0100, Christoph Muellner wrote: From: Christoph Müllner This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". The C906 is shipped for quite some time (it is the co

Re: [PATCH] RISC-V: branch-(not)equals-zero compares against $zero

On Thu, 17 Nov 2022 14:44:31 PST (-0800), jeffreya...@gmail.com wrote: On 11/8/22 12:55, Philipp Tomsich wrote: If we are testing a register or a paradoxical subreg (i.e. anything that is not a partial subreg) for equality/non-equality with zero, we can generate a branch that compares against $

Re: [PATCH 2/7] riscv: riscv-cores.def: Add T-Head XuanTie C906

On Sun, Nov 13, 2022 at 10:46:31PM +0100, Christoph Muellner wrote: > From: Christoph Müllner > > This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". > The C906 is shipped for quite some time (it is the core of the Allwinner D1). > Note, that the tuning struct for the C906

Re: [PATCH 7/7] riscv: Add basic extension support for XTheadFmv and XTheadInt

On Sun, Nov 13, 2022 at 10:46:36PM +0100, Christoph Muellner wrote: > From: Christoph Müllner > > This patch add basic support for the XTheadFmv and XTheadInt > ISA extension. As both extensions only contain instruction, > which are not supposed to be emitted by the compiler, the support > only c

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

On Thu, 17 Nov 2022 18:14:18 PST (-0800), christoph.muell...@vrull.eu wrote: On Wed, Nov 9, 2022 at 4:01 AM Palmer Dabbelt wrote: These extensions were recently frozen [1]. As per Andrew's post [2] we're meant to ignore these in software, this just adds them to the list of allowed extensions

[PATCH] RISC-V: Note that __builtin_riscv_pause() implies Xgnuzihintpausestate

gcc/ChangeLog: * doc/extend.texi (__builtin_riscv_pause): Imply Xgnuzihintpausestate. --- gcc/doc/extend.texi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index b1dd39e64b8..26f14e61bc8 100644 --- a/gcc/doc/extend

Re: [PATCH] invoke: RISC-V's -march doesn't take ISA strings

On Wed, 09 Nov 2022 01:52:12 PST (-0800), christoph.muell...@vrull.eu wrote: On Wed, Nov 9, 2022 at 4:00 AM Palmer Dabbelt wrote: On Tue, 08 Nov 2022 05:40:10 PST (-0800), christoph.muell...@vrull.eu wrote: > On Mon, Nov 7, 2022 at 8:01 PM Palmer Dabbelt wrote: > >> The docs say we take ISA s

Re: [PATCH 5/7] riscv: thead: Add support for XTheadBb ISA extension

On Sun, Nov 13, 2022 at 10:46:34PM +0100, Christoph Muellner wrote: > +(define_expand "extv" > + [(set (match_operand:GPR 0 "register_operand" "=r") > + (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") > + (match_operand 2 "const_int_operand") > +

Re: [PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.

Got it, I used to regard this test case as targeting at test if the const data would use the ".rodata" section. Palmer Dabbelt 于2022年11月18日周五 07:59写道： > On Thu, 17 Nov 2022 13:50:00 PST (-0800), gcc-patches@gcc.gnu.org wrote: > > > > On 11/17/22 02:53, Yixuan Chen wrote: > >> 2022-11-17 Yixuan

[PATCH 2/2] Fix PR middle-end/107705: ICE after reclaration error

From: Andrew Pinski The problem here is after we created a call expression in the C front-end, we replace the decl type with an error mark node. We then end up calling aggregate_value_p with the call expression with the decl with the error mark as the type and we ICE. The fix is to check the fun

[PATCH 1/2] Fix PRs 106764, 106765, and 107307, all ICE after invalid re-declaration

From: Andrew Pinski The problem here is the gimplifier returns GS_ERROR but in some cases we don't check that soon enough and try to do other work which could crash. So the fix in these two cases is to return GS_ERROR early if the gimplify_* functions had return GS_ERROR. OK? Bootstrapped and te

Re: [PATCH 3/8]middle-end: Support extractions of subvectors from arbitrary element position inside a vector

On Thu, Nov 17, 2022 at 9:59 PM Richard Sandiford wrote: > > Hongtao Liu writes: > > On Thu, Nov 17, 2022 at 5:39 PM Richard Sandiford > > wrote: > >> > >> Hongtao Liu writes: > >> > On Wed, Nov 16, 2022 at 1:39 AM Richard Sandiford > >> > wrote: > >> >> > >> >> Tamar Christina writes: > >> >

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

On Wed, Nov 9, 2022 at 4:01 AM Palmer Dabbelt wrote: > These extensions were recently frozen [1]. As per Andrew's post [2] > we're meant to ignore these in software, this just adds them to the list > of allowed extensions and otherwise ignores them. I added these under > SPEC_CLASS_NONE even th

[PATCH] RISC-V: Add support for AIA ISA extensions (Ssaia and Smaia)

From: Christoph Müllner This patch adds support for the two AIA ISA extensions Ssaia and Smaia. They are not relelvant for the compiler, but the assembler might want to validate the CSRs. Therefore, all this patch does is recognize the extension name, emit a feature macro (incl. a test). Signed-

[PATCH] [x86] define builtins for "shared" avxneconvert-avx512bf16vl builtins.

This should fix incorrect error when call those builtin with -mavxneconvert and w/o -mavx512bf16 -mavx512vl. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} Ready to push to trunk. gcc/ChangeLog: * config/i386/i386-builtins.cc (def_builtin): Hanlde "shared" avx512bf16vl-

Re: [PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On 11/17/22 15:42, Jakub Jelinek wrote: On Thu, Nov 17, 2022 at 07:42:40PM +0100, Jakub Jelinek via Gcc-patches wrote: I thought for older C++ this is to catch void foo () { constexpr int a = ({ static constexpr int b = 2; b; }); } and for C++23 the only 3 spots that diagnose those. But perha

Re: [PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Thu, Nov 17, 2022 at 09:42:17PM +0100, Jakub Jelinek wrote: > On Thu, Nov 17, 2022 at 07:42:40PM +0100, Jakub Jelinek via Gcc-patches wrote: > > I thought for older C++ this is to catch > > void > > foo () > > { > > constexpr int a = ({ static constexpr int b = 2; b; }); > > } > > and for C++2

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

On Fri, 18 Nov 2022 at 00:56, Palmer Dabbelt wrote: > > On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: > > > > On 11/12/22 14:29, Philipp Tomsich wrote: > >> Users might use explicit arithmetic operations to create a mask and > >> then and it, in a sequence like > >>

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

On Fri, 18 Nov 2022 at 00:41, Jeff Law wrote: > > > On 11/12/22 14:29, Philipp Tomsich wrote: > > Users might use explicit arithmetic operations to create a mask and > > then and it, in a sequence like > > cond = (bits >> SHIFT) & 1; > > mask = ~(cond - 1); > > val &= mask; > > whic

Re: [PATCH] c++: Reject UDLs in certain contexts [PR105300]

On 11/16/22 20:12, Marek Polacek wrote: On Wed, Nov 16, 2022 at 08:22:39AM -0500, Jason Merrill wrote: On 11/15/22 19:35, Marek Polacek wrote: On Tue, Nov 15, 2022 at 06:58:39PM -0500, Jason Merrill wrote: On 11/12/22 06:53, Marek Polacek wrote: In this PR, we are crashing because we've encou

Re: [PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.

On Thu, 17 Nov 2022 13:50:00 PST (-0800), gcc-patches@gcc.gnu.org wrote: On 11/17/22 02:53, Yixuan Chen wrote: 2022-11-17 Yixuan Chen * gcc/testsuite/gcc.dg/pr25521.c: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv. --- gcc/testsuite/gcc.dg/p

Re: [PATCH] c++: constinit on pointer to function [PR104066]

On 11/17/22 13:38, Marek Polacek wrote: [dcl.constinit]: "The constinit specifier shall be applied only to a declaration of a variable with static or thread storage duration." Thus, this ought to be OK: constinit void (*p)() = nullptr; but the error message I introduced when implementing co

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: On 11/12/22 14:29, Philipp Tomsich wrote: Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; whic

Re: [PATCH 2/5] c++: Set the locus of the function result decl

On 11/17/22 14:02, Bernhard Reutner-Fischer wrote: On Thu, 17 Nov 2022 09:53:32 -0500 Jason Merrill wrote: On 11/17/22 03:56, Bernhard Reutner-Fischer wrote: On Tue, 15 Nov 2022 18:52:41 -0500 Jason Merrill wrote: On 11/12/22 13:45, Bernhard Reutner-Fischer wrote: gcc/cp/ChangeLog:

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

On 11/12/22 14:29, Philipp Tomsich wrote: Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; which will present as a single-bit sign-extract. Dependening on what combina

Re: [PATCH 6/7] RISC-V: Support immediates in XVentanaCondOps

On 11/12/22 14:29, Philipp Tomsich wrote: When if-conversion encounters sequences using immediates, the sequences can't trivially map back onto vt.maskc/vt.maskcn (even if benefitial) due to vt.maskc and vt.maskcn not having immediate forms. This adds a splitter to rewrite opportunities for XV

Re: [PATCH 5/7] RISC-V: Recognize bexti in negated if-conversion

On 11/12/22 14:29, Philipp Tomsich wrote: While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can trigger conversion into efficient branchless sequences - with Zbs (bexti + neg + and) - with XVentanaCondOps (andi + vt.maskc) the inverted/negated case results in andi a5,a

Re: [PATCH 3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc

On 11/12/22 14:29, Philipp Tomsich wrote: When if-conversion in noce_try_store_flag_mask starts the sequence off with an order-operator, our patterns for vt.maskc will receive the result of the order-operator as a register argument; consequently, they can't know that the result will be either 1

Re: [PATCH 2/7] RISC-V: Generate vt.maskc on noce_try_store_flag_mask if-conversion

On 11/12/22 14:29, Philipp Tomsich wrote: Adds a pattern to map the output of noce_try_store_flag_mask if-conversion in the combiner onto vt.maskc; the input patterns supported are similar to the following: (set (reg/v/f:DI 75 [ ]) (and:DI (neg:DI (ne:DI (reg:DI 82)

Re: [PATCH 1/7] RISC-V: Recognize xventanacondops extension

On 11/12/22 14:29, Philipp Tomsich wrote: This adds the xventanacondops extension to the option parsing and as a default for the ventana-vt1 core: gcc/Changelog: * common/config/riscv/riscv-common.cc: Recognize "xventanacondops" as part of an architecture string. *

Re: [PATCH] RISC-V: branch-(not)equals-zero compares against $zero

On 11/8/22 12:55, Philipp Tomsich wrote: If we are testing a register or a paradoxical subreg (i.e. anything that is not a partial subreg) for equality/non-equality with zero, we can generate a branch that compares against $zero. This will work for QI, HI, SI and DImode, so we enable this for

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

On Thu, Nov 17, 2022 at 1:55 PM Andrew Pinski wrote: > > On Thu, Nov 17, 2022 at 1:46 PM Fangrui Song wrote: > > > > On Thu, Nov 17, 2022 at 1:37 PM Andrew Pinski wrote: > > > > > > On Thu, Nov 17, 2022 at 1:21 PM maskray--- via Gcc-patches > > > wrote: > > > > > > > > > +.. option:: -mdirect-e

Re: [PATCH] match.pd: rewrite select to branchless expression

On 11/8/22 13:15, Andrew Pinski via Gcc-patches wrote: On Tue, Nov 8, 2022 at 12:02 PM Michael Collison wrote: This patches transforms (cond (and (x , 0x1) == 0), y, (z op y)) into (-(and (x , 0x1)) & z ) op y, where op is a '^' or a '|'. It also transforms (cond (and (x , 0x1) != 0), (z op y

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

On Thu, Nov 17, 2022 at 1:46 PM Fangrui Song wrote: > > On Thu, Nov 17, 2022 at 1:37 PM Andrew Pinski wrote: > > > > On Thu, Nov 17, 2022 at 1:21 PM maskray--- via Gcc-patches > > wrote: > > > > > > > +.. option:: -mdirect-extern-access, -mno-direct-extern-access > > > > + > > > > + Use direct

Re: [PATCH] Ver.2: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv.

On 11/17/22 02:53, Yixuan Chen wrote: 2022-11-17 Yixuan Chen * gcc/testsuite/gcc.dg/pr25521.c: Add compile option "-msmall-data-limit=0" to avoid using .srodata section for riscv. --- gcc/testsuite/gcc.dg/pr25521.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

On Thu, Nov 17, 2022 at 1:37 PM Andrew Pinski wrote: > > On Thu, Nov 17, 2022 at 1:21 PM maskray--- via Gcc-patches > wrote: > > > > > +.. option:: -mdirect-extern-access, -mno-direct-extern-access > > > + > > > + Use direct accesses for external data symbols. It avoids a GOT > > > indirection

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

On Thu, Nov 17, 2022 at 1:21 PM maskray--- via Gcc-patches wrote: > > > +.. option:: -mdirect-extern-access, -mno-direct-extern-access > > + > > + Use direct accesses for external data symbols. It avoids a GOT > > indirection > > + on all external data symbols with :option:`-fpie` or :option:`

Re: [PATCH 4/6] diagnostics: libcpp: Add LC_GEN linemaps to support in-memory buffers

On Sat, Nov 05, 2022 at 12:23:28PM -0400, David Malcolm wrote: > On Fri, 2022-11-04 at 09:44 -0400, Lewis Hyatt via Gcc-patches wrote: > [...snip...] > > > > diff --git a/gcc/c-family/c-common.cc b/gcc/c-family/c-common.cc > > index 5890c18bdc3..2935d7fb236 100644 > > --- a/gcc/c-family/c-common.c

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

+.. option:: -mdirect-extern-access, -mno-direct-extern-access + + Use direct accesses for external data symbols. It avoids a GOT indirection + on all external data symbols with :option:`-fpie` or :option:`-fPIE`. This is + useful for executables linked with :option:`-static` or :option:`-s

Re: [PATCH]AArch64 Fix vector re-interpretation between partial SIMD modes

Tamar Christina writes: > Hi All, > > While writing a patch series I started getting incorrect codegen out from > VEC_PERM on partial struct types. > > It turns out that this was happening because the TARGET_CAN_CHANGE_MODE_CLASS > implementation has a slight bug in it. The hook only checked for

[PATCH] libcpp: Add missing config for --enable-valgrind-annotations [PR107691]

--- ceb17928e5d1d5 copied (parts of) the valgrind annotation checks from gcc to libcpp. The above copies the missing pieces to libcpp to diagnose when libcpp is configured with --enable-valgrind-annotations but valgrind is not installed. Tested with --enable-valgrind-annotations without valgrind i

Re: [PATCH] ARM: Make ARMv8-M attribute cmse_nonsecure_call work in Ada

On Mon, Oct 24, 2022 at 9:55 AM Eric Botcazou via Gcc-patches wrote: > > Hi, > > until most other machine attributes, this one does not work in Ada because, > while it applies to pointer-to-function types, it is explicitly marked as > requiring declarations in the implementation. > > Now, in Ada,

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

On Thu, Nov 17, 2022 at 5:30 PM Richard Sandiford via Gcc-patches wrote: > > Wilco Dijkstra writes: > > Hi Richard, > > > >> Can you go into more detail about: > >> > >>Use :option:`-mdirect-extern-access` either in shared libraries or in > >>executables, but not in both. Protected symbo

[PATCH] Fortran: reject NULL actual argument without explicit interface [PR107576]

Dear all, one cannot pass a NULL actual argument to a procedure without an explicit interface. This is detected and reported by NAG and Intel. (Cray accepts this silently, and some other brands ICE.) The testcase by Gerhard even tricked gfortran into inconsistent behavior which could lead to an

Re: [PATCH] [range-ops] Implement sqrt.

On Thu, 17 Nov 2022, Jakub Jelinek via Gcc-patches wrote: > On Thu, Nov 17, 2022 at 06:59:45PM +, Joseph Myers wrote: > > On Thu, 17 Nov 2022, Aldy Hernandez via Gcc-patches wrote: > > > > > So... is the optimization wrong? Are we not allowed to substitute > > > that NAN if we know it's gonn

[PATCH] c++, v4: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Thu, Nov 17, 2022 at 07:42:40PM +0100, Jakub Jelinek via Gcc-patches wrote: > I thought for older C++ this is to catch > void > foo () > { > constexpr int a = ({ static constexpr int b = 2; b; }); > } > and for C++23 the only 3 spots that diagnose those. > But perhaps for C++20 or older we can

Re: [PATCH][GCC] arm: Add support for new frame unwinding instruction "0xb5".

On Thu, Nov 10, 2022 at 10:38 AM Srinath Parvathaneni via Gcc-patches wrote: > > Hi, > > This patch adds support for Arm frame unwinding instruction "0xb5" [1]. When > an exception is taken and "0xb5" instruction is encounter during runtime > stack-unwinding, we use effective vsp as modifier in po

Re: [Patch Arm] Fix PR 92999

On Fri, Nov 11, 2022 at 9:50 PM Ramana Radhakrishnan wrote: > > On Thu, Nov 10, 2022 at 7:46 PM Ramana Radhakrishnan > wrote: > > > > On Thu, Nov 10, 2022 at 6:03 PM Richard Earnshaw > > wrote: > > > > > > > > > > > > On 10/11/2022 17:21, Richard Earnshaw via Gcc-patches wrote: > > > > > > > > >

Re: [PATCH v2] tree-object-size: Support strndup and strdup

Ping! On 2022-11-04 08:48, Siddhesh Poyarekar wrote: Use string length of input to strdup to determine the usable size of the resulting object. Avoid doing the same for strndup since there's a chance that the input may be too large, resulting in an unnecessary overhead or worse, the input may n

Re: [PATCH] [range-ops] Implement sqrt.

On Thu, Nov 17, 2022 at 06:59:45PM +, Joseph Myers wrote: > On Thu, 17 Nov 2022, Aldy Hernandez via Gcc-patches wrote: > > > So... is the optimization wrong? Are we not allowed to substitute > > that NAN if we know it's gonna happen? Should we also allow F F F F F > > in the test? Or someth

Re: [PATCH 2/5] c++: Set the locus of the function result decl

On Thu, 17 Nov 2022 09:53:32 -0500 Jason Merrill wrote: > On 11/17/22 03:56, Bernhard Reutner-Fischer wrote: > > On Tue, 15 Nov 2022 18:52:41 -0500 > > Jason Merrill wrote: > > > >> On 11/12/22 13:45, Bernhard Reutner-Fischer wrote: > >>> gcc/cp/ChangeLog: > >>> > >>> * decl.cc (start_fun

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, 17 Nov 2022 at 19:56, Andrew Waterman wrote: > > On Thu, Nov 17, 2022 at 10:52 AM Philipp Tomsich > wrote: > > > > On Thu, 17 Nov 2022 at 19:33, Andrew Waterman wrote: > > > > > > Am I wrong to worry that this will increase dynamic instruction count > > > when used in a loop? The obviou

Re: [PATCH] [range-ops] Implement sqrt.

On Thu, 17 Nov 2022, Aldy Hernandez via Gcc-patches wrote: > So... is the optimization wrong? Are we not allowed to substitute > that NAN if we know it's gonna happen? Should we also allow F F F F F > in the test? Or something else? This seems like the usual ambiguity about what transformation

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, 17 Nov 2022 at 19:28, Andrew Pinski wrote: > > On Thu, Nov 17, 2022 at 10:25 AM Andrew Pinski wrote: > > > > On Sun, Nov 13, 2022 at 12:51 PM Philipp Tomsich > > wrote: > > > > > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) > > > ..." > > > that can be expre

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, Nov 17, 2022 at 10:52 AM Philipp Tomsich wrote: > > On Thu, 17 Nov 2022 at 19:33, Andrew Waterman wrote: > > > > Am I wrong to worry that this will increase dynamic instruction count > > when used in a loop? The obvious code is more efficient when the > > constant loads can be hoisted ou

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, 17 Nov 2022 at 19:33, Andrew Waterman wrote: > > Am I wrong to worry that this will increase dynamic instruction count > when used in a loop? The obvious code is more efficient when the > constant loads can be hoisted out of a loop. Or does the cost model > account for this somehow? Wit

Re: [PATCH] c++, v3: Implement C++23 P2647R1 - Permitting static constexpr variables in constexpr functions

On Thu, Nov 17, 2022 at 09:42:18AM -0500, Jason Merrill wrote: > > --- gcc/cp/constexpr.cc.jj 2022-11-17 08:48:30.530357181 +0100 > > +++ gcc/cp/constexpr.cc 2022-11-17 09:56:50.479522863 +0100 > > @@ -7098,7 +7098,8 @@ cxx_eval_constant_expression (const cons > > && (TREE_STATIC (r) >

[PATCH] c++: constinit on pointer to function [PR104066]

[dcl.constinit]: "The constinit specifier shall be applied only to a declaration of a variable with static or thread storage duration." Thus, this ought to be OK: constinit void (*p)() = nullptr; but the error message I introduced when implementing constinit was not looking at funcdecl_p, so t

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

Am I wrong to worry that this will increase dynamic instruction count when used in a loop? The obvious code is more efficient when the constant loads can be hoisted out of a loop. Or does the cost model account for this somehow? On Sun, Nov 13, 2022 at 12:50 PM Philipp Tomsich wrote: > > Use Z

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, Nov 17, 2022 at 10:25 AM Andrew Pinski wrote: > > On Sun, Nov 13, 2022 at 12:51 PM Philipp Tomsich > wrote: > > > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." > > that can be expressed as bexti + bexti + andn. > > Can't you also handle if ((a & twobits) =

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Sun, Nov 13, 2022 at 12:51 PM Philipp Tomsich wrote: > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." > that can be expressed as bexti + bexti + andn. Can't you also handle if ((a & twobits) == 0) case doing a similar thing. That is: two bexti + and and then com

[COMMITTED] Fix PR 107734: valgrind errors with sbitmap in match.pd

From: Andrew Pinski sbitmap is a simple bitmap and the memory allocated is not cleared on creation; you have to clear it or set it to all ones before using it. This is unlike bitmap which is a sparse bitmap and the entries are cleared as created. The code added in r13-4044-gdc95e1e9702f2f missed

[COMMITTED] [PR tree-optimization/107732] [range-ops] Handle attempt to abs() negatives.

The threader is creating a scenario where we are trying to solve: [NEGATIVES] = abs(x) While solving this we have an intermediate value of UNDEFINED because we have no positive numbers. But then we try to union the negative pair to the final result by querying the bounds. Since neither

Re: [PATCH] maintainer-scripts/gcc_release: compress xz in parallel

> On 8 Nov 2022, at 07:14, Sam James wrote: > > 1. This should speed up decompression for folks, as parallel xz > creates a different archive which can be decompressed in parallel. > > Note that this different method is enabled by default in a new > xz release coming shortly anyway (>= 5

Re: [PATCH] [range-ops] Implement sqrt.

This may be DCE. DOM uses ranger through simplify_using_ranges::fold_cond() to fold the following conditional to false, because we know x_185 is a NAN: x_185 = __builtin_sqrtf (-1.0e+0); if (x_185 ord x_185) I believe we can do that, because there are no user observable effects. But DCE remove

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

Wilco Dijkstra writes: > Hi Richard, > >> Can you go into more detail about: >> >>Use :option:`-mdirect-extern-access` either in shared libraries or in >>executables, but not in both. Protected symbols used both in a shared >>library and executable may cause linker errors or fail to w

Re: [PATCH] [range-ops] Implement sqrt.

On 11/17/22 17:40, Aldy Hernandez wrote: To go along with whatever magic we're gonna tack along to the range-ops sqrt implementation, here is another revision addressing the VARYING issue you pointed out. A few things... Instead of going through trees, I decided to call do_mpfr_arg1 directly

PING^5 [PATCH] testsuite: Verify that module-mapper is available

Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604895.html Ok for trunk? Kind regards, Torbjörn On 2022-11-02 19:13, Torbjorn SVENSSON wrote: Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602844.html Ok for trunk? Kind regards, Torbjörn On 2022-10-25

[PATCH 13/35] arm: further fix overloading of MVE vaddq[_m]_n intrinsic

From: Stam Markianos-Wright It was observed that in tests `vaddq_m_n_[s/u][8/16/32].c`, the _Generic resolution would fall back to the `__ARM_undef` failure state. This is a regression since `dc39db873670bea8d8e655444387ceaa53a01a79` and `6bd4ce64eb48a72eca300cb52773e6101d646004`, but it previou

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On Thu, 17 Nov 2022 at 17:39, Jeff Law wrote: > > > On 11/17/22 08:12, Philipp Tomsich wrote: > > > > This serves as an assertion only, as that case is non-sensical and > > will be optimized away by earlier passes (as "a & C == T" with C and T > > sharing no bits will always be false). > > IFAIK t

[PATCH 15/35] arm: Explicitly specify other float types for _Generic overloading [PR107515]

From: Stam Markianos-Wright This patch adds explicit references to other float types to __ARM_mve_typeid in arm_mve.h. Resolves PR 107515: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107515 gcc/ChangeLog: PR 107515 * config/arm/arm_mve.h (__ARM_mve_typeid): Add float types. ---

PING^2 [PATCH] cpp/remap: Only override if string matched

Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604898.html Ok for trunk? Kind regards, Torbjörn On 2022-11-02 19:21, Torbjorn SVENSSON wrote: Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604062.html Ok for trunk? Kind regards, Torbjörn On 2022-10-20

Re: [PATCH] AArch64: Add support for -mdirect-extern-access

Hi Richard, > Can you go into more detail about: > >    Use :option:`-mdirect-extern-access` either in shared libraries or in >    executables, but not in both.  Protected symbols used both in a shared >    library and executable may cause linker errors or fail to work correctly > > If this is LLV

PING^2 [PATCH] testsuite: Windows paths use \ and not /

Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604896.html Ok for trunk? Kind regards, Torbjörn On 2022-11-02 19:16, Torbjorn SVENSSON wrote: Hi, Ping, https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604312.html Ok for trunk? Kind regards, Torbjörn On 2022-10-25

[PATCH 01/35] arm: improve vcreateq* tests

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise.

Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs

On 11/17/22 08:12, Philipp Tomsich wrote: This serves as an assertion only, as that case is non-sensical and will be optimized away by earlier passes (as "a & C == T" with C and T sharing no bits will always be false). IFAIK the preceding transforms should always clean such a check up, but we

Re: [PATCH] [range-ops] Implement sqrt.

To go along with whatever magic we're gonna tack along to the range-ops sqrt implementation, here is another revision addressing the VARYING issue you pointed out. A few things... Instead of going through trees, I decided to call do_mpfr_arg1 directly. Let's not go the wide int <-> tree rat hole

[PATCH 17/35] arm: improve tests and fix vadd*

gcc/ChangeLog: * config/arm/mve.md (mve_vaddlvq_p_v4si) (mve_vaddq_n_, mve_vaddvaq_) (mve_vaddlvaq_v4si, mve_vaddq_n_f) (mve_vaddlvaq_p_v4si, mve_vaddq, mve_vaddq_f): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vaddlvaq_p_

[PATCH 09/35] arm: improve tests for vmax*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise.

[PATCH 29/35] arm: improve tests for vqdmul*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c: L

[PATCH 32/35] arm: improve tests for vqsubq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c: * gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c: * gcc.target/arm/mve/intrinsics/vq

[PATCH 21/35] arm: improve tests for vhaddq_m*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c: Likewise

[PATCH 26/35] arm: improve tests for vmlasq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c: Likewise

[PATCH 34/35] arm: improve tests for vrshlq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c: Likewis

[PATCH 18/35] arm: improve tests for vmulq*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmulq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmulq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmulq_m_f32.c: Likewise. * gcc

[PATCH 25/35] arm: improve tests and fix vmlaldavaxq*

gcc/ChangeLog: * config/arm/mve.md (mve_vmlaldavaq_) (mve_vmlaldavaxq_s, mve_vmlaldavaxq_p_): Fix spacing vs tabs. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s3

[PATCH 28/35] arm: improve tests for vqdmlahq_m*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c: Li

[PATCH 22/35] arm: improve tests for vhsubq_m*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c: Likewise

[PATCH 08/35] arm: improve tests for vmin*

gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise.

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