Re: [PATCH] enable -fweb and -frename-registers at -O3 for rs6000

Segher Boessenkool writes: > Hi! > > On Fri, Dec 20, 2019 at 02:34:05PM +0800, Jiufu Guo wrote: >> Previously, limited unrolling was enabled at O2 for powerpc in r278034. At >> that >> time, -fweb and -frename-registers were not enabled together with >> -funroll-loops >> even for -O3. After t

Re: undefine OFFSET in testsuite/gcc.dg/vect/tree-vect.h

> On 21 Dec 2019, at 02:39, Mike Stump wrote: > > On Dec 20, 2019, at 10:11 AM, Olivier Hainque wrote: >> >> The attached patch is a proposal for a basic solution >> to an issue which might be an improper thing done by a >> system header on VxWorks, but which is a big pain to fix >> at this l

Re: [patch] Let libstdc++ know that VxWorks has_nanosleep

Hi Jonathan, > On 19 Dec 2019, at 12:13, Jonathan Wakely wrote: > > > Is there a way to detect that more reliably? Should we replicate the > test used later in the file, to detect whether the timers are really > enabled for VxWorks? > > AC_MSG_CHECKING([for nanosleep]) ... > You're the po

Re: [PATCH] Add OpenACC 2.6 `acc_get_property' support

Hi Thomas, >> Is it ok to commit the patch to trunk? > > OK, thanks. And then some follow-up/clean-up next year, also including > some of the open questions that I've snipped off here. Right, thanks for the review! I have committed the patch as r279710 with a minor change: I have disabled the n

Re: [PATCH] V11 patch #4 of 15, Update 'Q' constraint documentation.

On Fri, Dec 20, 2019 at 06:49:30PM -0500, Michael Meissner wrote: > In doing V11 patch #3, I noticed that the documentation for the 'Q' was > misleading. It originally was used just for lswi/stswi, which can access up to the first 32 bytes of storage pointed to by the register. But yes, the curre

Re: [PATCH] V11 patch #3 of 15, Use 'Q' constraint for variable vector extract from memory

Hi! On Fri, Dec 20, 2019 at 06:47:28PM -0500, Michael Meissner wrote: > Then I realized that eventaully we will want to generate an X-FORM (register + > register) address, and it was just simpler to use the 'Q' constraint, and have > the register allocator put the address into a register. Yep, go

Re: [PATCH] V11 patch #2 of 15, Use prefixed load for vector extract with large offset

Hi! On Fri, Dec 20, 2019 at 06:38:32PM -0500, Michael Meissner wrote: > --- gcc/config/rs6000/rs6000.c(revision 279553) > +++ gcc/config/rs6000/rs6000.c(working copy) > @@ -6792,9 +6792,17 @@ rs6000_adjust_vec_address (rtx scalar_re > HOST_WIDE_INT offset = INTVAL (op1) + I

[patch, fortran] Updated fix PR 92961, ICE on division by zero error in array bounds

Hello world, here is an update for the fix for PR 92961, which also takes care of the second test case in the PR (included in the first one). The patch itself should be clear enough - make sure that there is a MATCH_ERROR on matching an array spec which contains 0/(0). Rather than pass around in

Re: [PATCH] libstdcxx: Update ctype_base.h from NetBSD upstream

On 22.12.2019 00:36, Gerald Pfeifer wrote: > Hi Matthew, > > On Mon, 4 Feb 2019, Matthew Bauer wrote: >> The ctype_base.h file in libstdc++-v3 is out of date for NetBSD. They >> have changed their ctype.h definition. It was updated in their intree >> libstdc++-v3 but not in the GCC one. My underst

Re: [PATCH] V11 patch #1 of 15, Fix bug in vec_extract

Hi! On Fri, Dec 20, 2019 at 06:24:57PM -0500, Michael Meissner wrote: > This patch fixes the bug pointed out in the V10 patch review that the code > modified an input argument to vector extract with a variable element number. Great, thanks. > With this patch applied, the compiler will signal an