On Thu, Dec 20, 2018 at 08:42:05AM +0100, Uros Bizjak wrote:
> > If one vcond argument is all ones (non-bool) vector and another one is all
> > zeros, we can use for AVX512{DQ,BW} (sometimes + VL) the vpmovm2? insns.
> > While if op_true is all ones and op_false, we emit large code that the
> > com
On Thu, Dec 20, 2018 at 12:20 AM Jakub Jelinek wrote:
>
> Hi!
>
> If one vcond argument is all ones (non-bool) vector and another one is all
> zeros, we can use for AVX512{DQ,BW} (sometimes + VL) the vpmovm2? insns.
> While if op_true is all ones and op_false, we emit large code that the
> combine
Hi
I eventually find out what was the problem with the
std::move_if_noexcept within associative containers.
The std::pair move default constructor might not move both first
and second member. If any is not moveable it will just copy it. And then
the noexcept qualification of the copy
Hi Ramana,
Please ignore the patch in the previous email attachment (the
ChangeLog has deleted in this patch..) I have already communicated with Shao
Kun, he has fixed the problem of the previous patch. So I resubmitted the
tsv110 pipeline patch, please review.
The patch as
This fixes the bug id, 71176 to use the proper known
code print formatter type, %lu for size_t rather than
%d which is considered best pratice for print statements.
Signed-off-by: Nicholas Krause
---
fixincludes/fixincl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/fi
Hi Ramana,
I have already communicated with Shao Kun, he has fixed the problem
of the previous patch. So I resubmitted the tsv 110 pipeline patch, please
review.
The patch as follows :
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
old mode 100644
new mode 100755
index b1eed3b..5
On Wed, 2018-12-19 at 20:00 +0100, Thomas Schwinge wrote:
> Hi David!
>
> I will admit that I don't have researched ;-/ what this is actually
> all
> about, and how it's implemented, but...
>
> On Mon, 5 Nov 2018 15:31:08 -0500, David Malcolm m> wrote:
> > The C++ frontend gained various locati
On Wed, 2018-12-19 at 17:27 -0600, Aaron Sawdey wrote:
> Assuming you applied this as svn 267273, it causes bootstrap failure
> on powerpc64le-unknown-linux-gnu. Stage 2 fails with multiple
> instances
> of this error:
>
> ../../trunk-base/gcc/c-family/c-pragma.c: In function ‘void
> handle_pragma
Hi Richard,
On 2018/12/19 18:12, Richard Earnshaw (lists) wrote:
> On 19/12/2018 03:11, Shaokun Zhang wrote:
>> For HiSilicon's tsv110 cpu core, it supports some v8_4A features, but
>> some mandatory features are not implemented. Revert to ARMv8.2 that
>> all mandatory features are supported.
>>
>
This patch is wrong for multiple reasons (the %d you're changing is for an
int argument, so is correct as-is, and %lu is not portable for size_t, so
since we may not be able to assume C99 %zu on the host you'd need to cast
the ttl_data_size argument explicitly to unsigned long int to use %lu for
Christophe,
Thanks again for the report. This was quite an adventure to figure
out ;-) See below.
[PR88146] avoid diagnostics diffs if cdtor_returns_this
Diagnostics for testsuite/g++.dg/cpp0x/inh-ctor32.C varied across
platforms. Specifically, on ARM, the diagnostics within the subtest
deri
This fixes the bug id, 71176 to use the proper known
code print formatter type, %lu for size_t rather than
%d which is considered best pratice for print statements.
Signed-off-by: Nicholas Krause
---
fixincludes/fixincl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fixinc
Assuming you applied this as svn 267273, it causes bootstrap failure
on powerpc64le-unknown-linux-gnu. Stage 2 fails with multiple instances
of this error:
../../trunk-base/gcc/c-family/c-pragma.c: In function ‘void
handle_pragma_scalar_storage_order(cpp_reader*)’:
../../trunk-base/gcc/c-family/c
Hi!
If one vcond argument is all ones (non-bool) vector and another one is all
zeros, we can use for AVX512{DQ,BW} (sometimes + VL) the vpmovm2? insns.
While if op_true is all ones and op_false, we emit large code that the
combiner often optimizes to that vpmovm2?, if the arguments are swapped,
we
On Tue, Dec 18, 2018 at 10:27:56PM -0500, Jason Merrill wrote:
> On 12/18/18 6:19 PM, Jakub Jelinek wrote:
> > On Tue, Dec 18, 2018 at 05:40:03PM -0500, Jason Merrill wrote:
> > > On 12/18/18 3:45 PM, Jakub Jelinek wrote:
> > > > The following testcase FAILs, because parsing creates a TREE_CONSTANT
Hi!
On Tue, Dec 18, 2018 at 05:29:41PM -0500, Jason Merrill wrote:
> So, we end up calling ggc_collect because we're processing a member function
> in a context where defining a type is not allowed. One solution would be to
> not do late parsing of members in such a context.
>
> We don't have th
On Wed, 2018-12-19 at 23:57 +0100, Jakub Jelinek wrote:
> On Wed, Dec 19, 2018 at 10:10:19PM +, Steve Ellcey wrote:
> > @@ -199,6 +201,7 @@ int B::f25<7> (int a, int *b, int c)
> > // { dg-final { scan-assembler-times
> > "_ZGVdN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-*
> > x86
On Wed, Dec 19, 2018 at 10:10:19PM +, Steve Ellcey wrote:
> @@ -199,6 +201,7 @@ int B::f25<7> (int a, int *b, int c)
> // { dg-final { scan-assembler-times
> "_ZGVdN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* }
> } } }
> // { dg-final { scan-assembler-times
> "_ZGV
On Sun, Dec 16, 2018 at 09:42:25AM -0800, Steve Kargl wrote:
> The following patch removes the ICE reported in PR fortran/87992,
> and restores the behavior observed with gfortran 7 and 8 (ie,
> code compiles).
>
> The PR marks the code with ice-on-invalid-code. I don't use
> CLASS in any of code
Here is an updated version of the GCC patch to enable SIMD functions on
Aarch64. There are a number of changes from the last patch.
I reduced the shared code changes, there is still one change in shared code
(omp-simd-clone.c) to call targetm.simd_clone.adjust from expand_simd_clones
but it now u
Hi Jakub!
On Wed, 19 Dec 2018 15:18:12 +0100, Jakub Jelinek wrote:
> On Wed, Dec 19, 2018 at 03:03:42PM +0100, Jakub Jelinek wrote:
> > On Wed, Dec 19, 2018 at 02:59:54PM +0100, Thomas Schwinge wrote:
> > > Right. For OpenACC, there's no "device" clause, so we only ever passed
> > > in "GOMP_DEV
On Tue, 18 Dec 2018 at 16:51, Jonathan Wakely wrote:
>
> The resolution for LWG 2936 defines the comparison more precisely, which
> this patch implements. The patch also defines comparisons with strings
> to work without constructing a temporary path object (so avoids any
> memory allocations).
>
The clause makes any device code use the local memory address for each
of the variables specified unless the given variable is already present
on the current device.
2018-12-19 Julian Brown
Maciej W. Rozycki
gcc/
* omp-low.c (lower_omp_target): Support GOMP_MAP_
Hi,
Jakub Jelinek wrote:
> On Wed, Dec 19, 2018 at 07:53:48PM +, Uecker, Martin wrote:
>> What do you think about making the trampoline a single call
>> instruction and have a large memory region which is the same
>> page mapped many times?
This sounds like a good idea, but given a function d
Hello!
Attached patch uses equivalent instruction, where HImode variant is
also enabled for plain AVX512F isa.
2018-12-19 Uros Bizjak
* config/i386/i386.md (SWI1248_AVX512BWDQ_64): Rename from
SWI1248_AVX512BWDQ2_64. Unconditionally enable HImode.
(*cmp_ccz_1): Emit kortest inste
Prompted by Jon's observation in 52869, I noticed that we don't treat
a noexcept-specifier as a complete-class context of a class ([class.mem]/6).
As with member function bodies, default arguments, and NSDMIs, names used in
a noexcept-specifier of a member-function can be declared later in the clas
* doc/xml/manual/abi.xml: Add missing word.
Committed to trunk.
commit c8af51b0a2caa1e8a65d5aea28e82cde306f487e
Author: Jonathan Wakely
Date: Wed Dec 19 20:15:59 2018 +
Fix grammar in libstdc++ ABI history documentation
* doc/xml/manual/abi.xml: Add missing
On Wed, Dec 19, 2018 at 07:53:48PM +, Uecker, Martin wrote:
> What do you think about making the trampoline a single call
> instruction and have a large memory region which is the same
> page mapped many times?
>
>
> call trampoline_handler
> call trampoline_handler
> call trampoline_handler
Am Dienstag, den 18.12.2018, 17:42 +0100 schrieb Jakub Jelinek:
> On Tue, Dec 18, 2018 at 04:33:48PM +, Uecker, Martin wrote:
> > > Yes, something like this. If the trampolines are pre-allocated, this could
> > > even avoid the need to clear the cache on archs where this is needed.
> >
> > And
Because of POWER9 dd2.1 issues with certain unaligned vsx instructions
to cache inhibited memory, here is a patch that keeps memmove (and memcpy)
inline expansion from doing unaligned vector or using vector load/store
other than lvx/stvx. More description of the issue is here:
https://patchwork.oz
Am Sonntag, den 16.12.2018, 09:13 -0700 schrieb Jeff Law:
> It's also important to remember that not every target which uses
> function descriptors uses the LSB. On some targets the LSB may switch
> between modes (arm vs thumb for example). So on those targets the use
> of descriptors may imply
Hi David!
I will admit that I don't have researched ;-/ what this is actually all
about, and how it's implemented, but...
On Mon, 5 Nov 2018 15:31:08 -0500, David Malcolm wrote:
> The C++ frontend gained various location wrapper nodes in r256448 (GCC 8).
> That patch:
> https://gcc.gnu.org/ml
On Wed, Dec 19, 2018 at 04:47:51PM -0200, Alexandre Oliva wrote:
> On Dec 19, 2018, Christophe Lyon wrote:
>
> > The new test inh-ctor32.C fails on arm:
> > FAIL:g++.dg/cpp0x/inh-ctor32.C -std=c++14 (test for warnings, line
> > 208)
> > FAIL:g++.dg/cpp0x/inh-ctor32.C -std=c++17 (test
On Dec 19, 2018, Christophe Lyon wrote:
> The new test inh-ctor32.C fails on arm:
> FAIL:g++.dg/cpp0x/inh-ctor32.C -std=c++14 (test for warnings, line 208)
> FAIL:g++.dg/cpp0x/inh-ctor32.C -std=c++17 (test for warnings, line 208)
Thanks, sorry about the breakage, I'm looking into it.
On Wed, Dec 19, 2018 at 06:28:29PM +0100, Richard Biener wrote:
> On Wed, Dec 19, 2018 at 4:41 PM Andi Kleen wrote:
> >
> > > > We can combine the two together, increasing iteration count and
> > > > decreasing perf count at the same time. What count would you suggest
> > > > from your experience
On Wed, Dec 19, 2018 at 6:51 AM H.J. Lu wrote:
>
> On Tue, Dec 18, 2018 at 2:14 PM Jason Merrill wrote:
> >
> > On 12/18/18 4:12 PM, H.J. Lu wrote:
> > > On Tue, Dec 18, 2018 at 12:36 PM Jason Merrill wrote:
> > >>
> > >> On 12/18/18 9:10 AM, H.J. Lu wrote:
> > >>> + switch (TREE_CODE (rhs))
>
On Wed, Dec 19, 2018 at 4:41 PM Andi Kleen wrote:
>
> > > We can combine the two together, increasing iteration count and
> > > decreasing perf count at the same time. What count would you suggest
> > > from your experience?
> >
> > Can we instead for the tests where we want to test profile use/m
[ was: Re: [nvptx] vector length patch series ]
On 14-12-18 20:58, Tom de Vries wrote:
> 0005-nvptx-update-openacc-dim-macros.patch
Factored out this patch.
Committed.
Thanks,
- Tom
[nvptx] Add PTX_CTA_SIZE
2018-12-17 Tom de Vries
* config/nvptx/nvptx.c (PTX_CTA_SIZE): Define.
---
gcc/co
On Wed, Dec 19, 2018 at 12:08:35PM +0800, Bin.Cheng wrote:
> On Wed, Dec 19, 2018 at 12:00 PM Andi Kleen wrote:
> >
> > On Wed, Dec 19, 2018 at 10:01:15AM +0800, Bin.Cheng wrote:
> > > On Tue, Dec 18, 2018 at 7:15 PM Bin.Cheng wrote:
> > > >
> > > > On Sun, Dec 16, 2018 at 9:11 AM Andi Kleen wro
Hi all,
Since r265398 (combine: Do not combine moves from hard registers), the bfxil
scan in gcc.target/aarch64/combine_bfxil.c has been failing.
FAIL: gcc.target/aarch64/combine_bfxil.c scan-assembler-times bfxil\\t 13
This is because bfi was generated for the combine_* functions in the
above
On Fri, Dec 14, 2018 at 10:09:03AM -0600, Sudakshina Das wrote:
> I have updated the patch according to our discussions offline.
> The md pattern is now split into 4 patterns and i have added a new
> test for the setjmp case along with some comments where missing.
This is OK for trunk.
Thanks,
> > We can combine the two together, increasing iteration count and
> > decreasing perf count at the same time. What count would you suggest
> > from your experience?
>
> Can we instead for the tests where we want to test profile use/merge
> elide the profiling step and supply the "raw" data in a
On Tue, 2018-12-18 at 15:40 -0500, Jason Merrill wrote:
> On 12/18/18 4:22 PM, David Malcolm wrote:
> > On Mon, 2018-12-17 at 18:30 -0500, David Malcolm wrote:
> > > On Mon, 2018-12-17 at 14:33 -0500, Jason Merrill wrote:
> > > > On 12/14/18 7:17 PM, David Malcolm wrote:
> > > > > + /* Since d
[ was: Fwd: [openacc, committed] Add oacc_get_default_dim ]
On 19-12-18 16:27, Tom de Vries wrote:
> [ Adding gcc-patches ]
>
> Forwarded Message
> Subject: [openacc, committed] Add oacc_get_default_dim
> Date: Wed, 19 Dec 2018 16:24:25 +0100
> From: Tom de Vries
> To: Thomas S
[ Adding gcc-patches ]
Forwarded Message
Subject: [openacc, committed] Add oacc_get_default_dim
Date: Wed, 19 Dec 2018 16:24:25 +0100
From: Tom de Vries
To: Thomas Schwinge
[ was: Re: [nvptx] vector length patch series -- openacc parts ]
On 19-12-18 11:40, Thomas Schwinge wro
On 14/12/2018 21:09, Thomas Preudhomme wrote:
> Hi Richard,
>
> None, is there any? All the one I could find in the big switch
> selecting tm_files and tmake_files in gcc/config.gcc are including
> arm/elf.h. I tried to build for arm-wince-pe but got: "Configuration
> arm-wince-pe not supported".
Good catch.
Committed patch in attachment. Best regards,
Thomas
On Wed, 19 Dec 2018 at 14:13, Richard Earnshaw (lists)
wrote:
>
> On 14/12/2018 21:15, Thomas Preudhomme wrote:
> > Hi Richard,
> >
> > Thanks for catching the problem with this approach. Hopefully this
> > version should solve the
On Tue, Dec 18, 2018 at 7:19 PM Sandra Loosemore
wrote:
>
> On 12/18/18 2:12 PM, H.J. Lu wrote:
> >
> > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> > index ac2ee59d92c..47f2fc3f518 100644
> > --- a/gcc/doc/invoke.texi
> > +++ b/gcc/doc/invoke.texi
> > @@ -358,6 +358,7 @@ Objective-C a
On Tue, Dec 18, 2018 at 2:14 PM Jason Merrill wrote:
>
> On 12/18/18 4:12 PM, H.J. Lu wrote:
> > On Tue, Dec 18, 2018 at 12:36 PM Jason Merrill wrote:
> >>
> >> On 12/18/18 9:10 AM, H.J. Lu wrote:
> >>> + switch (TREE_CODE (rhs))
> >>> +{
> >>> +case ADDR_EXPR:
> >>> + base = TREE_O
On Sat, 15 Dec 2018 at 23:11, Jason Merrill wrote:
>
> On Fri, Dec 14, 2018 at 6:05 PM Alexandre Oliva wrote:
> >
> > On Dec 14, 2018, Jason Merrill wrote:
> >
> > > Let's move the initialization of "fields" inside the 'then' block here
> > > with the initialization of "cvquals", rather than cle
Hi,
Add pr85381*.c test-cases that are already passing without the fix for PR85381.
Build and reg-tested on x86_64 with nvptx accelerator.
Committed to trunk.
Thanks,
- Tom
[nvptx] Commit passing pr85381-*.c test-cases
2018-12-19 Tom de Vries
* testsuite/libgomp.oacc-c-c++-common/
Hi,
The goacc.exp test-cases nvptx-merged-loop.c and nvptx-sese-1.c are failing
during linking due to missing libgomp.spec.
Move them to the libgomp testsuite.
Build and reg-tested on x86_64 with nvptx accelerator.
Committed to trunk.
Thanks,
- Tom
[nvptx, libgomp] Move rtl-dump test-cases to
Hi,
This patch adds scan-offload-rtl-dump, similar to scan-offload-tree-dump.
Build and reg-tested on x86_64 with nvptx accelerator.
Pre-approved here ( https://gcc.gnu.org/ml/gcc-patches/2018-05/msg01089.html ).
Committed to trunk.
Thanks,
- Tom
[testsuite] Add scan-offload-rtl-dump
2018-03
On 14/12/2018 21:15, Thomas Preudhomme wrote:
> Hi Richard,
>
> Thanks for catching the problem with this approach. Hopefully this
> version should solve the real problem:
>
>
> FP instructions are only enabled for TARGET_32BIT and TARGET_HARD_FLOAT
> but GCC only gives an error when TARGET_HARD
On Wed, Dec 19, 2018 at 01:49:41PM +, Segher Boessenkool wrote:
> This pattern optimises a scalar extract from a vector loaded from
> memory to be just a scalar load from memory. But to do a 64-bit
> integer load you need 64-bit integer registers, which needs
> TARGET_POWERPC64.
>
> This fixe
This pattern optimises a scalar extract from a vector loaded from
memory to be just a scalar load from memory. But to do a 64-bit
integer load you need 64-bit integer registers, which needs
TARGET_POWERPC64.
This fixes it. Tested on powerpc64-linux {-m32,-m64}; committing to trunk.
Segher
20
Richard,
I'm happy to change the name of the helper to code_helper_for_stmt, the new
patch and changelog are included. Regarding the reductions being fold_left, the
FMINNM/FMINMV instructions are defined in such a way that this is not necessary
(it wouldn't work with FMIN/FMINV).
Alejandro
On Wed, Dec 19, 2018 at 10:33 AM Alejandro Martinez Vicente
wrote:
>
> Hi all,
>
> Loops that use the fmin/fmax builtins can be vectorized even without
> -ffast-math using SVE's FMINNM/FMAXNM instructions. This is an example:
>
> double
> f (double *x, int n)
> {
> double res = 100.0;
> for (i
With the patch for PR85275 I throttled loop-header copying too much.
The following reverts that patch and instead adds heuristics to
should_duplicate_loop_header_p as to _not_ copy exit tests that
are based on non-IV/invariant tests. Since CH runs before any
LIM we have to keep track of what is
On Dec 18, 2018, Jeff Law wrote:
>> Although such overflow tests could be uniformly simplified to compares
>> against a constant, the original code would only perform such
>> simplifications when the test could be resolved to an equality test
>> against zero. I've thus avoided introducing compar
[ was: Re: [nvptx] vector length patch series ]
On 14-12-18 20:58, Tom de Vries wrote:
> 0014-nvptx-Use-MAX-MIN-ROUND_UP-macros.patch
Committed.
Thanks,
- Tom
[nvptx] Use MAX, MIN, ROUND_UP macros
Use MAX, MIN, and ROUND_UP macros to simplify code.
Build and reg-tested on x86_64 with nvptx acc
[ was: Re: [nvptx] vector length patch series ]
On 14-12-18 20:58, Tom de Vries wrote:
> 0008-nvptx-make-nvptx-state-propagation-function-names-mo.patch
Committed.
Thanks,
- Tom
[nvptx] Make nvptx state propagation function names more generic
Rename state propagation functions to avoid worker/v
[ was: Re: [nvptx] vector length patch series ]
On 14-12-18 20:58, Tom de Vries wrote:
> 0006-nvptx-Rename-worker_bcast-variables-oacc_bcast.patch
Committed.
Thanks,
- Tom
[nvptx] Rename worker_bcast variables to oacc_bcast
Rename worker_bcast variables to oacc_bcast, avoiding worker terminolog
[ was: Re: [nvptx] vector length patch series ]
On 14-12-18 20:58, Tom de Vries wrote:
> 0011-nvptx-Add-thread-count-parm-to-bar.sync.patch
Factored out this patch, committed.
Thanks,
- Tom
[nvptx] Generalize bar.sync instruction
Allow the logical barrier operand of nvptx_barsync to be a regist
[ was: Re: [nvptx] vector length patch series ]
On 14-12-18 20:58, Tom de Vries wrote:
> 0010-nvptx-only-use-one-bar.sync-barriers-in-OpenACC-offl.patch
Committed.
Thanks,
- Tom
[nvptx] Only use one logical barrier resource
For openacc loops, we generate this style of code:
...
@%r41
[ was: Re: [nvptx] vector length patch series ]
On 14-12-18 20:58, Tom de Vries wrote:
> 0013-nvptx-Use-TARGET_SET_CURRENT_FUNCTION.patch
Committed.
Thanks,
- Tom
[nvptx] Use TARGET_SET_CURRENT_FUNCTION
Implement TARGET_SET_CURRENT_FUNCTION for nvptx. This gives us a place to
add initializatio
Hi!
On Wed, Dec 12, 2018 at 11:30:37PM +0100, Jakub Jelinek wrote:
> 2018-12-12 Jakub Jelinek
>
> PR c++/86524
> PR c++/88446
> * cp-tree.h (fold_non_dependent_expr): Add manifestly_const_eval
> argument.
> * constexpr.c (cxx_eval_builtin_function_call): Evaluate
On 19/12/2018 03:11, Shaokun Zhang wrote:
> For HiSilicon's tsv110 cpu core, it supports some v8_4A features, but
> some mandatory features are not implemented. Revert to ARMv8.2 that
> all mandatory features are supported.
>
Thanks, I've put this in.
I've modified the ChangeLog entry slightly -
I've applied the following three patches to aarch64/sve-acle-branch.
The first just fixes some bugs I noticed while testing the current branch.
The other two try to tidy up the instruction generation code so that we
aren't passing so many values around, and so that it's easier to separate
"number o
On Wed, Dec 19, 2018 at 5:08 AM Bin.Cheng wrote:
>
> On Wed, Dec 19, 2018 at 12:00 PM Andi Kleen wrote:
> >
> > On Wed, Dec 19, 2018 at 10:01:15AM +0800, Bin.Cheng wrote:
> > > On Tue, Dec 18, 2018 at 7:15 PM Bin.Cheng wrote:
> > > >
> > > > On Sun, Dec 16, 2018 at 9:11 AM Andi Kleen wrote:
> >
Hi all,
Loops that use the fmin/fmax builtins can be vectorized even without
-ffast-math using SVE's FMINNM/FMAXNM instructions. This is an example:
double
f (double *x, int n)
{
double res = 100.0;
for (int i = 0; i < n; ++i)
res = __builtin_fmin (res, x[i]);
return res;
}
Before th
On Wed, Dec 19, 2018 at 08:40:13AM +0200, Dimitar Dimitrov wrote:
> On Mon, Dec 17 2018 20:15:02 EET Bernd Edlinger wrote:
> > out of curiosity I looked at the clobber statement in
> > gdb/nat/linux-ptrace.c:
> >
> >asm volatile ("pushq %0;"
> > ".globl linux_p
Hi!
On Tue, Dec 18, 2018 at 10:23:05PM -0600, Paul Clarke wrote:
> This patch is the analog to r266868-r266870, but for SSSE3.
> The SSSE3 tests had been inadvertently made to PASS without actually running
> the test code. Actually running the code turned up some previously undetected
> issues.
>
On Tue, Dec 18, 2018 at 10:39:27AM +1030, Alan Modra wrote:
> On Mon, Dec 17, 2018 at 11:05:57AM -0600, Segher Boessenkool wrote:
> > Hi!
> >
> > On Mon, Dec 17, 2018 at 10:40:01AM +1030, Alan Modra wrote:
> > > Since I broke powerpc*-freebsd and the other non-linux powerpc
> > > targets, I guess
On Tue, Dec 18, 2018 at 9:53 PM Jakub Jelinek wrote:
>
> Hi!
>
> As mentioned in the PR, there is a VEX encoded vpclmulqdq instruction
> with ymm arguments that needs VPCLMULQDQ ISA, and then EVEX encoded
> vpclmulqdq with zmm arguments that needs VPCLMULQDQ + AVX512F ISAs and
> vpclmulqdq with xm
On Dec 14, 2018, Jason Merrill wrote:
> Yes, like that, thanks. It might be a bit of an optimization to skip
> this when t == TREE_TYPE (parm). OK either way.
Thanks, I've put the suggested optimization in.
Here's what I'm about to install.
[PR87012] canonicalize ref type for tmpl arg
When
76 matches
Mail list logo
