On January 30, 2017 7:10:07 PM GMT+01:00, Jakub Jelinek
wrote:
>Hi!
>
>This is yet another occurrence of the bug that we drop lhs on noreturn
>calls even when it actually should not be dropped (if it has
>addressable
>type or if it is a variable length type).
>
>Bootstrapped/regtested on x86_64-l
On Tue, Jan 31, 2017 at 8:48 AM Ville Voutilainen
wrote:
>
> On 31 January 2017 at 00:41, Ville Voutilainen
> wrote:
>
> I don't actually need to constrain it, I could just add a guide like
>
> template optional(optional<_Tp>) -> optional<_Tp>;
>
> However, I'm not convinced I need to. The prefe
This patch fixes PR target/78597 on PowerPC. The basic problem is conversion
between unsigned int and _Float128 fails for 0x8000. Both power{7,8} using
simulated IEEE 128-bit floating point and power9 using hardware IEEE 128-bit
failed in the same test.
I cut down the patches I had developed
On Fri, Jan 20, 2017 at 10:41 PM, Richard Henderson wrote:
> On 01/11/2017 06:30 PM, Palmer Dabbelt wrote:
>>
>> +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
>> + "A floating-point register (if available).")
>> +
>
>
> I know this is the Traditional Way, but I do wonde
Thanks for the feedback, Richard. We've addressed the bulk of it, and
added some explanatory comments in the few cases where the current
implementation makes sense, but for less than obvious reasons. We
will submit a v2 patch set reflecting these changes in the next couple
of days.
A few respons
On 31 January 2017 at 00:41, Ville Voutilainen
wrote:
> On 31 January 2017 at 00:06, Tim Song wrote:
>> On Mon, Jan 30, 2017 at 9:36 PM Jonathan Wakely wrote:
>>>
>>> On 30/01/17 13:28 +, Jonathan Wakely wrote:
>>> >On 30/01/17 13:47 +0200, Ville Voutilainen wrote:
>>> >>Tested on Linux-x64.
Hi Jakub, Mike,
On Mon, Jan 30, 2017 at 10:27:15PM +0100, Jakub Jelinek wrote:
> Accoring to make mddump generated tmp-mddump.md, on powerpc the only pattern
> with unsigned_fix:DI where the inner operand is SF or DFmode is the
> *fixuns_truncdi2_fctiduz.
It seems like vsx_fixuns_trunc2 (in vsx.m
So I see the introduction of many
if (const OP object) expressions
Can you please fix those as an independent patch after #4 and #5 are
installed on the trunk? Consider that patch pre-approved, but please
post it here for the historical record.
I think a regexp of paren followed by a constant
On 31 January 2017 at 00:06, Tim Song wrote:
> On Mon, Jan 30, 2017 at 9:36 PM Jonathan Wakely wrote:
>>
>> On 30/01/17 13:28 +, Jonathan Wakely wrote:
>> >On 30/01/17 13:47 +0200, Ville Voutilainen wrote:
>> >>Tested on Linux-x64.
>> >
>> >OK, thanks.
>>
>> To be clear: this isn't approved b
After the patch of 2016-11-03, gen_type_die_with_usage picks a variant
to use for the DIE for a FUNCTION_TYPE or METHOD_TYPE, as does
modified_type_die. The two need to pick the same variant, otherwise
modified_type_die will not find the DIE that was written earlier.
Unfortunately the loops were w
On Mon, Jan 30, 2017 at 9:36 PM Jonathan Wakely wrote:
>
> On 30/01/17 13:28 +, Jonathan Wakely wrote:
> >On 30/01/17 13:47 +0200, Ville Voutilainen wrote:
> >>Tested on Linux-x64.
> >
> >OK, thanks.
>
> To be clear: this isn't approved by LWG yet, but I think we can be a
> bit adventurous wit
Hi!
On Mon, Jan 23, 2017 at 09:36:29PM +0100, Jakub Jelinek wrote:
> So, I've bootstrapped/regtested s390x-linux (64-bit only, don't have 32-bit
> userland around anymore to test 31-bit) with the attached patch (and on top
> of the PR79168 patch I'll post soon) and the
> only regressions I got are
Bug 79275 - -Wformat-overflow false positive exceeding INT_MAX in
glibc sysdeps/posix/tempname.c points out a false positive found
during a Glibc build and caused by the checker using the upper
bound of a range of precisions in string directives with string
arguments of non-constant length. The a
Hi!
Accoring to make mddump generated tmp-mddump.md, on powerpc the only pattern
with unsigned_fix:DI where the inner operand is SF or DFmode is the
*fixuns_truncdi2_fctiduz. There is an expander for that instruction,
which uses different operand predicates and different condition, so the
followi
This URL does not work any longer, and given how old that news items
is (really, we've been supporting OpenMP for more than a decade now?),
I figured to just leave the textual reference on this one. We've got
plenty to links elsewhere.
Applied.
Gerald
Index: news.html
==
Hi Vladimir,
On 26 January 2017 at 18:09, Vladimir Makarov wrote:
> The following patch fixes
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79131
>
> The patch also adapts IP IRA in LRA because without it GCC IP RA tests
> become broken (it was just a luck that the tests worked before the patc
Hi!
The inline variable changes broke the default TLS model of non-inline static
data members. The decl_default_tls_model call needs DECL_EXTERNAL for the
!processing_template_decl be already set appropriately. The following patch
moves the thread_p processing a few lines below, so that it is al
On Fri, Jan 27, 2017 at 7:45 AM, Nathan Sidwell wrote:
> Jason,
> I happened to be working on 67273, noticed a problem with my 77585 fix, and
> coincidentally 79253 got filed, which this also fixes.
>
> In 67253, Wshadow checking was getting confused when determining the return
> type of an insta
On Mon, Jan 30, 2017 at 08:53:18PM +0100, Bernhard Reutner-Fischer wrote:
> As this will likely bri{ck,g} horribly I'll leave these to Martin and Pekka.
> Thanks for fixing but note that you attached the wrong patch below.
Oops, here is the right one (bootstrapped/regtested on x86_64-linux and
i68
On 30 January 2017 18:37:00 CET, Jakub Jelinek wrote:
>Hi!
>
>On Mon, Jan 30, 2017 at 05:56:36PM +0100, Bernhard Reutner-Fischer
>wrote:
>> On 30 January 2017 10:56:59 CET, Jakub Jelinek
>wrote:
>>
>> >+++ libhsail-rt/rt/sat_arithmetic.c 2017-01-30 10:27:27.861325330
>+0100
>> >@@ -49,21 +49,18
On January 30, 2017 7:02:38 PM GMT+01:00, Jeff Law wrote:
>On 01/30/2017 02:51 AM, Richard Biener wrote:
>> On Fri, Jan 27, 2017 at 11:21 PM, Jeff Law wrote:
>>> On 01/27/2017 02:35 PM, Richard Biener wrote:
On January 27, 2017 7:30:07 PM GMT+01:00, Jeff Law
>wrote:
>
> On 01/2
This patch fixes the __atomic builtins to not implement supposedly
lock-free atomic loads based on just a compare-and-swap operation.
If there is no hardware-backed atomic load for a certain memory
location, the current implementation can implement the load with a CAS
while claiming that the acces
Hi!
The brig FE doesn't build on i686-linux, because size_t arguments
get a warning there when used with %lu. As %zu is not portable enough,
cast to ulong is what is generally used elsewhere.
Bootstrapped/regtested on x86_64-linux and i686-linux, committed to trunk
as obvious.
2017-01-30 Jakub
Hi!
This is yet another occurrence of the bug that we drop lhs on noreturn
calls even when it actually should not be dropped (if it has addressable
type or if it is a variable length type).
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2017-01-30 Jakub Jelinek
Hi!
cp_build_modify_expr has some special code for the case when the lhs
is pre{inc,dec}rement, assignment, ?: or min/max, but the comma expression
handling has been removed (so that -fstrong-eval-order is honored; can't
we keep the previous behavior for -fstrong-eval-order=none and/or some?),
whi
On 01/30/2017 02:51 AM, Richard Biener wrote:
On Fri, Jan 27, 2017 at 11:21 PM, Jeff Law wrote:
On 01/27/2017 02:35 PM, Richard Biener wrote:
On January 27, 2017 7:30:07 PM GMT+01:00, Jeff Law wrote:
On 01/27/2017 05:08 AM, Richard Biener wrote:
On Fri, Jan 27, 2017 at 10:02 AM, Marc Gli
On 30/01/17 17:54 +, Jonathan Wakely wrote:
This adds the porting to guide for GCC 7. So far it only has details
of C++ changes, mostly in the std::lib.
Committed to CVS.
And this fixes the HTML errors.
Committed to CVS.
Index: htdocs/gcc-7/porting_to.html
===
This adds the porting to guide for GCC 7. So far it only has details
of C++ changes, mostly in the std::lib.
Committed to CVS.
Index: htdocs/gcc-7/porting_to.html
===
RCS file: htdocs/gcc-7/porting_to.html
diff -N htdocs/gcc-7/portin
On Jan 29, 2017, Cary Coutant wrote:
>> for gcc/ChangeLog
>>
>> PR debug/63238
> This is OK so far, but the DW_AT_alignment attribute also needs to be
> added to the checksum computation in die_checksum and
> die_checksum_ordered.
Thanks. I see what to do in die_checksum_ordered, but die_chec
Hi!
On Mon, Jan 30, 2017 at 05:56:36PM +0100, Bernhard Reutner-Fischer wrote:
> On 30 January 2017 10:56:59 CET, Jakub Jelinek wrote:
>
> >+++ libhsail-rt/rt/sat_arithmetic.c 2017-01-30 10:27:27.861325330 +0100
> >@@ -49,21 +49,18 @@ __hsail_sat_add_u16 (uint16_t a, uint16_
> > uint64_t
> > __h
Hi,
The builtins for the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw Loongson
instructions have the third argument's type set to UQI while its corresponding
insn operand is in SImode.
This results in the following error when matching insn operands:
../gcc/gcc/include/loongson.h: In function
On 01/30/2017 10:03 AM, Richard Biener wrote:
On Fri, Jan 27, 2017 at 12:20 PM, Aldy Hernandez wrote:
On 01/26/2017 07:29 AM, Richard Biener wrote:
On Thu, Jan 26, 2017 at 1:04 PM, Aldy Hernandez wrote:
On 01/24/2017 07:23 AM, Richard Biener wrote:
Your initial on-demand approach is fi
On 27/01/17 12:13, Ramana Radhakrishnan wrote:
> On Thu, Jan 26, 2017 at 3:56 PM, Andre Vieira (lists)
> wrote:
>> On 20/01/17 14:08, Ramana Radhakrishnan wrote:
>>> On Wed, Dec 28, 2016 at 9:58 AM, Andre Vieira (lists)
>>> wrote:
On 29/11/16 09:45, Andre Vieira (lists) wrote:
> On 17/11
On Mon, Jan 30, 2017 at 8:55 AM, Richard Earnshaw (lists)
wrote:
> On 28/01/17 20:34, Andrew Pinski wrote:
>> Hi,
>> On some (most) AARCH64 cores, it is not always profitable to
>> vectorize some integer loops. This patch does two things (I can split
>> it into different patches if needed).
>>
On 28/01/17 20:34, Andrew Pinski wrote:
> Hi,
> On some (most) AARCH64 cores, it is not always profitable to
> vectorize some integer loops. This patch does two things (I can split
> it into different patches if needed).
> 1) It splits the aarch64 back-end's vector cost model's vector and
> scal
On Mon, Jan 30, 2017 at 3:24 AM, Maxim Kuvyrkov
wrote:
> This patch series improves -fprefetch-loop-arrays pass through small fixes
> and tweaks, and then enables it for several AArch64 cores.
>
> My tunings were done on and for Qualcomm hardware, with results varying
> between +0.5-1.9% for SPE
On Mon, Jan 30, 2017 at 3:48 AM, Maxim Kuvyrkov
wrote:
> This patch port prefetch configuration from aarch32 backend to aarch64.
> There is no code-generation change from this patch.
>
> This patch also happens to address Kyrill's comment on Andrew's prefetching
> patch at https://gcc.gnu.org/m
On Mon, Jan 30, 2017 at 2:01 AM, Richard Biener
wrote:
> On Sat, Jan 28, 2017 at 9:34 PM, Andrew Pinski wrote:
>> Hi,
>> On some (most) AARCH64 cores, it is not always profitable to
>> vectorize some integer loops. This patch does two things (I can split
>> it into different patches if needed)
On Mon, Jan 30, 2017 at 6:49 AM, Maxim Kuvyrkov
wrote:
>> On Jan 27, 2017, at 6:59 PM, Andrew Pinski wrote:
>>
>> On Fri, Jan 27, 2017 at 4:11 AM, Richard Biener
>> wrote:
>>> On Fri, Jan 27, 2017 at 1:10 PM, Richard Biener
>>> wrote:
On Thu, Jan 26, 2017 at 9:56 PM, Andrew Pinski wrote:
On Mon, Jan 30, 2017 at 4:14 AM, Maxim Kuvyrkov
wrote:
>> On Jan 27, 2017, at 1:54 PM, Kyrill Tkachov
>> wrote:
>>
>>
>> On 26/01/17 20:56, Andrew Pinski wrote:
>>> Hi,
>>> This patch enables -fprefetch-loop-arrays for -mcpu=thunderxt88 and
>>> -mcpu=thunderxt88p1. I filled out the tuning str
On 1/27/17 5:43 PM, Segher Boessenkool wrote:
On Fri, Jan 27, 2017 at 12:11:05PM -0600, Aaron Sawdey wrote:
+addi 9,4,7
+lwbrx 10,0,9
+addi 9,5,7
+lwbrx 9,0,9
It would be nice if this was
li 9,7
lwbrx 10,9,4
lwbrx 9,9,5
Hi Cesar!
On Mon, 30 Jan 2017 07:19:27 -0800, Cesar Philippidis
wrote:
> On 01/30/2017 02:26 AM, Thomas Schwinge wrote:
> > On Fri, 27 Jan 2017 08:06:22 -0800, Cesar Philippidis
> > wrote:
> > PASS: libgomp.fortran/examples-4/async_target-2.f90 -O0 (test for
> > excess errors)
> >
On 01/30/2017 04:12 PM, Richard Biener wrote:
> On Mon, Jan 30, 2017 at 4:09 PM, Martin Liška wrote:
>> Hello.
>>
>> During investigation of another issue, I accidentally came a profile
>> inconsistency
>> mentioned in the PR. Problem is that flag_ipa_bit_cp is enabled in use stage
>> of PGO
>>
Hi Cesar! (It's me, again!) ;-)
On Fri, 27 Jan 2017 09:13:06 -0800, Cesar Philippidis
wrote:
> This patch partially enables GOMP_MAP_FIRSTPRIVATE_POINTER in gfortran.
> gfortran still falls back to GOMP_MAP_POINTER for arrays with
> descriptors and derived types. The limitation on derived type
On Mon, Jan 30, 2017 at 04:14:40PM +0100, Richard Biener wrote:
> > as was figured out in PR, using DECL_NAME (TRANSLATION_UNIT_DECL) does not
> > always give us a correct module name in LTO mode because e.g. DECL_CONTEXT
> > of
> > some variables can be NAMESPACE_DECL and LTO merges NAMESPACE_DEC
On 01/30/2017 02:26 AM, Thomas Schwinge wrote:
> On Fri, 27 Jan 2017 08:06:22 -0800, Cesar Philippidis
> wrote:
>> This is probably because CloverLeaf makes use
>> of ACC DATA regions in the critical sections, so all of those PSETs and
>> POINTERs are already preset on the accelerator.
>>
>> One
On Mon, Jan 30, 2017 at 06:09:36PM +0300, Maxim Ostapenko wrote:
> Hi,
>
> as was figured out in PR, using DECL_NAME (TRANSLATION_UNIT_DECL) does not
> always give us a correct module name in LTO mode because e.g. DECL_CONTEXT
> of some variables can be NAMESPACE_DECL and LTO merges NAMESPACE_DECL
On Mon, 30 Jan 2017, Maxim Ostapenko wrote:
> Hi,
>
> as was figured out in PR, using DECL_NAME (TRANSLATION_UNIT_DECL) does not
> always give us a correct module name in LTO mode because e.g. DECL_CONTEXT of
> some variables can be NAMESPACE_DECL and LTO merges NAMESPACE_DECLs.
Yes, it indeed d
On Mon, Jan 30, 2017 at 4:09 PM, Martin Liška wrote:
> Hello.
>
> During investigation of another issue, I accidentally came a profile
> inconsistency
> mentioned in the PR. Problem is that flag_ipa_bit_cp is enabled in use stage
> of PGO
> and not in instrumentation stage. That causes ccp1 to f
> On Jan 26, 2017, at 11:56 PM, Andrew Pinski wrote:
>
> Hi,
> This patch enables -fprefetch-loop-arrays for -mcpu=thunderxt88 and
> -mcpu=thunderxt88p1. I filled out the tuning structures for both
> thunderx and thunderx2t99. No other core current enables software
> prefetching so I set them
Hi,
as was figured out in PR, using DECL_NAME (TRANSLATION_UNIT_DECL) does
not always give us a correct module name in LTO mode because e.g.
DECL_CONTEXT of some variables can be NAMESPACE_DECL and LTO merges
NAMESPACE_DECLs. The easiest fix is just to disable the initialization
order checkin
Hello.
During investigation of another issue, I accidentally came a profile
inconsistency
mentioned in the PR. Problem is that flag_ipa_bit_cp is enabled in use stage of
PGO
and not in instrumentation stage. That causes ccp1 to find nonzero bits and
that leads
to a CFG changes as a condition ca
On Mon, Jan 30, 2017 at 3:49 PM, Maxim Kuvyrkov
wrote:
>> On Jan 27, 2017, at 6:59 PM, Andrew Pinski wrote:
>>
>> On Fri, Jan 27, 2017 at 4:11 AM, Richard Biener
>> wrote:
>>> On Fri, Jan 27, 2017 at 1:10 PM, Richard Biener
>>> wrote:
On Thu, Jan 26, 2017 at 9:56 PM, Andrew Pinski wrote:
On Fri, Jan 27, 2017 at 12:20 PM, Aldy Hernandez wrote:
> On 01/26/2017 07:29 AM, Richard Biener wrote:
>>
>> On Thu, Jan 26, 2017 at 1:04 PM, Aldy Hernandez wrote:
>>>
>>> On 01/24/2017 07:23 AM, Richard Biener wrote:
>
>
>> Your initial on-demand approach is fine to catch some of the cases but
> On Jan 27, 2017, at 6:59 PM, Andrew Pinski wrote:
>
> On Fri, Jan 27, 2017 at 4:11 AM, Richard Biener
> wrote:
>> On Fri, Jan 27, 2017 at 1:10 PM, Richard Biener
>> wrote:
>>> On Thu, Jan 26, 2017 at 9:56 PM, Andrew Pinski wrote:
Hi,
This patch enables -fprefetch-loop-arrays for -
> On Jan 30, 2017, at 3:23 PM, Kyrill Tkachov
> wrote:
>
> Hi Maxim,
>
> On 30/01/17 12:06, Maxim Kuvyrkov wrote:
>> This patch enables prefetching at -O3 for aarch64 cores that set
>> "simultaneous prefetches" parameter above 0. There are currently no such
>> settings, so this patch doesn't
The recent changes to the header infrastructure for ARM targets broke
building of plugins due to missing headers.
Patch below, tested on a cross build plus visual examination of the
install infrastructure.
PR target/79260
* config.gcc (arm*-*-*): Add arm/arm-flags.h and arm/arm-isa.h to tm_p_file
On Tue, Jun 21, 2016 at 09:00:58AM -0600, Jeff Law wrote:
> On 06/21/2016 08:14 AM, Bernhard Reutner-Fischer wrote:
> > Hi!
> >
> > Ok for trunk?
> >
> > thanks,
> >
> > contrib/ChangeLog
> >
> > 2016-06-21 Bernhard Reutner-Fischer
> >
> > * update-copyright.py (Copyright.process_file):
On Mon, Jan 30, 2017 at 10:47:12AM +0100, Martin Liška wrote:
> Hi.
>
> Following patch simply fixes issues reported by -Wmaybe-unitialized. That
> enables PGO bootstrap
> on ThunderX aarch64 machine.
>
> Ready to be installed?
OK.
Thanks,
James
Bootstrapped / tested on x86_64-unknown-linux-gnu, applied.
Richard.
2017-01-30 Richard Biener
PR tree-optimization/79276
* tree-vrp.c (process_assert_insertions): Properly adjust common
when removing a duplicate.
* gcc.dg/torture/pr79276.c: New testcase.
In
Hi Thomas,
On 30/01/17 13:32, Thomas Preudhomme wrote:
Hi,
ARM backend now support a new set of multilib libraries enabled with
--with-multilib-list=rmprofile [1]. This patch documents it in the changes for
GCC 7.
[1] https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=r242696
Is this ok
On 30/01/17 13:28 +, Jonathan Wakely wrote:
On 30/01/17 13:47 +0200, Ville Voutilainen wrote:
Tested on Linux-x64.
OK, thanks.
To be clear: this isn't approved by LWG yet, but I think we can be a
bit adventurous with deduction guides and add them for experimental
C++17 features. Getting
On 01/30/2017 12:27 PM, Martin Liška wrote:
> Hi.
>
> Following patch simply fixes issues reported by -Wmaybe-unitialized. That
> enables PGO bootstrap
> on a s390x machine.
>
> Ready to be installed?
> Martin
>
There's second version that adds one more hunk for s390 target.
Martin
>From 598d
Hi,
ARM backend now support a new set of multilib libraries enabled with
--with-multilib-list=rmprofile [1]. This patch documents it in the changes for
GCC 7.
[1] https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=r242696
Is this ok for wwwdocs?
Best regards,
Thomas
Index: htdocs/gcc-7
On 30/01/17 13:47 +0200, Ville Voutilainen wrote:
Tested on Linux-x64.
OK, thanks.
On Mon, Jan 30, 2017 at 12:43 PM, Maxim Kuvyrkov
wrote:
> This patch fixes heuristic in loop array prefetching to use
> "round-to-nearest" instead of "floor", which is what _all_ other similar
> heuristics in the pass are doing.
_all_ is a bit over-exaggregating... In the context we are testin
On Mon, Jan 30, 2017 at 12:36 PM, Maxim Kuvyrkov
wrote:
> Current debug output from -fprefetch-loop-arrays refers to prefetching
> instances by their (void *) address, which makes it painful to compare dumps,
> e.g., when investigating how different parameter values affect prefetching
> decisio
On Mon, Jan 30, 2017 at 12:28 PM, Maxim Kuvyrkov
wrote:
> This patch adds a debug counter to -fprefetch-loop-arrays pass. It can be
> activated by "-fdbg-cnt=prefetch:10" to allow only 10 first prefetches to be
> issued.
>
> Bootstrapped and regtested on x86_64-linux-gnu and aarch64-linux-gnu.
Hi Maxim,
On 30/01/17 12:06, Maxim Kuvyrkov wrote:
This patch enables prefetching at -O3 for aarch64 cores that set "simultaneous
prefetches" parameter above 0. There are currently no such settings, so this patch
doesn't change default code generation.
I'm now working on improvements to -fpr
> On Jan 27, 2017, at 1:54 PM, Kyrill Tkachov
> wrote:
>
>
> On 26/01/17 20:56, Andrew Pinski wrote:
>> Hi,
>> This patch enables -fprefetch-loop-arrays for -mcpu=thunderxt88 and
>> -mcpu=thunderxt88p1. I filled out the tuning structures for both
>> thunderx and thunderx2t99. No other core
This patch enables software prefetching at -O3 for Qualcomm's qdf24xx cores.
Bootstrapped and regtested on x86_64-linux-gnu and aarch64-linux-gnu.
--
Maxim Kuvyrkov
www.linaro.org
0006-Update-prefetch-tuning-parameters-for-falkor-and-qdf.patch
Description: Binary data
This patch enables prefetching at -O3 for aarch64 cores that set "simultaneous
prefetches" parameter above 0. There are currently no such settings, so this
patch doesn't change default code generation.
I'm now working on improvements to -fprefetch-loop-arrays pass to make it
suitable for -O2.
> Date: Sun, 29 Jan 2017 23:06:56 +0100 (CET)
> From: Gerald Pfeifer
> There is one reference left in gcc.gnu.org/readings.html; Hans-Peter,
> do you have a recommendation on how to best handle that? (Remove it,
> or is there a good and stable replacement?)
Sorry, I don't know. I'll open an in
This patch port prefetch configuration from aarch32 backend to aarch64. There
is no code-generation change from this patch.
This patch also happens to address Kyrill's comment on Andrew's prefetching
patch at https://gcc.gnu.org/ml/gcc-patches/2017-01/msg02133.html .
This patch also fixes a mi
Tested on Linux-x64.
2017-01-30 Ville Voutilainen
Implement LWG 2825, LWG 2756 breaks class template argument
deduction for optional.
* include/std/optional: Add a deduction guide.
* testsuite/20_util/optional/cons/deduction_guide.cc: New.
diff --git a/libstdc++-v3/include/std/
This patch fixes heuristic in loop array prefetching to use "round-to-nearest"
instead of "floor", which is what _all_ other similar heuristics in the pass
are doing.
This subtle change allows a critical loop in 429.mcf to get prefetches without
making the pass too aggressive, which causes regr
Current debug output from -fprefetch-loop-arrays refers to prefetching
instances by their (void *) address, which makes it painful to compare dumps,
e.g., when investigating how different parameter values affect prefetching
decisions.
This patch adds UIDs to two main prefetching concepts: mem_r
On 25/01/17 12:35, Szabolcs Nagy wrote:
> ARM libatomic inline asm uses sel, uadd8, uadd16 instructions
> which are only available if __ARM_FEATURE_SIMD32 is defined.
>
> libatomic/
> 2017-01-25 Szabolcs Nagy
>
> PR target/78945
> * config/arm/exch_n.c (libat_exchange): Check __ARM
This patch adds a debug counter to -fprefetch-loop-arrays pass. It can be
activated by "-fdbg-cnt=prefetch:10" to allow only 10 first prefetches to be
issued.
Bootstrapped and regtested on x86_64-linux-gnu and aarch64-linux-gnu.
--
Maxim Kuvyrkov
www.linaro.org
0001-Add-debug-counter-for-lo
Hi.
Following patch simply fixes issues reported by -Wmaybe-unitialized. That
enables PGO bootstrap
on a s390x machine.
Ready to be installed?
Martin
>From 3f3c3fe790ebffd038a033b6946de663e2305574 Mon Sep 17 00:00:00 2001
From: marxin
Date: Mon, 30 Jan 2017 11:09:29 +0100
Subject: [PATCH] Fix P
On Mon, 30 Jan 2017, Uros Bizjak wrote:
> On Mon, Jan 30, 2017 at 11:56 AM, Richard Biener wrote:
> > On Mon, 30 Jan 2017, Jakub Jelinek wrote:
> >
> >> On Mon, Jan 30, 2017 at 11:47:51AM +0100, Richard Biener wrote:
> >> > On Mon, 30 Jan 2017, Uros Bizjak wrote:
> >> >
> >> > > > 2017-01-30 Ric
This patch series improves -fprefetch-loop-arrays pass through small fixes and
tweaks, and then enables it for several AArch64 cores.
My tunings were done on and for Qualcomm hardware, with results varying between
+0.5-1.9% for SPEC2006 INT and +0.25%-1.0% for SPEC2006 FP at -O3, depending on
h
On Mon, Jan 30, 2017 at 11:56 AM, Richard Biener wrote:
> On Mon, 30 Jan 2017, Jakub Jelinek wrote:
>
>> On Mon, Jan 30, 2017 at 11:47:51AM +0100, Richard Biener wrote:
>> > On Mon, 30 Jan 2017, Uros Bizjak wrote:
>> >
>> > > > 2017-01-30 Richard Biener
>> > > >
>> > > > PR target/79277
>> > >
Hi Jakub,
Thanks for noticing that. Of course the declaration had to be in the
header for this case
Alexander
2017-01-30 13:13 GMT+03:00 Jakub Jelinek :
> Hi!
>
> On Mon, Dec 26, 2016 at 06:15:01PM +0300, Alexander Ivchenko wrote:
>> Submitted as r243928.
>> >> (__mpxrt_stop): Ditto.
>
> I've no
On Mon, 30 Jan 2017, Jakub Jelinek wrote:
> On Mon, Jan 30, 2017 at 11:47:51AM +0100, Richard Biener wrote:
> > On Mon, 30 Jan 2017, Uros Bizjak wrote:
> >
> > > > 2017-01-30 Richard Biener
> > > >
> > > > PR target/79277
> > > > * config/i386/i386-modes.def: Align DFmode properly.
> > >
> >
On Mon, Jan 30, 2017 at 11:47:51AM +0100, Richard Biener wrote:
> On Mon, 30 Jan 2017, Uros Bizjak wrote:
>
> > > 2017-01-30 Richard Biener
> > >
> > > PR target/79277
> > > * config/i386/i386-modes.def: Align DFmode properly.
> >
> > Index: gcc/config/i386/i386-modes.def
> > =
On Mon, 30 Jan 2017, Uros Bizjak wrote:
> > 2017-01-30 Richard Biener
> >
> > PR target/79277
> > * config/i386/i386-modes.def: Align DFmode properly.
>
> Index: gcc/config/i386/i386-modes.def
> ===
> --- gcc/config/i386/i386-mode
> 2017-01-30 Richard Biener
>
> PR target/79277
> * config/i386/i386-modes.def: Align DFmode properly.
Index: gcc/config/i386/i386-modes.def
===
--- gcc/config/i386/i386-modes.def (revision 245021)
+++ gcc/config/i386/i386-modes.de
Hi,
>
> Andrew Burgess (2):
> ARC: Make arc_selected_cpu global
> ARC: Better creation of __NPS400__ define
>
> gcc/ChangeLog | 31
> gcc/config/arc/arc-arch.h | 50 ++
> ---
> gcc/config/arc/arc-c.def|
The following fixes PR79256 in a way suitable for stage4. But the
underlying issue is that our IL advertises bogus alignment for
types like double on i?86 as their alignment inside structures
is 4 bytes, not 8, and double_type_node advertises 64bit alignment.
UBSAN folks invented the min_align_of
Hi!
On Fri, 27 Jan 2017 08:06:22 -0800, Cesar Philippidis
wrote:
> This patch optimizes GOMP_MAP_TO_PSET in libgomp by installing the
> remapped pointer to the array data directly in the PSET, instead of
> uploading it separately with GOMP_MAP_POINTER. Effectively this
> eliminates the GOMP_MAP_
Hi Cesar!
On Fri, 27 Jan 2017 07:45:52 -0800, Cesar Philippidis
wrote:
> If you take a close look at lower_omp_target, you'll notice that I'm
> gave reference types special treatment. Specifically, I disabled this
> optimization on non-INTEGER_TYPE and floating point values, because the
> nvptx
Hi!
On Mon, Dec 26, 2016 at 06:15:01PM +0300, Alexander Ivchenko wrote:
> Submitted as r243928.
> >> (__mpxrt_stop): Ditto.
I've noticed:
../../../../libmpx/mpxrt/mpxrt.c:255:6: warning: implicit declaration of
function ‘__mpxrt_stop’; did you mean ‘__mpxrt_mode’? [-Wimplicit-function
__mp
On Mon, Jan 30, 2017 at 12:23 AM, kugan
wrote:
> Hi All,
>
> As suggested by Richard in the PR, I tried to implement variable size
> structures for VR as shown in attached patch. That is, I changed ipa-prop.h
> to:
>
> diff --git a/gcc/ipa-prop.h b/gcc/ipa-prop.h
> index 93a2390c..acab2aa 100644
>
Hi Cesar!
On Thu, 10 Nov 2016 09:38:33 -0800, Cesar Philippidis
wrote:
> This patch has been committed to gomp-4_0-branch.
> --- a/gcc/fortran/openmp.c
> +++ b/gcc/fortran/openmp.c
> @@ -242,7 +243,8 @@ gfc_match_omp_variable_list (const char *str,
> gfc_omp_namelist **list,
> case MATC
On Sat, Jan 28, 2017 at 9:34 PM, Andrew Pinski wrote:
> Hi,
> On some (most) AARCH64 cores, it is not always profitable to
> vectorize some integer loops. This patch does two things (I can split
> it into different patches if needed).
> 1) It splits the aarch64 back-end's vector cost model's ve
Hi!
I've noticed a bug in libhsail-rt/configure.tgt - those files are actually
pure shell script, not autoconf templates (they are just sourced from
the autoconf templates as well as configure scripts generated by autoconf),
so [[ ]] doesn't really work there.
After fixing that I've noticed that
On 01/26/2017 09:42 PM, Dominik Vogt wrote:
> On Thu, Jan 26, 2017 at 05:45:18PM +0100, Jakub Jelinek wrote:
>> On Thu, Jan 26, 2017 at 05:43:13PM +0100, Dominik Vogt wrote:
If the predicates are supposed to ensure it, then I think the assert is
fine.
>>>
>>> Is it guaranteed that the pre
On Fri, Jan 27, 2017 at 11:21 PM, Jeff Law wrote:
> On 01/27/2017 02:35 PM, Richard Biener wrote:
>>
>> On January 27, 2017 7:30:07 PM GMT+01:00, Jeff Law wrote:
>>>
>>> On 01/27/2017 05:08 AM, Richard Biener wrote:
On Fri, Jan 27, 2017 at 10:02 AM, Marc Glisse
>>>
>>> wrote:
>
>>>
Hi.
Following patch simply fixes issues reported by -Wmaybe-unitialized. That
enables PGO bootstrap
on ThunderX aarch64 machine.
Ready to be installed?
Martin
>From 6188df717836ee79f4d7951dca5066ef10b577a1 Mon Sep 17 00:00:00 2001
From: marxin
Date: Mon, 30 Jan 2017 10:44:07 +0100
Subject: [PAT
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