Hi,
Currently for the following function:
int f(int a, int b)
{
return a + (b <<7);
}
GCC produces:
add w0, w0, w1, lsl 7
But for ThunderX 1, it is better if the instruction was split allowing
better scheduling to happen in most cases, the latency is the same. I
get a small improvement in
This addresses PR libobjc/78698, fixing the build with --disable-shared and .la
files available. As mentioned in the bug report I'm not aware of a configure
check to write a check using LIBTOOL_LINK and LIBTOOL_COMPILE, because these
commands (using libtool) are only created by running the configu
This addresses PR libobjc/78697, allowing a common include dir for all multilib
variants. Tested with a libgc installation in /opt/gcc/include, /opt/gcc/lib32,
/opt/gcc/lib64 and configured with
--prefix=/opt/gcc7 --enable-languages=c,c++,objc --disable-shared
--enable-objc-gc=yes --with-multilib
I've checked in the attached patch to reorder entries in cppopts.texi.
I put the most-commonly-used options (e.g. -D and -U) first, and the
options for debugging cpp last, and tried to group the things in between
a little better.
There's no change to actual content here, just the ordering.
-S
The signbit-3.c test explicitly tests for the value coming from memory, a
vector register, or a GPR. Unfortunately, the code did not handle splitting up
the registers when the value was in a GPR.
These patches add teh GPR support. While I was editing the code, I also did
some cleanup.
I removed
Also, use wi::shifted_mask helper function instead of hardcoding it.
No functional changes.
2016-12-30 Uros Bizjak
* config/i386/i386.md (*testqi_ext_3): Merge insn pattern and
corresponding splitter to define_insn_and_split. Use wi::shifted_mask
helper function to calculate mask
On Thu, 29 Dec 2016, Jakub Jelinek wrote:
> Hi!
>
> As mentioned in the PR, the option handling for multi-line help texts
> concatenates those lines with spaces in between (essentially replaces
> newlines with spaces), but exgettext extracts just the first line from the
> multiline help text and
On Fri, Dec 30, 2016 at 03:37:14PM +0100, Uros Bizjak wrote:
> As suggested in [1], you should write multi-line enums like:
>
> enum foo
> {
> a = ...
> b = ...
> }
Sure. Plus it depends on if users of the APIs should just write the
operands on their own as numbers, or as __SGX_E*, or as E*.
This patch by Than McIntosh fixes the Go frontend to wrap the return
from Type::gc_symbol_pointer with a type conversion to uintptr, since
the values returned are stored into structure fields with that type.
Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed
to mainline.
Ian
Inde
Applied (as revision 243975), and I plan on backporting to the GCC 6
and GCC 5 branches later.
Gerald
2016-12-30 Gerald Pfeifer
* doc/standards.texi (Standards): Remove broken reference to
objc.toodarkpark.net and avoid list with now just one item.
Index: doc/standards.texi
=
Hello!
We only have to copy registers without upper parts to a pseudo in
named patterns (extv, extzv and insv). Nowadays, it is the job of
TARGET_LEGITIMATE_COMBINED_INSN target hook to prevent propagation of
unwanted hard registers to a combined insn.
So, only check the supported mode in the pre
This atrocious link is now broken (or kind of, redirecting to a
generic page talking about software support and roadmap/future)
of True64. ;-)
Applied
Gerald
Index: gcc-3.4/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-3.4
On Fri, Dec 30, 2016 at 3:17 PM, Koval, Julia wrote:
> Thank you for your comments, how about this patch? Enums are not part of the
> intrinsic ABI, they are just meaningful names for constants, taken from
> reference doc.
>
> gcc/
> * common/config/i386/i386-common.c
>(OPTION_MASK_I
Thank you for your comments, how about this patch? Enums are not part of the
intrinsic ABI, they are just meaningful names for constants, taken from
reference doc.
gcc/
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_SGX_UNSET, OPTION_MASK_ISA_SGX_SET): New.
(ix86_handle_op
On Fri, Dec 30, 2016 at 09:25:49AM +0100, Uros Bizjak wrote:
> On Thu, Dec 29, 2016 at 10:50 AM, Koval, Julia wrote:
> > Hi,
> >
> > This patch enables Intel SGX instructions (Reference:
> > https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
> > page 44
On Thu, Dec 29, 2016 at 10:50 AM, Koval, Julia wrote:
> Hi,
>
> This patch enables Intel SGX instructions (Reference:
> https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
> page 4478 in pdf and 3D 41-1 in page numbers) Ok for trunk?
I don't like asm ma
16 matches
Mail list logo
