Re: [PATCH] [AArch64] Fix PR78382

Hi James, Thanks for the review and suggestions regarding the testcase. >> Why limit the ABI and endianness here Extra options have been dropped and the testcase will check across all variants and endianness. Please find attached the modified patch as per the comments and let me know if its oka

Re: [PATCH] [AArch64] Fix PR71112

Hi James, Thanks for the review and suggestions regarding the testcase. >> Why limit the ABI and endianness here, and if you do plan to do that Extra options have been dropped and the testcase will check across all variants and endianness. Please find attached the modified patch as per the comm

Re: [patch v2] Get rid of stack trampolines for nested functions (1/4)

> > Btw, Ian, if the heap trampoline support is no longer used by the Go > > compiler, you might want to remove it from the middle-end. > > Yes, I suppose so. The Go frontend hasn't used them for a while. Speaking of obsolete stuff, do you have any opinion on the below patch? https://gcc.gnu.o

[PATCH], PR target/72717, Fix PowerPC abort in emit_move_insn from rs6000_expand_vector_init

This patch fixes an abort in vector initialization on ISA 2.07 (power8) and above (it needs a vector long shift left, which was not in ISA 2.06). A V2DImode value was being initialized with two elements. Each element has a SImode SUBREG wrapped around a DImove value. Force_reg was being called w

Re: [AArch64][ARM][GCC][PATCHv2 3/3] Add tests for missing Poly64_t intrinsics to GCC

On Wed, Nov 30, 2016 at 1:04 AM, Christophe Lyon wrote: > Hi Tamar, > > > On 29 November 2016 at 14:54, James Greenhalgh > wrote: >> On Tue, Nov 29, 2016 at 01:48:22PM +, Kyrill Tkachov wrote: >>> >>> On 29/11/16 09:50, Tamar Christina wrote: >>> >Hi All, >>> > >>> >The new patch contains th

[committed] Fix x86_64-ism in selftest (PR bootstrap/78705)

In r243317 I accidentally introduced an assumption in a selftest in i386.c that Pmode == DImode. This patch conditionalizes the overzealous string comparison to avoid breaking the build on 32-bit i386.c targets. Committed to trunk as r243332 as obvious. Sorry about the breakage. gcc/ChangeLog:

Re: [PATCH] add missing attribute nonnull to stdio functions (PR 78673 and 17308)

On 12/05/2016 03:56 PM, Martin Sebor wrote: The new -Wformat-length warning pass detects and diagnoses non- constant null format strings. This is in addition to (but not in conflict with) -Wformat which is limited to detecting only null constants. A recently posted patch of mine also adds the d

Re: [PATCH] correct handling of non-constant width and precision (pr 78521)

On 12/05/2016 11:52 AM, Martin Sebor wrote: What's the concern with using std::abs? My concern, when I wrote the reply n Friday, was that not all C++98 implementations may get std::abs right, declare it in the right header, avoid defining the abs macro, or put it in namespace std. (IIRC, the s

[PR tree-optimization/67955] Exploit PTA in DSE

So I was going through the various DSE related bugs as stumbled across 67955. The basic issue in 67955 is that DSE is too simplistic when trying to determine if two writes hit the same memory address. There are cases were PTA analysis can get us that information. The unfortunate problem

Fix PR middle-end/78700

The PR is about a couple of regressions in the Go testsuite on PowerPC64/Linux introduced by the patch implementing support for custom descriptors for nested functions. The problematic hunk is the change to expand_call, which moves up the call to prepare_call_address ; this turns out to be prob

config/ sync with binutils vs. removing gcc targets.

I understand that config/ in the gcc repository is the master source for binutils-gdb config/. If that's the case then people removing gcc support for particular targets need to be careful about their config/ edits. If a target is still supported in binutils, then please don't rip out config/ sup

Go patch committed: Tell backend whether Var is lvalue or rvalue

This patch by Than McIntosh changes the Go frontend's backend interface to tell the backend whether a variable reference is an lvalue or an rvalue. This adds a new flag on the Var_expression class that indicates whether the var reference appears in an "lvalue" context (for example, on the LHS of a

Re: [patch v2] Get rid of stack trampolines for nested functions (1/4)

> I tried this patch applied against latest and it fixed the testcases > that I had reported as failing, but the patch also causes > > libgo reflect testcase to fail. Still testing to verify and will report > the failure details. Please double check, as I can reproduce neither on PowerPC64 nor o

Re: [PATCH], PR target/78658: Fix PowerPC ISA 3.0 convert floating point to char and back

On Tue, Dec 06, 2016 at 03:47:18PM -0600, Segher Boessenkool wrote: > Hi Mike, > > On Tue, Dec 06, 2016 at 03:56:11PM -0500, Michael Meissner wrote: > > PR target 78658 exposed a thinko that I had in extending the conversion of > > QImode and HImode to floating point. If the QImode/HImode value w

Re: [PATCH, rs6000] pr65479 Add -fasynchronous-unwind-tables when the -fsanitize=address option is seen

On Tue, Dec 06, 2016 at 03:55:54PM -0600, Segher Boessenkool wrote: > On Tue, Dec 06, 2016 at 03:23:06PM -0600, Bill Seurer wrote: > > 2016-12-06 Bill Seurer > > > > PR sanitizer/65479 > > * gcc/config/rs6000/rs6000.c: Add -fasynchronous-unwind-tables option > > when > > -fsanitize

Re: [patch v2] Get rid of stack trampolines for nested functions (1/4)

I tried this patch applied against latest and it fixed the testcases that I had reported as failing, but the patch also causes libgo reflect testcase to fail. Still testing to verify and will report the failure details. On 12/06/2016 02:18 PM, Ian Lance Taylor wrote: On Tue, Dec 6, 2016 at

Re: [PATCH v3, rs6000] Add built-in support for vector compare listed in the ABI

On Tue, Dec 06, 2016 at 01:23:24PM -0800, Carl E. Love wrote: > Per the feedback I received on the first and second versions of the > patch I have created the following patch to modify the original commit > for the vector compare built-in support. Specifically, the tests were > broken into files f

Re: [PATCH, rs6000] pr65479 Add -fasynchronous-unwind-tables when the -fsanitize=address option is seen

On Tue, Dec 06, 2016 at 03:23:06PM -0600, Bill Seurer wrote: > 2016-12-06 Bill Seurer > > PR sanitizer/65479 > * gcc/config/rs6000/rs6000.c: Add -fasynchronous-unwind-tables option > when > -fsanitize=address is specified. You should mention the function name here. > --- gc

Re: [PATCH], PR target/78658: Fix PowerPC ISA 3.0 convert floating point to char and back

Hi Mike, On Tue, Dec 06, 2016 at 03:56:11PM -0500, Michael Meissner wrote: > PR target 78658 exposed a thinko that I had in extending the conversion of > QImode and HImode to floating point. If the QImode/HImode value was in a > vector register, the pattern didn't allocate the second pseudo regis

[PATCH v3, rs6000] Add built-in support for vector compare listed in the ABI

GCC maintainers: Per the feedback I received on the first and second versions of the patch I have created the following patch to modify the original commit for the vector compare built-in support. Specifically, the tests were broken into files for the processors that supports them. This allows f

[PATCH, rs6000] pr65479 Add -fasynchronous-unwind-tables when the -fsanitize=address option is seen

[PATCH, rs6000] pr65479 Add -fasynchronous-unwind-tables when the -fsanitize=address option is seen. This patch adds the -fasynchronous-unwind-tables option to compilations when the -fsanitize=address option is seen. -fasynchronous-unwind-tables causes a full strack trace to be produced when the

Re: IRA combine_and_move_insns fix, PR78669

Hello! > In this PR, we have two registers with "replace" set for them. When > processing the first, we > delete its setter, which happens to be the only use of the other register. In > the second iteration we > then assert that the other register has a use, which would be reasonable if > we ha

[PATCH], PR target/78658: Fix PowerPC ISA 3.0 convert floating point to char and back

PR target 78658 exposed a thinko that I had in extending the conversion of QImode and HImode to floating point. If the QImode/HImode value was in a vector register, the pattern didn't allocate the second pseudo register, but the code generated a reference to that second register. The second regis

Re: [patch v2] Get rid of stack trampolines for nested functions (1/4)

On Tue, Dec 6, 2016 at 9:52 AM, Eric Botcazou wrote: >> There are a couple of changes to the RTL expander for calls; they are >> supposed to be transparent but they might have tripped on a latent issue. > > Tentative fix attached, I need to test it extensively in Ada though. Thanks. Lynn, can yo

Re: [Patches] Add variant constexpr support for visit, comparisons and get

On Tue, Dec 6, 2016 at 6:37 AM, Jonathan Wakely wrote: > On 06/12/16 12:49 +, Jonathan Wakely wrote: >> >> On 06/12/16 03:52 -0800, Tim Shen wrote: >>> >>> On Tue, Dec 6, 2016 at 2:30 AM, Jonathan Wakely wrote: This looks good - OK for trunk, thanks! >>> >>> >>> Committed. >>> >>> Th

patch to fix PR77761

The following patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77761 The patch was successfully bootstrapped and tested on x86-64 Committed as rev. 243316. Index: ChangeLog === --- ChangeLog (revision 243315) +++ ChangeLo

[PATCH, i386]: Cleanup splitters that call ix86_split_long_move

Hello! ix86_split_long_move operates on general hard registers only. Introduce and use predicates that allow only these regs (in addition to memory and/or immediate operands). No functional changes. 2016-12-06 Uros Bizjak * config/i386/predicates.md (general_gr_operand): New predicate.

Re: [PATCH], Committed, PR target/78688, fix PowerPC bootstrap issue

On Tue, Dec 06, 2016 at 08:03:32AM -0600, Segher Boessenkool wrote: > On Mon, Dec 05, 2016 at 08:05:22PM -0500, Michael Meissner wrote: > > A recent change to enable signed vs. unsigned comparisons to be flagged as > > an > > error broke the PowerPC bootstrap. > > I have been trying to find that

Re: [PATCH 8c/9] Add aarch64-specific selftests for RTL function reader

On Tue, 2016-12-06 at 17:22 +, James Greenhalgh wrote: > On Thu, Dec 01, 2016 at 09:00:11PM -0500, David Malcolm wrote: > > This patch adds more selftests for class function_reader, where > > the dumps to be read contain aarch64-specific features. > > > > In an earlier version of the patch kit

Re: Fix compilation errors with libstdc++v3 for AVR target and allow --enable-libstdcxx

On 16/09/16 02:53 -0300, Felipe Magno de Almeida wrote: On Fri, Sep 16, 2016 at 2:42 AM, Marc Glisse wrote: On Thu, 15 Sep 2016, Felipe Magno de Almeida wrote: + || sizeof(uint32_t) == sizeof(void*) +|| sizeof(uint16_t) == sizeof(void*), Indentation is off? Cal

Re: Fix compilation errors with libstdc++v3 for AVR target and allow --enable-libstdcxx

On 10/11/16 13:51 -0200, Felipe Magno de Almeida wrote: @@ -752,11 +770,13 @@ _GLIBCXX_END_NAMESPACE_LDBL_OR_CXX11 // Seconds. [tm_sec] // [00, 60] in C99 (one leap-second), [00, 61] in C89. #if _GLIBCXX_USE_C99 - __beg = _M_extract_num(__beg, _

IRA combine_and_move_insns fix, PR78669

In this PR, we have two registers with "replace" set for them. When processing the first, we delete its setter, which happens to be the only use of the other register. In the second iteration we then assert that the other register has a use, which would be reasonable if we hadn't deleted it.

Re: [PATCH v2,rs6000] Add built-in function support for Power9 byte instructions.

On Mon, Dec 05, 2016 at 08:56:30PM -0700, Kelvin Nilsen wrote: > +;; Predicate: test byte within range. Just "Test byte within range."? > +;; Return in target register operand 0 a value of 1 if the byte > +;; held in bits 24:31 of operand 1 is within the inclusive range > +;; bounded above by ope

Re: [PATCH] Fill bitregion_{start,end} in store_constructor (PR, tree-optimization/78428).

> But maybe all the non-constant offset / size cases are "dead code" now that > we are in GIMPLE? Note they likely can only appear from Ada code anyway Possibly, but to be sure put a call to gcc_unreachable where appropriate and run the Ada testsuite; if it is clean, then send me the patch and I'

Re: Fix compilation errors with libstdc++v3 for AVR target and allow --enable-libstdcxx

On 10/11/16 13:51 -0200, Felipe Magno de Almeida wrote: Subject: [PATCH 1/3] Add #ifdef case for 16 bits in cow-stdexcept.cc Added #ifdef case for when void* is 16 bits so it compiles in AVR target. I've committed this patch. From 7ed4af72fe0bdee1a38c7487955590fb64f76a5d Mon Sep 17 00:00:00

Re: [patch v2] Get rid of stack trampolines for nested functions (1/4)

> There are a couple of changes to the RTL expander for calls; they are > supposed to be transparent but they might have tripped on a latent issue. Tentative fix attached, I need to test it extensively in Ada though. Btw, Ian, if the heap trampoline support is no longer used by the Go compiler,

Re: [PATCH] Fill bitregion_{start,end} in store_constructor (PR, tree-optimization/78428).

Pinging Eric. On 11/23/2016 11:49 AM, Richard Biener wrote: > On Wed, Nov 23, 2016 at 11:26 AM, Martin Liška wrote: >> Following patch fixes situation where we do a store to a bitfield which >> is at boundary of a record. This leads to usage of wider store, leading >> to overwriting a following m

Re: [PATCH] [AArch64] Fix PR71727

On Tue, Nov 08, 2016 at 09:57:29AM +, Hurugalawadi, Naveen wrote: > Hi Kyrill, > > Thanks for the review and suggestions. > > >> It's a good idea to CC the AArch64 maintainers and reviewers > >> on aarch64 patches, or at least > > Thanks for CCing the maintainers. Added [AArch64] in the subj

Re: [PATCH 8c/9] Add aarch64-specific selftests for RTL function reader

On Thu, Dec 01, 2016 at 09:00:11PM -0500, David Malcolm wrote: > This patch adds more selftests for class function_reader, where > the dumps to be read contain aarch64-specific features. > > In an earlier version of the patch kit, these were handled using > #ifndef GCC_AARCH64_H to conditionalize

[gomp4] fix implicit data clause linker error

The patch I introduced here to fix PR70828 in gomp-4_0-branch has a bug involving the creation of new implicit data clauses for variables inside ACC PARALLEL or KERNELS regions that are present inside an enclosing ACC DATA region. Specifica

Re: [LRA] Fix ICE on pathological testcase

On Dec 6, 2016, at 8:59 AM, Eric Botcazou wrote: > >> what you got there, looks more or less exactly like what I tried >> to fix with that patch a few months ago, but unfortunately >> we were unable to get a consensus on that approach: > > It's indeed the same underlying issue, but restricted to

Re: [PATCH][AArch64] Improve TI mode address offsets

On Fri, Nov 11, 2016 at 01:14:15PM +, Wilco Dijkstra wrote: > Richard Earnshaw wrote: > > > Has this patch been truncated?  The last line above looks to be part-way > > through a hunk. > > Oops sorry, it seems the last few lines are missing. Here is the full version: OK. Thanks, James > >

Re: [LRA] Fix ICE on pathological testcase

> what you got there, looks more or less exactly like what I tried > to fix with that patch a few months ago, but unfortunately > we were unable to get a consensus on that approach: It's indeed the same underlying issue, but restricted to a specific case where reload and other passes do the right

Re: [PATCH][AArch64] Improve SHA1 scheduling

On Tue, Dec 06, 2016 at 03:10:50PM +, Wilco Dijkstra wrote: >   > > ping I haven't seen a follow-up to Andrew's point regarding other read-modify-write operations. Did youi investigate the cost of these? James > > > From: Wilco Dijkstra > Sent: 25 October 2016 18:08 > To: GCC Patches

[PATCH][ARM][committed] Sort ARMv8 processors by alphabetic order

Hi all, I believe we try to keep the lists of processors in arm-cores.def in alphabetical order (though we don't follow it strictly) and the order of the cortex-m23 and cortex-m33 sticks out a bit. This patch puts them together and in alphabetical order in relation to the other processors in t

Re: [PATCH] Added noexcept on constructors

On 6 December 2016 at 18:23, Aditya Kumar wrote: > Since g++ correctly finds this error, I'm wondering how > libstdc++-v3/src/c++11/shared_ptr.cc was compiling correctly before. Presumably because it wasn't built with __GTHREADS defined?

RE: [PATCH] Added noexcept on constructors

Since g++ correctly finds this error, I'm wondering how libstdc++-v3/src/c++11/shared_ptr.cc was compiling correctly before. With a small test case: $ cat tes.cpp class A { public: A() noexcept; }; A::A() { } $ ../../build/gcc/xg++ -B ../../build/gcc -c test.cpp -std=gnu++14 test.cpp:6:1: e

Re: [patch, libgomp, OpenACC] Additional enter/exit data map handling

Ping. On 2016/11/3 10:22 PM, Chung-Lin Tang wrote: > > Ping this patch again. > > On 2016/9/21 12:43 AM, Cesar Philippidis wrote: >>> +/* Returns the number of mappings associated with the pointer or pset. PSET + have three mappings, whereas pointer have two. */ + static int >

Re: [PATCH][AArch64] Improve TI mode address offsets

ping From: Wilco Dijkstra Sent: 11 November 2016 13:14 To: Richard Earnshaw; GCC Patches Cc: nd Subject: Re: [PATCH][AArch64] Improve TI mode address offsets   Richard Earnshaw wrote: > Has this patch been truncated?  The last line above looks to be part-way > through a hunk. Oops sorry, it

Re: [PATCH][AArch64 - v3] Simplify eh_return implementation

    ping From: Wilco Dijkstra Sent: 02 September 2016 12:31 To: Ramana Radhakrishnan; GCC Patches Cc: nd Subject: Re: [PATCH][AArch64 - v3] Simplify eh_return implementation     Ramana Radhakrishnan wrote: > Can you please file a PR for this and add some testcases ?  This sounds like > a seri

Re: [PATCH][AArch64] Improve SHA1 scheduling

  ping From: Wilco Dijkstra Sent: 25 October 2016 18:08 To: GCC Patches Cc: nd Subject: [PATCH][AArch64] Improve SHA1 scheduling     SHA1H instructions may be scheduled after a SHA1C instruction that uses the same input register.  However SHA1C updates its input, so if SHA1H is scheduled aft

Re: [PATCH], Committed, PR target/78688, fix PowerPC bootstrap issue

On Mon, Dec 05, 2016 at 08:05:22PM -0500, Michael Meissner wrote: > A recent change to enable signed vs. unsigned comparisons to be flagged as an > error broke the PowerPC bootstrap. I have been trying to find that change; can you point me to it? > I committed this patch as obvious to get the Pow

Re: [PATCH][ARM] Fix ldrd offsets

ping From: Wilco Dijkstra Sent: 03 November 2016 12:20 To: GCC Patches Cc: nd Subject: [PATCH][ARM] Fix ldrd offsets   Fix ldrd offsets of Thumb-2 - for TARGET_LDRD the range is +-1020, without -255..4091.  This reduces the number of addressing instructions when using DI mode operations (such

Re: Fix compilation errors with libstdc++v3 for AVR target and allow --enable-libstdcxx

On 10/11/16 13:51 -0200, Felipe Magno de Almeida wrote: --- a/libstdc++-v3/include/bits/locale_facets_nonio.tcc +++ b/libstdc++-v3/include/bits/locale_facets_nonio.tcc @@ -659,30 +659,38 @@ _GLIBCXX_END_NAMESPACE_LDBL_OR_CXX11 // Abbreviated weekday name [tm_wday]

[PATCH] Fix PR c++/71182 - UB in parser.c

An -fsanitize=undefined instrumented compiler shows: cp/parser.c:768:7: runtime error: member call on null pointer of type 'struct vec' 760 static inline cp_token * 761 cp_lexer_previous_token (cp_lexer *lexer) 762 { 763 cp_token_position tp = cp_lexer_previous_token_position (lexer);

Re: [PATCH v2][AArch64] Fix symbol offset limit

ping From: Wilco Dijkstra Sent: 12 September 2016 15:50 To: Richard Earnshaw; GCC Patches Cc: nd Subject: Re: [PATCH v2][AArch64] Fix symbol offset limit   Wilco wrote:    > The original example is from GCC itself, the fixed_regs array is small but > due to > optimization we can end up wit

Re: [RFC][PATCH][AArch64] Cleanup frame pointer usage

  ping From: Wilco Dijkstra Sent: 31 October 2016 18:29 To: GCC Patches Cc: nd Subject: [RFC][PATCH][AArch64] Cleanup frame pointer usage     This patch cleans up all code related to the frame pointer.  On AArch64 we emit a frame chain even in cases where the frame pointer is not required.

Re: [PATCH][ARM] Improve max_insns_skipped logic

ping From: Wilco Dijkstra Sent: 10 November 2016 17:19 To: GCC Patches Cc: nd Subject: [PATCH][ARM] Improve max_insns_skipped logic   Improve the logic when setting max_insns_skipped.  Limit the maximum size of IT to MAX_INSN_PER_IT_BLOCK as otherwise multiple IT instructions are needed, incr

Re: [PATCH][ARM] Remove movdi_vfp_cortexa8

ping From: Wilco Dijkstra Sent: 29 November 2016 11:05 To: GCC Patches Cc: nd Subject: [PATCH][ARM] Remove movdi_vfp_cortexa8   Merge the movdi_vfp_cortexa8 pattern into movdi_vfp and remove it to avoid unnecessary duplication and repeating bugs like PR78439 due to changes being applied only

Re: [PATCH][ARM] Improve Thumb allocation order

ping From: Wilco Dijkstra Sent: 30 November 2016 17:32 To: GCC Patches Cc: nd Subject: [PATCH][ARM] Improve Thumb allocation order   Thumb uses a special register allocation order to increase the use of low registers.  Oddly enough, LR appears before R12, which means that LR must be saved and

Re: [PATCH][ARM] Merge negdi2 patterns

ping From: Wilco Dijkstra Sent: 30 November 2016 17:39 To: GCC Patches Cc: nd; Bernd Edlinger Subject: [PATCH][ARM] Merge negdi2 patterns   The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2 doesn't support RSC with an immediate.  We can however emulate RSC with zero usin

Re: [Patches] Add variant constexpr support for visit, comparisons and get

On 06/12/16 12:49 +, Jonathan Wakely wrote: On 06/12/16 03:52 -0800, Tim Shen wrote: On Tue, Dec 6, 2016 at 2:30 AM, Jonathan Wakely wrote: This looks good - OK for trunk, thanks! Committed. Thanks! ChangeLog dates fixed by this patch. And pretty printer fixed by this one. The "vref

Re: [PATCH] Partial solution to LWG 523

On 30/11/16 14:45 +, Jonathan Wakely wrote: On 30/11/16 13:03 +, Jonathan Wakely wrote: On 26/11/16 16:27 -0800, Tim Shen wrote: diff --git a/libstdc++-v3/include/bits/shared_ptr_base.h b/libstdc++-v3/include/bits/shared_ptr_base.h index 953aa87..2fb70b7 100644 --- a/libstdc++-v3/inclu

Re: [PATCH v2] add -fprolog-pad=N option to c-family

> On Oct 5, 2016, at 12:45 AM, Maxim Kuvyrkov wrote: > >> On Sep 29, 2016, at 11:14 AM, Torsten Duwe wrote: >> >> In case anybody missed it, the Linux kernel side to make use >> of this has also been finished meanwhile. Of course it can not >> be accepted without compiler support; and this feat

GCC 6.3 Status Report (2016-12-06)

Status == It has been some time since the last release from the GCC 6 branch. Thus the plan is to do GCC 6.3 before Christmas which means a release candidate mid next week. Until then the GCC 6 branch is still open for regression and documentation fixes. Quality Data Priority

RE: [PATCH] MIPS MSA: Fix ICE when using out-of-range values to intrinsics

Hi, Committed as r243301. Regards, Robert > > Robert Suchanek writes: > > The revised patch attached below. > > > > Regards, > > Robert > > > > gcc/ > > * config/mips/mips.c (mips_expand_builtin_insn): Check input ranges > > of literal integer arguments. > > > > gcc/testsuite/ > > > >

Re: [Patch, fortran, RFC] Add warning for missing location information

Hi Thomas, hi all, my part of the patch was okayed by Thomas in the PR at comment #12: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78226#c12 Committed as r243300. Thomas, your part of the patch looks ok to me, too. I haven't tracked the discussion on whether it is ok to add your part of the pa

Re: [LRA] Fix ICE on pathological testcase

Hi Eric, what you got there, looks more or less exactly like what I tried to fix with that patch a few months ago, but unfortunately we were unable to get a consensus on that approach: [PATCH] Fix asm X constraint (PR inline-asm/59155) https://gcc.gnu.org/ml/gcc-patches/2016-06/msg01649.html Be

Re: [PATCH] Tree-level fix for PR 69526

On Mon, Nov 28, 2016 at 2:26 PM, Robin Dapp wrote: >>> + /* Sign-extend @1 to TYPE. */ >>> + w1 = w1.from (w1, TYPE_PRECISION (type), SIGNED); >>> >>> not sure why you do always sign-extend. If the inner op is unsigned >>> and we widen then that's certainly bogus consider

Re: [Patches] Add variant constexpr support for visit, comparisons and get

On 06/12/16 03:52 -0800, Tim Shen wrote: On Tue, Dec 6, 2016 at 2:30 AM, Jonathan Wakely wrote: This looks good - OK for trunk, thanks! Committed. Thanks! ChangeLog dates fixed by this patch. commit c3651cf0403b826414b8376bb29b4757530f4eec Author: redi Date: Tue Dec 6 12:48:54 2016 +000

Re: [v3 PATCH] Constrain optional's __constexpr_addressof in its return type, Use a constexpr addressof for optional, if available.

On 06/12/16 10:52 +0200, Ville Voutilainen wrote: The background for these is at https://stackoverflow.com/questions/40983822/cannot-use-a-constant-reference-of-experimentaloptional-when-using-clang-lib We use excessive trickery to constrain __constexpr_addressof in experimental::optional. That

Re: [C++/78252 PATCH] libiberty demangler crash with lambda (auto)

Ping? https://gcc.gnu.org/ml/gcc-patches/2016-11/msg03102.html Don't get confused by the chatter on https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70909. That defect mixes demangler recursion due to malformed symbols with recursion on well-formed ones. This patch fixes the well-formed lambda s

Re: [PATCH] [AArch64] Fix PR71112

On Wed, Nov 23, 2016 at 05:25:44AM +, Hurugalawadi, Naveen wrote: > Hi, > > Please find attached the patch that fixes PR71112. > > The current implementation that handles SYMBOL_SMALL_GOT_28K in > aarch64_load_symref_appropriately access the high part of RTX for Big-Endian > mode which result

[LRA] Fix ICE on pathological testcase

Hi, the compiler ICEs for SPARC 64-bit with LRA on the asm-subreg-1.c test: volatile unsigned short _const_32 [4] = {1,2,3,4}; void evas_common_convert_yuv_420p_601_rgba() { __asm__ __volatile__ ("" : : "X" (*_const_32)); } The issue is that combine merges back the 3 instructions necessary to

Re: [PATCH] Even more minimal reimplementation of errors.c within read-md.c

On 12/03/2016 12:07 AM, David Malcolm wrote: seen_error is already implemented in the "real" diagnostic subsystem, and would be a clash: we want a way to determine if read-md.c's implementation of error_at was called. Hence it seems simplest to conditionally add a copy of the "have_error" globa

Re: [PATCH] Add ASSERT_RTX_PTR_EQ

On 12/02/2016 09:24 PM, David Malcolm wrote: gcc/ChangeLog: * selftest-rtl.c (selftest::assert_rtx_ptr_eq_at): New function. * selftest-rtl.h (ASSERT_RTX_PTR_EQ): New macro. Ok. Bernd

Re: [PATCH] libstdc++: Improve code generation for atomic reference counting

I missed this patch until today and have only just seen it, sorry. On 09/11/16 23:26 +0200, Pauli wrote: Atomic reference counting generates pessimistic code in platforms where builtin atomics could optimize code for following branch with subtract instruction. Which targets are affected? To

Re: Default associative containers constructors/destructor/assignment

On 20/11/16 19:14 +0100, François Dumont wrote: Talking about _M_color I just realize that move semantic doesn't copy _M_color. Shouldn't we capture it along with all the other _M_header information ? Is it needed? I think the current code does the right thing, doesn't it? I'd prefer not to ch

Re: [Patches] Add variant constexpr support for visit, comparisons and get

On Tue, Dec 6, 2016 at 2:30 AM, Jonathan Wakely wrote: > This looks good - OK for trunk, thanks! Committed. Thanks! -- Regards, Tim Shen

Re: [PATCH PR78691]Require integral type for pattern ((convert1 (minmax ((convert2 (x) c)))) -> minmax (x c))

On Tue, Dec 6, 2016 at 12:02 PM, Bin Cheng wrote: > Hi, > This patch fixes ICE reported by PR78691, it adds requirement of integral > type for the outer > expression of pattern ((convert1 (minmax ((convert2 (x) c -> minmax (x > c)). > Test case checked on ppc, bootstrap and test on x86_64 on

Re: [PATCH, GCC/ARM, gcc-5/6-branch, ping] Fix PR77904: callee-saved register trashed when clobbering sp

Ping? Best regards, Thomas On 30/11/16 10:44, Thomas Preudhomme wrote: Sorry, the bug cannot be reproduced on gcc-5-branch so it's probably better to only do a backport to gcc-6-branch. Ok for a backport to gcc-6-branch? Best regards, Thomas On 30/11/16 10:42, Thomas Preudhomme wrote: Hi,

Re: [PATCH, GCC/ARM, gcc-5/6-branch, ping] Fix PR77933: stack corruption on ARM when using high registers and lr

Ping? Best regards, Thomas On 30/11/16 09:50, Thomas Preudhomme wrote: Hi, Is this ok to backport to gcc-5-branch and gcc-6-branch? Patch applies cleanly (patches attached for reference). 2016-11-17 Thomas Preud'homme Backport from mainline 2016-11-17 Thomas Preud'homme

Re: [PATCH, GCC/ARM, gcc-5/6-branch, ping] Fix ICE when compiling empty FIQ interrupt handler in ARM mode

On 06/12/16 11:36, Thomas Preudhomme wrote: Ping? Best regards, Ok if bootstrap and testing on those branches doesn't reveal any issues. Thanks, Kyrill Thomas On 30/11/16 10:20, Thomas Preudhomme wrote: Hi, Is this ok to backport this fix together with its follow-up testcase fix to gcc-

Re: [PATCH, GCC/ARM, gcc-5/6-branch, ping] Fix ICE when compiling empty FIQ interrupt handler in ARM mode

Ping? Best regards, Thomas On 30/11/16 10:20, Thomas Preudhomme wrote: Hi, Is this ok to backport this fix together with its follow-up testcase fix to gcc-5-branch and gcc-6-branch? Both patches apply cleanly (patches attached for reference). 2016-11-30 Thomas Preud'homme Backport f

Re: [PATCH, GCC/ARM 2/2, ping3] Allow combination of aprofile and rmprofile multilibs

Ping? *** gcc/ChangeLog *** 2016-10-03 Thomas Preud'homme * config.gcc: Allow combinations of aprofile and rmprofile values for --with-multilib-list. * config/arm/t-multilib: New file. * config/arm/t-aprofile: Remove initialization of MULTILIB_* variab

Re: [PATCH] Add noexcept to various basic_string string operations

On 06/12/16 06:05 -0500, Tim Song wrote: On Tue, Dec 6, 2016 at 6:00 AM, Jonathan Wakely wrote: Oh, but if you mean what the standard should say, my issue submission proposed "Throws: Nothing." for the ones with a narrow contract. It should be in the issue list soon, but I only sent it yesterd

Re: [PATCH] Add noexcept to various basic_string string operations

On Tue, Dec 6, 2016 at 6:00 AM, Jonathan Wakely wrote: > Oh, but if you mean what the standard should say, my issue submission > proposed "Throws: Nothing." for the ones with a narrow contract. It > should be in the issue list soon, but I only sent it yesterday. > Yes, I was talking about the st

Re: [Aarch64][PATCH] Fix gcc.dg/zero_bits_compound-2.c for aarch64

Hi Michael, On 6 December 2016 at 01:46, Michael Collison wrote: > This patches fixes a regression in gcc.dg/zero_bits_compound-2.c. A recent > patch (https://gcc.gnu.org/ml/gcc-patches/2016-11/msg02392.html) > to the aarch64 backend improved generation for 'and' instructions with > constants.

[PATCH PR78691]Require integral type for pattern ((convert1 (minmax ((convert2 (x) c)))) -> minmax (x c))

Hi, This patch fixes ICE reported by PR78691, it adds requirement of integral type for the outer expression of pattern ((convert1 (minmax ((convert2 (x) c -> minmax (x c)). Test case checked on ppc, bootstrap and test on x86_64 ongoing, is it OK if no new failure? Thanks, bin 2016-12-06 Bi

Re: [PATCH] Add noexcept to various basic_string string operations

On 06/12/16 10:59 +, Jonathan Wakely wrote: On 06/12/16 05:55 -0500, Tim Song wrote: On Tue, Dec 6, 2016 at 5:43 AM, Jonathan Wakely wrote: None of these functions can throw, so we should mark them as such. I've reported this as a defect against C++17, because they should have been made no

Re: [PATCH] Add noexcept to various basic_string string operations

On 06/12/16 05:55 -0500, Tim Song wrote: On Tue, Dec 6, 2016 at 5:43 AM, Jonathan Wakely wrote: None of these functions can throw, so we should mark them as such. I've reported this as a defect against C++17, because they should have been made noexcept after the application of https://wg21.link

Re: [PATCH] Add noexcept to various basic_string string operations

On Tue, Dec 6, 2016 at 5:43 AM, Jonathan Wakely wrote: > None of these functions can throw, so we should mark them as such. > I've reported this as a defect against C++17, because they should have > been made noexcept after the application of https://wg21.link/p0254r2 Surely the const _CharT* var

[PATCH] Add noexcept to various basic_string string operations

None of these functions can throw, so we should mark them as such. I've reported this as a defect against C++17, because they should have been made noexcept after the application of https://wg21.link/p0254r2 * include/bits/basic_string.h (basic_string::find, basic_string::rfind) (

Re: [Patches] Add variant constexpr support for visit, comparisons and get

On 02/12/16 19:14 -0800, Tim Shen wrote: On Wed, Nov 30, 2016 at 8:27 AM, Jonathan Wakely wrote: On 26/11/16 21:38 -0800, Tim Shen wrote: This 4-patch series contains the following in order: a.diff: Remove uses-allocator ctors. They are going away, and removing it reduces the maintenance burd

Re: [PATCH] Added noexcept on constructors

On 05/12/16 15:34 -0600, Aditya Kumar wrote: Thanks for the feedback. Updated patch is below. The noexcept on definition and the declaration of constructors _Sp_locker do not match. Thanks for the patch (and thanks, Ville, for reviewing it). I'll commit this today.

Re: [PR middle-end/78566] Fix uninit regressions caused by previous -Wmaybe-uninit change

On 12/05/2016 11:07 PM, Jeff Law wrote: On 11/29/2016 09:33 AM, Aldy Hernandez wrote: This fixes the gcc.dg/uninit-pred-6* failures I seem to have caused on some non x86 platforms. Sorry for the delay. The problem is that my fix for PR61409 had the logic backwards. I was proving that all the u

Re: [tree-tailcall] Check if function returns it's argument

On Tue, 6 Dec 2016, Richard Biener wrote: > On Mon, 5 Dec 2016, Jeff Law wrote: > > > On 12/02/2016 01:33 AM, Richard Biener wrote: > > > > The LHS on the assignment makes it easier to identify when a tail call > > > > is > > > > possible. It's not needed for correctness. Not having the LHS on

Re: [PATCH] Fix ICE due to IPA-VRP (PR tree-optimization/78681)

On 6 December 2016 at 14:50, Richard Biener wrote: > On Tue, 6 Dec 2016, Jakub Jelinek wrote: > >> On Tue, Dec 06, 2016 at 09:36:55AM +0100, Richard Biener wrote: >> > > As shown on the testcase, with K&R definitions and fn prototypes with >> > > promoted types, we can end up computing caller's va

Re: [PATCH] Fix ICE due to IPA-VRP (PR tree-optimization/78681)

On Tue, 6 Dec 2016, Jakub Jelinek wrote: > On Tue, Dec 06, 2016 at 09:36:55AM +0100, Richard Biener wrote: > > > As shown on the testcase, with K&R definitions and fn prototypes with > > > promoted types, we can end up computing caller's value ranges in wider > > > type than the parameter actually

Re: [PATCH] Fix ICE due to IPA-VRP (PR tree-optimization/78681)

On Tue, Dec 06, 2016 at 09:36:55AM +0100, Richard Biener wrote: > > As shown on the testcase, with K&R definitions and fn prototypes with > > promoted types, we can end up computing caller's value ranges in wider > > type than the parameter actually has in the function. > > The problem with that is

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