Fix fir PR71696 in Libiberty Demangler (6)

Hi, The attached patch fixes the stack overflow in the demangler due to cycles in the references of “remembered” mangled types (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71696). The methods demangle_signature and do_arg in cplus-dem.c allow to “remember” mangled type names that can later be

Re: [AArch64] - feedback on the approach followed for vulcan scheduler

On Wed, Jun 29, 2016 at 9:59 AM, Virendra Pathak wrote: > Hi gcc-patches group, > > I am working on adding vulcan.md (machine description) for vulcan cpu > in the aarch64 port. However, before proposing the final patch, I would like > the basic approach to be reviewed by you all (as changes are th

Re: [Fortran] Help with STAT= attribute in coarray reference

Dear Mikael, thanks for your review and for the test. The attached patch, built and regtested for x86_64-pc-linux-gnu, addresses all the suggestions. The next patch will change the documentation related to the caf_get and caf_send functions and will add support for STAT= to the sendget function.

Re: [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006

And yes, the reply was to the other patch in play (vector extract). I think it is time to go home for the night, and I will commit the fix for PR 71677 tomorrow. :-) -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone:

Re: [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006

On Wed, Jun 29, 2016 at 06:06:04PM -0500, Segher Boessenkool wrote: > On Wed, Jun 29, 2016 at 05:58:37PM -0400, Michael Meissner wrote: > > Assuming there are no regressions in power7, are these patches ok to > > install in > > the trunk, and backport to GCC 6.2 after a burn-in period? > > Yes, t

[PATCH] gcc/arc: Avoid add_s REG,REG,pcl on ARCv2 targets

The ARCv2 targets don't support add_s REG,REG,pcl like earlier ARC targets did. This instruction format is used when generating case jump tables. This commit updates the code so that ARCv2 targets avoid the unsupported instruction. This does mean the code is slightly longer on ARCv2, so the inst

Re: [PATCH,rs6000] Fix error in Power9 code generation for vpermr instruction

On Wed, Jun 29, 2016 at 03:35:28PM -0600, Kelvin Nilsen wrote: > Testing on a Power9 simulator revealed an error in the code emitted for > the *altivec_vpermr__internal define_insn pattern. Two of the > operands of the vpermr operand had been emitted in wrong order. This > patch corrects the err

Re: [PATCH 0/9] separate shrink-wrapping

On Thu, Jun 30, 2016 at 01:03:17AM +0200, Bernd Schmidt wrote: > On 06/08/2016 07:26 PM, Segher Boessenkool wrote: > >One thing I should try is put a USE of the saved registers at such > >exits, maybe that helps those passes that now delete frame restores > >to not do that. > > Have you had a chan

Re: [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006

On Wed, Jun 29, 2016 at 05:58:37PM -0400, Michael Meissner wrote: > Assuming there are no regressions in power7, are these patches ok to install > in > the trunk, and backport to GCC 6.2 after a burn-in period? Yes, this is fine, thanks for the changes. Okay for 6 too. > * config/rs6000/c

Re: [PATCH 0/9] separate shrink-wrapping

On 06/08/2016 07:26 PM, Segher Boessenkool wrote: One thing I should try is put a USE of the saved registers at such exits, maybe that helps those passes that now delete frame restores to not do that. Have you had a chance to try this? Bernd

Re: [PATCH] Offer suggestions for misspelled --param names.

On Mon, 27 Jun 2016, David Malcolm wrote: > Another use of spellcheck.{c|h}, this time for --param. > > Successfully bootstrapped®retested on x86_64-pc-linux-gnu; > adds 4 PASS results to gcc.sum. > > OK for trunk? OK. -- Joseph S. Myers jos...@codesourcery.com

Re: [PATCH] Fix bogus option suggestions for RejectNegative options (PR driver/71651)

On Fri, 24 Jun 2016, David Malcolm wrote: > PR driver/71651 identifies an issue where the driver can make > nonsensical suggestions for options flagged as RejectNegative: > > $ gcc -fno-stack-protector-explicit > gcc: error: unrecognized command line option '-fno-stack-protector-explicit'; > d

Re: [PATCH], Add PowerPC ISA 3.0 vector extract support

On Wed, Jun 29, 2016 at 05:20:26PM -0500, Segher Boessenkool wrote: > On Wed, Jun 29, 2016 at 03:33:24PM -0400, Michael Meissner wrote: > > Is it ok to install in the trunk? > > See comments below. Okay with that taken care of. > > > Ideally, I would like to also install it on the GCC 6.2 branch

Re: [PATCH], Add PowerPC ISA 3.0 vector extract support

On Wed, Jun 29, 2016 at 03:33:24PM -0400, Michael Meissner wrote: > Is it ok to install in the trunk? See comments below. Okay with that taken care of. > Ideally, I would like to also install it on the GCC 6.2 branch. Note, it > depends on the June 15th changes to allow DImode into Altivec regi

[patch] Get rid of stack trampolines for nested functions

Hi, this patch implements generic support for the elimination of stack trampolines and, consequently, of the need to make the stack executable when pointers to nested functions are used. That's done on a per-language and per-target basis (i.e. there is 1 language hook and 1 target hook to para

Re: [PATCH] Fix source locations of bad enum values (PR c/71610 and PR c/71613)

On Wed, 22 Jun 2016, David Malcolm wrote: > PR c/71613 identifies a problem where we fail to report this enum: > > enum { e1 = LLONG_MIN }; > > with -pedantic, due to LLONG_MIN being inside a system header. > > This patch updates the C and C++ frontends to use the location of the > name as th

[PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006

Sigh, I forgot to attach the patch, and I also used the wrong bug number in my previous patch. As we discussed in the patch review, there were some issues with using %Y for the ISA 3.0 instructions LXSD and STXSD. I have rewritten the patch so that we have a new memory constraint (%wY) that expli

Re: Improve insert/emplace robustness to self insertion

On 29/06/16 21:43 +0200, François Dumont wrote: I tried those changes too but started having failing tests in vector/ext_pointer so prefer to not touch that for the moment. I think the compilation error was coming from the change of begin() + (__position - cbegin()) into begin() + __n because o

Re: [PATCH, rs6000] Use direct moves for __builtin_signbit for 128-bit floating-point

Hi, On Tue, Jun 28, 2016 at 04:44:08PM -0500, Bill Schmidt wrote: > +void > +rs6000_split_signbit (rtx dest, rtx src) > +{ > + machine_mode d_mode = GET_MODE (dest); > + machine_mode s_mode = GET_MODE (src); > + rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest); > + rtx shif

[PATCH,rs6000] Fix error in Power9 code generation for vpermr instruction

Testing on a Power9 simulator revealed an error in the code emitted for the *altivec_vpermr__internal define_insn pattern. Two of the operands of the vpermr operand had been emitted in wrong order. This patch corrects the error. Testing of this patch on a Power9 simulator demonstrates that thi

Re: [Patch, lra] PR70751, correct the cost for spilling non-pseudo into memory

Andreas Krebbel writes: > On 06/28/2016 04:16 PM, Jiong Wang wrote: > ... >> So my first impression is TARGET_LEGITIMATE_ADDRESS_P on s390 do need a >> fix here. The following draft patch fix this, my fix may be in >> correct as normally we will allow illegal constant offset if it's >> associated

Re: Improve insert/emplace robustness to self insertion

On 29/06/16 21:36 +0100, Jonathan Wakely wrote: On 29/06/16 21:43 +0200, François Dumont wrote: As asked here is now a patch to only fix the robustness issue. The consequence is that it is reverting the latest optimization as, without smart algo, we always need to do a copy to protect against

Re: [AArch64] ARMv8.2 command line and feature macros support

On Mon, Jun 27, 2016 at 7:58 AM, Jiong Wang wrote: > On 07/06/16 09:46, Jiong Wang wrote: >> >> 2016-06-07 Matthew Wahab >> Jiong Wang >> >> * config/aarch64/aarch64-arches.def: Add "armv8.2-a". >> * config/aarch64/aarch64.h (AARCH64_FL_V8_2): New. >> (AARCH64_

Re: [RFC] [2/2] divmod transform: override expand_divmod_libfunc for ARM and add test-cases

ping * 2 https://gcc.gnu.org/ml/gcc-patches/2016-05/msg02008.html Thanks, Prathamesh On 7 June 2016 at 13:56, Prathamesh Kulkarni wrote: > ping https://gcc.gnu.org/ml/gcc-patches/2016-05/msg02008.html > > Thanks, > Prathamesh > > On 25 May 2016 at 18:19, Prathamesh Kulkarni > wrote: >> On 23 Ma

Re: [PATCH] tree-ssa-strlen improvements (PR tree-optimization/71625)

On 29 June 2016 at 15:20, Jakub Jelinek wrote: > On Wed, Jun 29, 2016 at 03:11:07PM +0200, Christophe Lyon wrote: >> This causes GCC builds failures on arm-linux* targets, while building glibc: >> >> ns_print.c: In function 'ns_sprintrrf': >> ns_print.c:94:1: internal compiler error: in get_stridx

Re: [PATCH, libstdc++/testsuite, ping2] 29_atomics/atomic/65913.cc: require atomic-builtins rather than specific target

On 29/06/16 13:49 -0700, Mike Stump wrote: On Thursday 26 May 2016 14:00:55 Thomas Preudhomme wrote: [Sorry for the large recipient list, I wasn't sure who of C++ and x86 maintainers should approve this] Hi, 29_atomics/atomic/65913.cc test in libstdc++ is a runtime test that only rely on atomi

Re: [PATCH, libstdc++/testsuite, ping2] 29_atomics/atomic/65913.cc: require atomic-builtins rather than specific target

On 29/06/16 13:49 -0700, Mike Stump wrote: Please include the libstdc++ list, they don't all read the other list. And the documentation clearly says (in two places) that all libstdc++ patches must go to the libstdc++ list.

Re: [PATCH, libstdc++/testsuite, ping2] 29_atomics/atomic/65913.cc: require atomic-builtins rather than specific target

Please include the libstdc++ list, they don't all read the other list. Also, the patch or a link to the patch helps the reviewers find the patch, otherwise even finding the patch to review can be hard for some folks. Seems reasonable to me, though, I'd normally punt to the atomic people. > On

Re: [PATCH], Add PowerPC ISA 3.0 vector extract support

On Wed, Jun 29, 2016 at 03:33:24PM -0400, Michael Meissner wrote: > This patch adds support to generate the ISA 3.0 VEXTRACTUB, VEXTRACTUH, and > XXEXTRACTUW instructions to extract a constant element from the small vector > integer types. I also added support to generate STXSIWX if a DImode is in

Re: Improve insert/emplace robustness to self insertion

On 29/06/16 21:43 +0200, François Dumont wrote: As asked here is now a patch to only fix the robustness issue. The consequence is that it is reverting the latest optimization as, without smart algo, we always need to do a copy to protect against insertion of values contained in the vector as sh

Re: Improve insert/emplace robustness to self insertion

On 29/06/2016 11:10, Jonathan Wakely wrote: On 28/06/16 21:59 +0200, François Dumont wrote: @@ -303,16 +301,20 @@ _GLIBCXX_BEGIN_NAMESPACE_CONTAINER emplace(const_iterator __position, _Args&&... __args) { const size_type __n = __position - begin(); It looks like this should use

Re: [PATCH, AARCH64] add qdf24xx tuning structure

On 28 June 2016 at 10:21, Kyrill Tkachov wrote: > > On 28/06/16 02:03, Jim Wilson wrote: >> >> On Mon, Jun 13, 2016 at 3:01 AM, Kyrill Tkachov >> wrote: >>> >>> Hi Jim, >>> >>> On 10/06/16 23:48, Jim Wilson wrote: This adds a tuning structure for qdf24xx. This was tested with an a

[PATCH], Add PowerPC ISA 3.0 vector extract support

This patch adds support to generate the ISA 3.0 VEXTRACTUB, VEXTRACTUH, and XXEXTRACTUW instructions to extract a constant element from the small vector integer types. I also added support to generate STXSIWX if a DImode is in an Altivec register (which is needed for this patch when extracting cha

Re: [PATCH 1/2] gcc: Remove unneeded global flag.

* Jeff Law [2016-06-21 20:55:15 -0600]: > On 06/10/2016 10:56 AM, Andrew Burgess wrote: > > The global flag `user_defined_section_attribute' is set while parsing C > > code when the section attribute is encountered. The flag is set when > > anything has the section attribute applied to it, funct

Problem in cxx_fundamental_alignment_p?

I came across what I think is a bug in cxx_fundamental_alignment_p. User alignments are specified in units of bytes. This is documented, and we can also see the following in handle_aligned_attribute, for the case when we have no args: align_expr = size_int (ATTRIBUTE_ALIGNED_VALUE / BITS_PER

Re: [PATCH], Pr 71667, Fix PowerPC ISA 3.0 DImode Altivec load/store

On Wed, Jun 29, 2016 at 05:29:36PM +0100, Alan Hayward wrote: > Hi, > > This patch references the wrong bug. It should reference 71677 and not > 71667 > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71677 > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71667 > > > Thanks, > Alan. Whoops, yes y

[PATCH] Fix fold_binary RROTATE_EXPR opts (PR middle-end/71693)

Hi! This issue is latent on the trunk/6.2, fails with checking in 5.x/4.9. As usually in fold_*_loc, arg0/arg1 is STRIP_NOPS op0/op1, so might have incompatible type, so we need to convert it to the right type first before optimizing. Bootstrapped/regtested on x86_64-linux/i686-linux, ok everywhe

[PATCH][AArch64] Canonicalize Cortex core tunings

This patch sets the branch cost to the same most optimal setting for all Cortex cores, reducing codesize and improving performance due to using more CSEL instructions. Set the autoprefetcher model in Cortex-A72 to weak like the others. Enable AES fusion in Cortex-A35. As a result generated code

[AArch64] - feedback on the approach followed for vulcan scheduler

Hi gcc-patches group, I am working on adding vulcan.md (machine description) for vulcan cpu in the aarch64 port. However, before proposing the final patch, I would like the basic approach to be reviewed by you all (as changes are there in aarch64.md) In vulcan, a (load/store) instruction could be

[Patch, Fortran, 71623, v1][5/6/7 Regression] Segfault when allocating deferred-length characters to size of a pointer

Hi all, the attached patch fixes the regression at least for trunk (I haven't checked the others, but for 6 it should do either, 5 may need a little bit more work). The issue here is that computing the typespec involved code in se.pre that was not merged to the parent block. Bootstrapped and regt

Re: [PATCH, rs6000] Enable some existing __float128 tests for powerpc64*

On Tue, 28 Jun 2016, Bill Schmidt wrote: > -/* { dg-do compile { target ia64-*-* i?86-*-* x86_64-*-* } } */ > +/* { dg-do compile { target ia64-*-* i?86-*-* x86_64-*-* powerpc64*-*-* } } > */ > /* { dg-options "-pedantic" } */ > +/* { dg-additional-options "-mfloat128 -mvsx" { target powerpc64*-

Re: [PATCH][AArch64] Increase code alignment

On 06/29/16 07:59, James Greenhalgh wrote: On Tue, Jun 21, 2016 at 02:39:23PM +0100, Wilco Dijkstra wrote: ping From: Wilco Dijkstra Sent: 03 June 2016 11:51 To: GCC Patches Cc: nd; philipp.toms...@theobroma-systems.com; pins...@gmail.com; jim.wil...@linaro.org; benedikt.hu...@theobroma-syste

Re: [PATCH, libstdc++/testsuite, ping2] 29_atomics/atomic/65913.cc: require atomic-builtins rather than specific target

Ping? Best regards, Thomas On Thursday 02 June 2016 14:34:03 Thomas Preudhomme wrote: > Ping? > > On Thursday 26 May 2016 14:00:55 Thomas Preudhomme wrote: > > [Sorry for the large recipient list, I wasn't sure who of C++ and x86 > > maintainers should approve this] > > > > Hi, > > > > 29_ato

Re: [PATCH], Pr 71667, Fix PowerPC ISA 3.0 DImode Altivec load/store

Hi, This patch references the wrong bug. It should reference 71677 and not 71667 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71677 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71667 Thanks, Alan. As we discussed in the patch review, there were some issues with using %Y for the ISA 3.0 instr

Re: [PATCH PR70729] The second part of patch.

Hi! On Tue, 28 Jun 2016 18:50:37 +0300, Yuri Rumyantsev wrote: > Here is the second part of patch to improve loop invariant code motion > for loop marked with pragma omp simd. > > Bootstrapping and regression testing did not show any new failures. That got committed in r237844. In my testing,

Re: Fix for PR70909 in Libiberty Demangler (4)

On 06/29/2016 08:43 AM, Marcel Böhme wrote: > Hi Jason, > > These test cases are generated by fuzzing which produces a lot of nonsensical > input data. > I think, "Garbage In, Garbage Out" is quite applicable here. > With the patch at least it doesn’t crash and fixes the vulnerability. Note tha

Re: [PATCH,openacc] check for compatible loop parallelism with acc routine calls

On 06/29/2016 07:11 AM, Thomas Schwinge wrote: > Cesar, I have not yet fully digested this, but do I understand right that > you're really fixing two issues here, that are related (OpenACC routines) > but still can be addressed independently of each other? Do I understand > right that the first o

Re: Minor tweak to df_note_bb_compute

> This simply prevents valgrind from complaining about an invalid read when > pass_free_cfg::execute calls df_analyze for targets with delay slots, > because var_location instructions are present in the RTL stream at this > point. > > Tested on x86_64-suse-linux, applied on the mainline as obvious

[C++ RFC/Patch] PR c++/71665

Hi, we have this pretty old regression where we ICE on the invalid snippet: class A { int f (); enum { a = f }; }; in fact we hit the gcc_checking_assert in cxx_eval_constant_expression case COMPONENT_REF: if (is_overloaded_fn (t)) { /* We can only get here in checking

Re: [PATCH,openacc] check for compatible loop parallelism with acc routine calls

On Wed, Jun 29, 2016 at 04:11:31PM +0200, Thomas Schwinge wrote: > > >> Actually, I relaxed non-acc routines by excluding > > >> calls to builtin functions, including those prefixed with _gfortran_. > > >> Nvptx does have a newlib c library, and it also has a subset of > > >> libgfortran. Still, th

Re: [PATCH 2/9] c-decl.c: add [cd]tors to c_struct_parse_info

On Wed, Jun 29, 2016 at 09:21:01AM -0400, David Malcolm wrote: > On Wed, 2016-06-29 at 08:26 -0400, tbsaunde+...@tbsaunde.org wrote: > > From: Trevor Saunders > > > > gcc/c/ChangeLog: > > I may be missing my coffee here but you mention adding a constructor in > the ChangeLog here: No, I think I

Re: [PATCH,openacc] check for compatible loop parallelism with acc routine calls

Hi! Cesar, I have not yet fully digested this, but do I understand right that you're really fixing two issues here, that are related (OpenACC routines) but still can be addressed independently of each other? Do I understand right that the first one, the "problems with acc routines [...] incorrect

[PATCH] Testcase for PR15256

noticed we have this fixed since GCC 6. Committed. Richard. 2016-06-29 Richard Biener PR middle-end/15256 * gcc.dg/tree-ssa/forwprop-34.c: New testcase. Index: gcc/testsuite/gcc.dg/tree-ssa/forwprop-34.c === **

Re: [PATCH 2/9] c-decl.c: add [cd]tors to c_struct_parse_info

On Wed, 2016-06-29 at 08:26 -0400, tbsaunde+...@tbsaunde.org wrote: > From: Trevor Saunders > > gcc/c/ChangeLog: I may be missing my coffee here but you mention adding a constructor in the ChangeLog here: > 2016-06-29 Trevor Saunders > > * c-decl.c (struct c_struct_parse_info): Add co

Re: [PATCH] tree-ssa-strlen improvements (PR tree-optimization/71625)

On Wed, Jun 29, 2016 at 03:11:07PM +0200, Christophe Lyon wrote: > This causes GCC builds failures on arm-linux* targets, while building glibc: > > ns_print.c: In function 'ns_sprintrrf': > ns_print.c:94:1: internal compiler error: in get_stridx_plus_constant, > at tree-ssa-strlen.c:680 > ns_spri

Re: [PATCH] tree-ssa-strlen improvements (PR tree-optimization/71625)

On 28 June 2016 at 16:23, Jakub Jelinek wrote: > Hi! > > This is just first small step towards this PR. > It brings the ADDR_EXPR of DECL_P bases roughly on the same level as > SSA_NAMEs pointers - so get_stridx_plus_constant works for them, and > more importantly, before this patch there was a ve

[Ada] translate System.Address as void pointer for convention C

The natural idiom is to import/export objects whose type is void pointer in C with the System.Address type in Ada, for example the malloc & memcpy routines. However System.Address is (almost) always a scalar type in Ada so there is a discrepancy between the C side (pointer) and the Ada side (inte

Re: [PATCH][AArch64] Increase code alignment

On Tue, Jun 21, 2016 at 02:39:23PM +0100, Wilco Dijkstra wrote: > > ping > > > From: Wilco Dijkstra > Sent: 03 June 2016 11:51 > To: GCC Patches > Cc: nd; philipp.toms...@theobroma-systems.com; pins...@gmail.com; > jim.wil...@linaro.org; benedikt.hu...@theobroma-systems.com; Evandro Menezes > S

[PATCH 6/9] ree.c: use auto_vec in ext_state

From: Trevor Saunders gcc/ChangeLog: 2016-06-29 Trevor Saunders * ree.c (struct ext_state): Make type of members auto_vec. (find_and_remove_re): Adjust. --- gcc/ree.c | 19 ++- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/gcc/ree.c b/gcc/ree

[PATCH 9/9] remove unnecessary calls to vec::release

From: Trevor Saunders There's no point in calling release () on an auto_vec just before it goes out of scope. gcc/ChangeLog: 2016-06-29 Trevor Saunders * tree-data-ref.c (find_data_references_in_stmt): Remove unnecessary call to vec::release. (graphite_find_data_refe

[PATCH 8/9] use auto_vec for more local variables

From: Trevor Saunders gcc/c/ChangeLog: 2016-06-29 Trevor Saunders * c-parser.c (c_parser_generic_selection): Make type of variable auto_vec. (c_parser_omp_declare_simd): Likewise. gcc/ChangeLog: 2016-06-29 Trevor Saunders * cfgexpand.c (expand_used_vars)

[PATCH 4/9] ipa.c: remove static_{ctors,dtors} globals

From: Trevor Saunders gcc/ChangeLog: 2016-06-29 Trevor Saunders * ipa.c (record_cdtor_fn): Adjust. (build_cdtor_fns): Likewise. (ipa_cdtor_merge): Make static_ctors and static_dtors local variables. --- gcc/ipa.c | 37 + 1

[PATCH 3/9] genextract.c: add [cd]tors to accum_extract

From: Trevor Saunders gcc/ChangeLog: 2016-06-29 Trevor Saunders * genextract.c (struct accum_extract): Add constructor and make members auto_vec. (gen_insn): Adjust. --- gcc/genextract.c | 23 +++ 1 file changed, 7 insertions(+), 16 deletions(-)

[PATCH 7/9] tree-ssa-sccvn.c: use auto_vec for sccvn_dom_walker::cond_stack

From: Trevor Saunders gcc/ChangeLog: 2016-06-29 Trevor Saunders * tree-ssa-sccvn.c (sccvn_dom_walker::~sccvn_dom_walker): remove. (sccvn_dom_walker): make cond_stack an auto_vec. --- gcc/tree-ssa-sccvn.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/

[PATCH 2/9] c-decl.c: add [cd]tors to c_struct_parse_info

From: Trevor Saunders gcc/c/ChangeLog: 2016-06-29 Trevor Saunders * c-decl.c (struct c_struct_parse_info): Add constructor and change member types from vec to auto_vec. (start_struct): Adjust. (finish_struct): Likewise. --- gcc/c/c-decl.c | 16 +--

[PATCH 5/9] cfgexpand.c: use auto_vec in stack_vars_data

From: Trevor Saunders gcc/ChangeLog: 2016-06-29 Trevor Saunders * cfgexpand.c (struct stack_vars_data): Make type of fields auto_vec. (expand_used_vars): Adjust. --- gcc/cfgexpand.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/gcc/cfge

[PATCH 1/9] tree.c: add [cd]tors to free_lang_data_d

From: Trevor Saunders gcc/ChangeLog: 2016-06-29 Trevor Saunders * tree.c (struct free_lang_data_d): Add constructor and change types of members to ones that automatically manage resources. (fld_worklist_push): Adjust. (find_decls_types): Likewise. (fin

[PATCH 0/9] remove some manual memory management

From: Trevor Saunders Hi, This is just a bunch of adding constructors and destructors and switching to use auto_vec more. patches individually bootstrapped and regtested on x86_64-linux-gnu, ok? Trev Trevor Saunders (9): tree.c: add [cd]tors to free_lang_data_d c-decl.c: add [cd]tors to c

[PATCH][C++] C++ bitfield memory model for as-base classes

Currently as-base classes lack DECL_BIT_FIELD_REPRESENTATIVEs which means RTL expansion doesn't honor the C++ memory model for bitfields in them thus for the following testcase struct B { B() {} int x; int a : 6; int b : 6; int c : 6; }; struct C : B { char d; }; C c; i

Re: [PATCH] Generate more effective one-operand permutation instruction for knl.

Hello, On 29 Jun 13:12, Yuri Rumyantsev wrote: > Hi All, > > Here is a simple patch which generates on-operand vperm instructions > introduced in knl. > Using this patch we got +5% speed-up on one important benchmark. > > Bootstrapping and regression testing did not show any new failures. > Is it

[PATCH, www, obvious] Fix typo in htdocs/develop.html

Hello. This looks as typo, I'm going to install the patch. Index: htdocs/develop.html === RCS file: /cvs/gcc/wwwdocs/htdocs/develop.html,v retrieving revision 1.165 diff --unified -r1.165 develop.html --- htdocs/develop.html 3 Jun 20

Re: [AArch64] ARMv8.2 command line and feature macros support

Richard Earnshaw (lists) writes: > On 29/06/16 09:43, James Greenhalgh wrote: >> On Mon, Jun 27, 2016 at 03:58:00PM +0100, Jiong Wang wrote: >>> >>> The permissible values for @var{arch} are @samp{armv8-a}, >>> -@samp{armv8.1-a} or @var{native}. >>> +@samp{armv8.1-a}, @samp{armv8.2-a} or @var{

Re: [PATCH] Mark -fstack-protect as optimization flag (PR middle-end/71585)

On Wed, Jun 29, 2016 at 12:29 PM, Martin Liška wrote: > On 06/29/2016 12:27 PM, Martin Liška wrote: >> On 06/29/2016 11:12 AM, Richard Biener wrote: >>> So what was your original reason to pursue this? >>> >>> Richard. >> >> Agree with you that handling the option during inlining is a bit overkill

Re: [PATCH/AARCH64] Add rtx_costs routine for vulcan.

Hi James, > Did you see those patches, and did you consider whether there would be a > benefit to doing the same for Vulcan? No. I have not studied those patches yet. Currently I am working on adding vulcan scheduler as a next patch. Kindly advise on the following: Could this patch be merged now (

Re: Determine more IVs to be non-overflowing

Hi, after some exprimentation I am re-testing the following version. wide_int variant seemed ugly. Here I simply cap nit to be in range of the type and then the widest_int calculation ought to be safe. What do you think? Perhaps I need to use signs of STEP and BASE type just in the case some cas

Re: [PATCH][AArch64] Fix some scan-assembler tests for -mabi=ilp32

On 29/06/16 11:47, James Greenhalgh wrote: > On Wed, Jun 29, 2016 at 11:40:13AM +0100, Kyrill Tkachov wrote: >> Hi all, >> >> I notice these scan-assembler tests fail when testing -mabi=ilp32 because the >> 64-bit operation that they expect doesn't happen on the 32-bit long types in >> that configu

Re: [PATCH][AArch64] Fix some scan-assembler tests for -mabi=ilp32

On Wed, Jun 29, 2016 at 11:40:13AM +0100, Kyrill Tkachov wrote: > Hi all, > > I notice these scan-assembler tests fail when testing -mabi=ilp32 because the > 64-bit operation that they expect doesn't happen on the 32-bit long types in > that configuration. > > The easy fix is to change the 'long'

Re: [PATCH][AArch64] Fix some scan-assembler tests for -mabi=ilp32

On 29/06/16 11:40, Kyrill Tkachov wrote: > Hi all, > > I notice these scan-assembler tests fail when testing -mabi=ilp32 > because the 64-bit operation that they > expect doesn't happen on the 32-bit long types in that configuration. > > The easy fix is to change the 'long' types to be 'long long

Re: [PATCH/AARCH64] Add rtx_costs routine for vulcan.

On Thu, Jun 23, 2016 at 02:45:21PM +0530, Virendra Pathak wrote: > Hi gcc-patches group, > > Please find the patch for adding rtx_costs routine for vulcan cpu. > > Tested with compiling cross aarch64-linux-gcc , bootstrapped native > aarch64-unknown-linux-gnu > and make check (gcc). No new regres

[PATCH][AArch64] Fix some scan-assembler tests for -mabi=ilp32

Hi all, I notice these scan-assembler tests fail when testing -mabi=ilp32 because the 64-bit operation that they expect doesn't happen on the 32-bit long types in that configuration. The easy fix is to change the 'long' types to be 'long long' so that they are always 64-bit. With this patch th

Re: [PATCH] Mark -fstack-protect as optimization flag (PR middle-end/71585)

On 06/29/2016 12:27 PM, Martin Liška wrote: > On 06/29/2016 11:12 AM, Richard Biener wrote: >> So what was your original reason to pursue this? >> >> Richard. > > Agree with you that handling the option during inlining is a bit overkill. > I can live with just marking the option as Optimize, which

Re: [AArch64] ARMv8.2 command line and feature macros support

On 29/06/16 09:43, James Greenhalgh wrote: > On Mon, Jun 27, 2016 at 03:58:00PM +0100, Jiong Wang wrote: >> On 07/06/16 09:46, Jiong Wang wrote: >>> 2016-06-07 Matthew Wahab >>>Jiong Wang >>> >>>* config/aarch64/aarch64-arches.def: Add "armv8.2-a". >>>* config/aarch64/a

Re: [PATCH] Mark -fstack-protect as optimization flag (PR middle-end/71585)

On 06/29/2016 11:12 AM, Richard Biener wrote: > So what was your original reason to pursue this? > > Richard. Agree with you that handling the option during inlining is a bit overkill. I can live with just marking the option as Optimize, which will fix reported PR. Sending simplified version 2.

Re: Improve insert/emplace robustness to self insertion

Hi, On 29/06/2016 12:07, Jonathan Wakely wrote: On 29/06/16 11:35 +0200, Paolo Carlini wrote: Hi, On 29/06/2016 10:57, Jonathan Wakely wrote: On 28/06/16 21:59 +0200, François Dumont wrote: + if (_M_data_ptr(__position.base()) <= __ptr + && __ptr < _M_data_ptr(this->_M_impl._M_fini

[PATCH] Generate more effective one-operand permutation instruction for knl.

Hi All, Here is a simple patch which generates on-operand vperm instructions introduced in knl. Using this patch we got +5% speed-up on one important benchmark. Bootstrapping and regression testing did not show any new failures. Is it OK for trunk? ChangeLog: 2016-06-29 Yuri Rumyantsev * con

Re: Improve insert/emplace robustness to self insertion

On 29/06/16 11:35 +0200, Paolo Carlini wrote: Hi, On 29/06/2016 10:57, Jonathan Wakely wrote: On 28/06/16 21:59 +0200, François Dumont wrote: + if (_M_data_ptr(__position.base()) <= __ptr + && __ptr < _M_data_ptr(this->_M_impl._M_finish - 1)) This is undefined behaviour. If the obj

Re: Improve insert/emplace robustness to self insertion

Hi, On 29/06/2016 10:57, Jonathan Wakely wrote: On 28/06/16 21:59 +0200, François Dumont wrote: + if (_M_data_ptr(__position.base()) <= __ptr + && __ptr < _M_data_ptr(this->_M_impl._M_finish - 1)) This is undefined behaviour. If the object is not contained in the vector then you can

Re: Improve diagnostic messages of "#pragma omp cancel", "#pragma omp cancellation point" parsing (was: Clarify PRAGMA_OACC_* and PRAGMA_OMP_*)

Hi! On Tue, 28 Jun 2016 14:25:28 +0200, Jakub Jelinek wrote: > On Tue, Jun 28, 2016 at 02:19:13PM +0200, Thomas Schwinge wrote: > > [...] > > > > OK for trunk? > > This LGTM if you tweak it to apply without the previous patch or with just > a patch for PRAGMA_OMP_DECLARE. > > Thanks. Committe

Rename PRAGMA_OMP_DECLARE_REDUCTION to PRAGMA_OMP_DECLARE (was: Clarify PRAGMA_OACC_* and PRAGMA_OMP_*)

Hi! On Tue, 28 Jun 2016 14:20:26 +0200, Jakub Jelinek wrote: > On Tue, Jun 28, 2016 at 02:13:24PM +0200, Thomas Schwinge wrote: > > Looking at how OpenMP declare simd is handled in the C++ front end, I ran > > into it being parsed for PRAGMA_OMP_DECLARE_REDUCTION, which got me > > confused. OK t

[PING, two months] libgomp: In OpenACC testing, cycle though $offload_targets, and by default only build for the offload target that we're actually going to test

Hi! Ping... Now waiting for review for two months. Quoting my latest commentary from : | [...] there actually is a difference between offload_plugins and | offload_targets (for example, "intelmic" |

Re: [PATCH] Mark -fstack-protect as optimization flag (PR middle-end/71585)

On Wed, Jun 29, 2016 at 11:02 AM, Martin Liška wrote: > On 06/28/2016 03:54 PM, Richard Biener wrote: >> I wonder about the inliner change. If one marks a single function >> with -fstack-protector >> that implicitely marks callers with -fno-stack-protector. So I'd >> rather disable inlining >> b

Re: Improve insert/emplace robustness to self insertion

On 28/06/16 21:59 +0200, François Dumont wrote: @@ -303,16 +301,20 @@ _GLIBCXX_BEGIN_NAMESPACE_CONTAINER emplace(const_iterator __position, _Args&&... __args) { const size_type __n = __position - begin(); It looks like this should use __position - cbegin(), to avoid an impli

Re: [PATCH] Mark -fstack-protect as optimization flag (PR middle-end/71585)

On 06/28/2016 03:54 PM, Richard Biener wrote: > I wonder about the inliner change. If one marks a single function > with -fstack-protector > that implicitely marks callers with -fno-stack-protector. So I'd > rather disable inlining > between different settings here? It works in the opposite way,

Re: Improve insert/emplace robustness to self insertion

On 28/06/16 21:59 +0200, François Dumont wrote: template void vector<_Tp, _Alloc>:: -_M_insert_aux(iterator __position, const _Tp& __x) +_M_insert_value_aux(iterator __position, const _Tp& __x) #endif { - if (this->_M_impl._M_finish != this->_M_impl._M_end_of_storage) +

Re: [AArch64] ARMv8.2 command line and feature macros support

On Mon, Jun 27, 2016 at 03:58:00PM +0100, Jiong Wang wrote: > On 07/06/16 09:46, Jiong Wang wrote: > >2016-06-07 Matthew Wahab > >Jiong Wang > > > >* config/aarch64/aarch64-arches.def: Add "armv8.2-a". > >* config/aarch64/aarch64.h (AARCH64_FL_V8_2): New. > >(AA

Re: [ARM] Fix, add tests for FP16 aapcs.

On Mon, Jun 27, 2016 at 10:58 AM, Matthew Wahab wrote: > On 10/06/16 15:30, Matthew Wahab wrote: >> On 10/06/16 15:22, Christophe Lyon wrote: >>> On 10 June 2016 at 15:56, Matthew Wahab >>> wrote: On 10/06/16 09:32, Christophe Lyon wrote: > > On 9 June 2016 at 17:21, Matthew Wahab >

Re: [ARM] Fix, add tests for FP16 aapcs.

On 27 June 2016 at 11:58, Matthew Wahab wrote: > On 10/06/16 15:30, Matthew Wahab wrote: >> On 10/06/16 15:22, Christophe Lyon wrote: >>> On 10 June 2016 at 15:56, Matthew Wahab >>> wrote: On 10/06/16 09:32, Christophe Lyon wrote: > > On 9 June 2016 at 17:21, Matthew Wahab > wro

Re: [PATCH] tree-ssa-strlen improvements (PR tree-optimization/71625)

On Tue, 28 Jun 2016, Jakub Jelinek wrote: > Hi! > > This is just first small step towards this PR. > It brings the ADDR_EXPR of DECL_P bases roughly on the same level as > SSA_NAMEs pointers - so get_stridx_plus_constant works for them, and > more importantly, before this patch there was a very s

RE: [PATCH 3/4] Add support to run auto-vectorization tests for multiple effective targets

On Wed, 29 Jun 2016, Matthew Fortune wrote: > Robert Suchanek writes: > > I'm resending this patch as it has been rebased and updated. I reverted a > > change > > to check_effective_target_vect_call_lrint procedure because it does not use > > cached result. > > Hi Richard, > > Do you know who

Re: Determine more IVs to be non-overflowing

On Wed, 29 Jun 2016, Jan Hubicka wrote: > > + if (!get_max_loop_iterations (loop, &nit)) > > +/* 10GHz CPU runing one cycle loop will reach 2^60 iterations in 260 > > + years. I won't live long enough to be forced to fix the > > + miscompilation. Having the limit here will let u

  1   2   >