On 10/11/2014 09:11 AM, Richard Henderson wrote:
> On 09/22/2014 11:45 PM, Zhenqiang Chen wrote:
>> +static unsigned int
>> +aarch64_code_to_nzcv (enum rtx_code code, bool inverse) {
>> + switch (code)
>> +{
>> +case NE: /* NE, Z == 0. */
>> + return inverse ? AARCH64_CC_Z : 0;
>> +
convert_like_real was getting confused because it was seeing a reference
binding that we had marked as bad, but it couldn't tell what was bad
about it. This happened because when we did the ck_base conversion the
rvalue expression became an lvalue. Fixed by preserving rvalueness
through conve
A few cleanups in line-map code. Bootstrapped and regression tested on
x86_64-linux-gnu.
OK?
libcpp/ChangeLog:
2014-10-12 Manuel López-Ibáñez
* include/line-map.h (linemap_location_from_macro_expansion_p):
const struct line_maps * argument.
(linemap_position_for_line_and_column):
On 09/22/2014 11:46 PM, Zhenqiang Chen wrote:
> @@ -2375,10 +2387,21 @@ noce_get_condition (rtx_insn *jump, rtx_insn
> **earliest, bool then_else_reversed
>return cond;
> }
>
> + /* For conditional compare, set ALLOW_CC_MODE to TRUE. */
> + if (targetm.gen_ccmp_first)
> +{
>
On 09/22/2014 11:46 PM, Zhenqiang Chen wrote:
> +static bool
> +aarch64_convert_mode (rtx* op0, rtx* op1, int unsignedp)
> +{
> + enum machine_mode mode;
> +
> + mode = GET_MODE (*op0);
> + if (mode == VOIDmode)
> +mode = GET_MODE (*op1);
> +
> + if (mode == QImode || mode == HImode)
> +
On 09/22/2014 11:45 PM, Zhenqiang Chen wrote:
> +(define_expand "cbranchcc4"
> + [(set (pc) (if_then_else
> + (match_operator 0 "aarch64_comparison_operator"
> +[(match_operand 1 "cc_register" "")
> + (const_int 0)])
> + (label_ref (match_operand 3 "" ""
After the compile-time simplification, this patch fixes the handling of special
values (infinities and NaNs) by intrinsics EXPONENT, FRACTION, SPACING,
RRSPACING & SET_EXPONENT on the code generation side.
Bootstrapped and regtested on x86_64-linux.
OK to commit?
intrinsics.ChangeLog
Descri
On Oct 10, 2014, at 8:32 PM, Bin.Cheng wrote:
>
>>> Though I guess if we run fusion + peep2 between sched1 and sched2, that
>>> problem would just resolve itself as we'd have fused AB together into a new
>>> insn and we'd schedule normally with the fused insns and X, Y.
>>
>> Yes, in my versio
On 11/10/2014 5:56 PM, Andrew Pinski wrote:
On Sat, Oct 11, 2014 at 9:42 AM, Kwok Cheung Yeung
wrote:
__gthread_active_p() in libgcc checks for thread support by looking for the
presence of a symbol from libpthread. With glibc, it looks for
__pthread_key_create. However, it determines that gli
On Sat, Oct 11, 2014 at 9:42 AM, Kwok Cheung Yeung
wrote:
> __gthread_active_p() in libgcc checks for thread support by looking for the
> presence of a symbol from libpthread. With glibc, it looks for
> __pthread_key_create. However, it determines that glibc is being used by
> checking for a defi
__gthread_active_p() in libgcc checks for thread support by looking for
the presence of a symbol from libpthread. With glibc, it looks for
__pthread_key_create. However, it determines that glibc is being used by
checking for a definition of __GLIBC__, which is also defined by uClibc
(in include
On 09/22/2014 11:45 PM, Zhenqiang Chen wrote:
> +static unsigned int
> +aarch64_code_to_nzcv (enum rtx_code code, bool inverse) {
> + switch (code)
> +{
> +case NE: /* NE, Z == 0. */
> + return inverse ? AARCH64_CC_Z : 0;
> +case EQ: /* EQ, Z == 1. */
> + return inverse ? 0
On Sat, Oct 11, 2014 at 03:13:00PM +0200, FX wrote:
> The attached patch fixes the compile-time simplification of special
> values (positive and negative zeros, infinities, and NaNs) in
> intrinsics EXPONENT, FRACTION, RRSPACING, SET_EXPONENT, SPACING.
> Those are all the intrinsics in the Fortran
On 09/22/2014 11:44 PM, Zhenqiang Chen wrote:
> +case CC_DNEmode:
> + return comp_code == NE ? AARCH64_NE : AARCH64_EQ;
> +case CC_DEQmode:
> + return comp_code == NE ? AARCH64_EQ : AARCH64_NE;
> +case CC_DGEmode:
> + return comp_code == NE ? AARCH64_GE : AARCH64_LT;
> +
On 09/22/2014 11:44 PM, Zhenqiang Chen wrote:
> +/* Return true if val can be encoded as a 5-bit unsigned immediate. */
> +bool
> +aarch64_uimm5 (HOST_WIDE_INT val)
> +{
> + return (val & (HOST_WIDE_INT) 0x1f) == val;
> +}
This is just silly.
> +(define_constraint "Usn"
> + "A constant that can
On 09/22/2014 11:43 PM, Zhenqiang Chen wrote:
> + /* If jumps are cheap and the target does not support conditional
> + compare, turn some more codes into jumpy sequences. */
> + else if (BRANCH_COST (optimize_insn_for_speed_p (), false) < 4
> +&& (targetm.gen_
On 09/22/2014 11:43 PM, Zhenqiang Chen wrote:
>
> +@cindex @code{ccmp} instruction pattern
> +@item @samp{ccmp}
> +Conditional compare instruction. Operand 2 and 5 are RTLs which perform
> +two comparisons. Operand 1 is AND or IOR, which operates on the result of
> +operand 2 and 5.
> +It uses r
Hello,
This is the last common infrastructure patch in the series.
(Next patches will contain tests for libgomp testsuite and MIC specific things)
It introduces 2 new options:
1. -foffload==
By default, GCC will build offload images for all offload targets specified
in configure, with non-targ
On Thu, 9 Oct 2014, Maciej W. Rozycki wrote:
> Seeing Rohit got good results it has struck me that perhaps one of the
> patches I had previously reverted, to be able to compile GCC in the first
> place, interfered with this fix -- I backed out all the subsequent patches
> to test yours and Roh
Hi,
The TARGET_SH4A_ARCH macro has the same meaning as TARGET_SH4A and thus
can be removed. Tested with 'make all' on sh-elf, committed as r216119.
Cheers,
Oleg
gcc/ChangeLog:
* config/sh/sh.h (TARGET_SH4A_ARCH): Remove macro.
* config/sh/sh.h: Replace uses of TARGET_SH4A_ARCH w
The attached patch fixes the compile-time simplification of special values
(positive and negative zeros, infinities, and NaNs) in intrinsics EXPONENT,
FRACTION, RRSPACING, SET_EXPONENT, SPACING. Those are all the intrinsics in the
Fortran 2008 standard that say anything about these special value
Hello Jeff,
I see that you have improved the RTL typesafety issue for ira.c,
so I rebased this patch
on the latest trunk and change to use the new list walking interface.
Bootstrapped on x86_64-SUSE-Linux and make check regression tested.
OK for trunk?
Index: gcc/ChangeLog
===
> So, I hate the name of the option, and the documentation seems wrong to me.
> It doesn’t use the caller saved registers for allocation, it uses the call
> clobbered registers for allocation. Or, one could say it uses the callee
> saved registers for allocation.
Seconded, the description is a b
On 11.10.14 12:43, Jan-Benedict Glaw wrote:
On Wed, 2014-10-08 17:10:01 -, hubi...@gcc.gnu.org
wrote:
URL: https://gcc.gnu.org/viewcvs?rev=216010&root=gcc&view=rev
* ipa-polymorphic-call.c (extr_type_from_vtbl_store): Do better
pattern matching of MEM_REF.
(check_st
On Wed, 2014-10-08 17:10:01 -, hubi...@gcc.gnu.org
wrote:
> URL: https://gcc.gnu.org/viewcvs?rev=216010&root=gcc&view=rev
> * ipa-polymorphic-call.c (extr_type_from_vtbl_store): Do better
> pattern matching of MEM_REF.
> (check_stmt_for_type_change): Update.
This recent com
When testing arm-linux-gnueabihf triple with configure options
--with-mode=thumb(that makes -mthumb option default).
some testcase is failed with error message "sorry, unimplemented:
Thumb-1 hard-float VFP ABI".
I found gcc compiler show this error message when :
1. -mthumb is used with -march=armv
On 10 October 2014 21:13, Jeff Law wrote:
...
> ISTM it would be better to find the mode of the same class that corresponds
> to GET_MODE_SIZE (mode) / nregs. In your case that's obviously QImode :-)
Like this?
Or did you mean to remove the save_mode[regno] use altogether? I can
think of argume
PING?
>
> Hi Sterling,
>
> I made some improvement to the patch. Two changes:
> 1. TARGET_LOOPS is now used as a condition of the doloop related
> patterns, which is more elegant.
> 2. As the trip count register of the zero-cost loop maybe potentially
> spilled,
> we need to change
>
> Hello.
>
> Yeah, you are right. But even Richard advised me to put it to a single place.
> Maybe we are a bit
> more strict than it would be necessary. But I hope that's fine ;)
OK, lets do extra checking now and play with this incrementally.
>
> Good point. Do you mean cases like, foo (al
> > +/* Verifies for given GIMPLEs S1 and S2 that
> > + goto statements are semantically equivalent. */
> > +
> > +bool
> > +func_checker::compare_gimple_goto (gimple g1, gimple g2)
> > +{
> > + tree dest1, dest2;
> > +
> > + dest1 = gimple_goto_dest (g1);
> > + dest2 = gimple_goto_dest (g2);
>
> After few days of measurement and tuning, I was able to get numbers to the
> following shape:
> Execution times (seconds)
> phase setup : 0.00 ( 0%) usr 0.00 ( 0%) sys 0.00 ( 0%)
> wall1412 kB ( 0%) ggc
> phase opt and generate : 27.83 (59%) usr 0.66 (19%) sys 28
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