Re: [PATCH] reload: Try alternative with swapped operands before going to the next

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/15/11 15:31, Maxim Kuvyrkov wrote: > On 15/11/2011, at 6:21 AM, Andreas Krebbel wrote: >> >> Bootstrapped on s390x, x86_64 and PPC64. No regressions >> >> Ok for mainline? > > Good portion of the code you're changing was written by Richard K.

RE: [PATCH RFA] rtl-optimization/PR50663, conditional propagation missed in cprop.c pass

Hi, Thanks for your review. Here comes the 2nd version patch modified according to your comments. Is it ok? Also could you please commit it if ok because I have no write access? The new patch is tested against x86-linux-gnu. Thanks. 2011-11-15 Bin Cheng PR rtl-optimization/50663

Re: Fix x86-elf build

I should add: I don't know any reason why this target should need its own ASM_OUTPUT_ASCII definition (instead of the default ELF version) at all, but haven't tried removing the definition. -- Joseph S. Myers jos...@codesourcery.com

Re: [trunk] RFS: translate built-in include paths for sysroot (issue 5394041)

On 2011/11/16 00:47:10, shenhan wrote: 2011-11-15 Han Shen * gcc/Makefile.in: * gcc/configure: * gcc/cppdefault.c: diff --git a/gcc/Makefile.in b/gcc/Makefile.in index ae4f4da..0a05783 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in

[alpha] Convert to atomic optabs

Tested with qemu. Thankfully most of the changes really only have to do with passing around the memory model, and eliding one or both of the mb insns. I didn't implement mem_thread_fence or atomic_load/store patterns, because, with the existing memory_barrier pattern, the generic fallback pattern

[trunk] RFS: translate built-in include paths for sysroot (issue5394041)

2011-11-15 Han Shen * gcc/Makefile.in: * gcc/configure: * gcc/cppdefault.c: diff --git a/gcc/Makefile.in b/gcc/Makefile.in index ae4f4da..0a05783 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -615,6 +615,7 @@ gcc_tooldir = @gcc_tooldir@ build_tooldir = $(exec_

Make x86-elf use DWARF-2 not stabs

i?86-elf and x86_64-elf targets default to stabs debugging format. This default dates back to when x86-elf support was added in - and given the copyright dates in the original submission, the support was pretty old even then. Even if this

Fix x86-elf build

config/i386/i386elf.h wasn't updated for the change of STRING_LIMIT to ELF_STRING_LIMIT, so breaking builds for i?86-elf. I've committed this patch as obvious to fix this. Tested building cc1 and xgcc for cross to i686-elf. Index: gcc/ChangeLog

[v3] libstdc++/51142

Hi, this fixes the problem submitter noticed by implementing LWG 2059, which seems a good thing to do anyway, instead of just fixing the specific erase calls in the debug-mode code. The patch seems big, but actually is straightforward and limited to C++11, thus I mean to apply it to the branc

Re: [PATCH] reload: Try alternative with swapped operands before going to the next

On 15/11/2011, at 6:21 AM, Andreas Krebbel wrote: > Hi, > > find_reloads currently loops over all alternatives in an insn and > restarts the whole process after swapping commutative operands. This > together with the early exit for a perfectly matching alternative > leads to an behavior which do

[PATCH RFC] Correct sparc's REGMODE_NATURAL_SIZE and MODES_TIEABLE_P wrt. vector modes.

Eric, this is just something I noticed while trying to fix the vec_init problems last week. I'm confident that the issue is real, however I can't point to any real bugs that are caused by this. Therefore I'm reluctant to commit this change. What do you think? gcc/ * config/sparc/sparc

Re: [PR50764, PATCH] Fix for ICE in maybe_record_trace_start with -fsched2-use-superblocks

On 30/10/2011, at 8:17 AM, Tom de Vries wrote: > Richard, > > I have a tentative fix for PR50764. Richard, Tom's patch is good (with the comments below addressed), and I would appreciate you validating my review with your formal approval. > > In the example from the test-case, -fsched2-use-s

Re: [PATCH] tail_merge_optimize frequency fix

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/15/11 12:24, Tom de Vries wrote: > Richard, > > this patch fixes up the basic block frequencies after merging 2 bbs > in tail_merge_optimize, and prevents tree-dump messages like: > 'Invalid sum of incoming frequencies x, should be y'. > > Boo

Re: [PATCH 0/2] Convert ia64 to atomic optabs

On Tue, Nov 15, 2011 at 11:30 AM, Steve Ellcey wrote: > I'll try to test it but I am currently trying to track down a bootstrap > failure on IA64 HP-UX that appears to have started somewhere between > r181238 and r181287.  My IA64 HP-UX build currently fails with: > > build/genmddeps /ctires/gcc/n

Re: [PATCH 0/2] Convert ia64 to atomic optabs

On Tue, 2011-11-15 at 08:53 -1000, Richard Henderson wrote: > This is relatively straight-forward, given that most of the > language actually matches up with the opcodes. ;-) > > As mentioned in the patch itself, this is based on the data > presented in > >http://www.cl.cam.ac.uk/~pes20/cpp

[PATCH, i386]: Optimize v2df (x2) -> v4sf,v4si conversion sequences for AVX.

Hello! Attached patch optimizes v2df (x2) -> v4sf,v4si conversion sequences for AVX from: vcvtpd2psx 48(%rsp), %xmm1 vcvtpd2psx 64(%rsp), %xmm0 vmovlhps%xmm0, %xmm1, %xmm0 vmovaps %xmm0, 32(%rsp) to vmovapd 64(%rsp), %xmm0 vinse

[PATCH] tail_merge_optimize frequency fix

Richard, this patch fixes up the basic block frequencies after merging 2 bbs in tail_merge_optimize, and prevents tree-dump messages like: 'Invalid sum of incoming frequencies x, should be y'. Bootstrapped and reg-tested on x86_64 and i686, build and reg-tested on ARM and MIPS. OK for trunk? Th

Re: New port^2: Renesas RL78

> Otherwise the port is looking ok. What else need I do for this port?

Committed: fix typo in epiphany.md:movcc

David Bremner alerted be to the presence of a typo in the Epiphany movcc pattern. I have checked in the attached patch as obvious. 2011-11-15 Joern Rennecke * config/epiphany/epiphany.md (movcc): Fix code to get mode from CMP_OP1 if CMP_OP0 is VOIDmode. Index: config/epiphany

[PATCH 2/2] ia64: Update to atomic optabs

--- gcc/config/ia64/ia64-protos.h |3 +- gcc/config/ia64/ia64.c| 75 -- gcc/config/ia64/ia64.md |2 + gcc/config/ia64/sync.md | 312 ++--- 4 files changed, 294 insertions(+), 98 deletions(-) diff --git a/gcc/config/ia64/ia

[PATCH 0/2] Convert ia64 to atomic optabs

This is relatively straight-forward, given that most of the language actually matches up with the opcodes. ;-) As mentioned in the patch itself, this is based on the data presented in http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html which has a few non-obvious points. Tested on ia64-

[PATCH 1/2] ia64: Use define_c_enum for unspec constants.

--- gcc/config/ia64/ia64.md | 104 +++--- 1 files changed, 52 insertions(+), 52 deletions(-) diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 46eebc2..df744e7 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -48,61

Re: [PATCH, debug] Emit basic block markers in .debug_line section

I considered to use it as a starting point to build the control-flow graph of a function in order to display it in a custom profiler we use internally since I could assume that I had the debugging information and I had to read the .debug_line section anyway to get the source lines. I ended up not

Re: [wwwdocs] add news items for TM work

On 11/15/11 12:18, Aldy Hernandez wrote: Is this OK? BTW, I have updated the wiki here for more information: http://gcc.gnu.org/wiki/TransactionalMemory And included a relevant link from the news items.

[wwwdocs] add news items for TM work

Is this OK? Index: index.html === RCS file: /cvs/gcc/wwwdocs/htdocs/index.html,v retrieving revision 1.824 diff -c -p -r1.824 index.html *** index.html 15 Nov 2011 06:01:24 - 1.824 --- index.html 15 Nov 2011 18:16:43 -

Re: [PING] PR50325: store_bit_field: Fix for big endian targets

On 11/15/2011 07:22 AM, Andreas Krebbel wrote: > This fixes many C++ tests on s390x and PPC64: > http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01220.html Ok. r~

Re: CFG review needed for fix of "PowerPC shrink-wrap support 3 of 3"

On 11/14/2011 11:56 AM, Alan Modra wrote: > * function.c (thread_prologue_and_epilogue_insns): Guard > emitting return with single_succ_p test. Ok. r~

Re: [PATCH, take 2] Fix PR tree-optimization/49960 ,Fix self data dependence

On Tue, Nov 15, 2011 at 11:31 AM, Razya Ladelsky wrote: >> > I hope it's clearer now, I will add a comment to the code, and submit > it >> > before committing it. >> >> No, it's not clearer, because it is not clear why you need to add the > hack >> instead of avoiding the 2nd access function. And

[PING] PR50325: store_bit_field: Fix for big endian targets

This fixes many C++ tests on s390x and PPC64: http://gcc.gnu.org/ml/gcc-patches/2011-09/msg01220.html Bye, -Andreas-

Re: Minor contrib.texi update

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/15/11 10:19, Joseph S. Myers wrote: > The attachment doesn't seem to match the rest of your message. > Attached wrong file as Andrey pointed out earlier... Here's the right one... Oh how I wish thunderbird would show the attachment inline...

Re: Minor contrib.texi update

The attachment doesn't seem to match the rest of your message. -- Joseph S. Myers jos...@codesourcery.com

Re: [Patch] Fix compilation of libgcc/config/alpha/qrnnd.S on VMS

On 11/15/2011 01:58 AM, Tristan Gingold wrote: > * config/alpha/qrnnd.S: Use specific pseudos for VMS. Fine by me. I know nothing about vms.

Re: PATCH for to use tree clobbers for c++/51060 (temporary re-use)

> Now that we have a way of explicitly marking a variable as dead, we > can use that to indicate the end of a temporary's lifetime by adding > it as a cleanup for that temporary. Since gimple_push_cleanup still > deals in trees I needed to tweak a couple of places to avoid trying > to treat a clo

[RFA/ARM] Make libgcc use UDIV/SDIV instructions when they are available.

All, The attached patch causes libgcc to use the UDIV and SDIV instructions when possible in the implementation of the ARM div/mod functions in libgcc. This will benefit Cortex-M3, Cortex-M4, all Cortex-R* CPUs, Cortex-A7, and Cortex-A15. The special case of some Cortex-R* CPUs where the UD

Re: Memset/memcpy patch

On 11/15/2011 04:12 PM, Michael Zolotukhin wrote: Looks like we have a bootstrap issue, thus sorry if may message may appear stupid nitpicking: why Zolotukhin Michael instead of Michael Zolotukhin in the ChangeLog? Is Michael the family name? Michael is the first name, Zolotukhin - last name.

Re: [PATCH, debug] Emit basic block markers in .debug_line section

> "Roberto" == Roberto Agostino Vitillo writes: Roberto> With this patch DW_LNS_set_basic_block opcodes are emitted in Roberto> the .debug_line section marking the instructions that indicate Roberto> the beginning of a basic block as specified by the dwarf Roberto> standards 2,3 and 4. I'm c

Re: Memset/memcpy patch

> Looks like we have a bootstrap issue, thus sorry if may message may appear > stupid nitpicking: why Zolotukhin Michael instead of Michael Zolotukhin in > the ChangeLog? Is Michael the family name? Michael is the first name, Zolotukhin - last name. I probably swapped them accidentally in the cha

Re: [wwwdocs] gcc-4.6/porting_to.html

[Sorry for the delay, catching up after being away] Gerald Pfeifer writes: > On Mon, 10 Oct 2011, Gerald Pfeifer wrote: >> I realized this one hasn't made it in, but is really nice. I made a >> number of minor edits (typos, markup, simplifying headings,... among >> others). What do you think

[C++11] Streamline user-defined literal error messages and some code reformatting.

I just wanted to do a little clean up on the user-defined literal code. Index: gcc/testsuite/g++.dg/cpp0x/udlit-raw-op-string-neg.C === --- gcc/testsuite/g++.dg/cpp0x/udlit-raw-op-string-neg.C(revision 181376) +++ gcc/testsu

[Patch] Fix compilation of libgcc/config/alpha/qrnnd.S on VMS

Hi, latest versions of gas are picky about the use of the pseudos. Consequently we need to adjust them in qrnnd.S. Tested by building gcc for alpha-vms. Ok for the trunk ? Tristan. 2011-11-07 Tristan Gingold * config/alpha/qrnnd.S: Use specific pseudos for VMS. diff --git a/

Re: GCC 4.7.0 Status Report (2011-10-27), Stage 1 will end Nov 7th

Hello! x86-specific part of this patch was committed to the trunk recently. There is also target-independent part, which covers memset/memcopy for the smallest sizes (from 1 to ~256 bytes). In contrast to existing implementation, it has a cost model to choose the fastest move-mode (which could be

[v3] libstdc++/51133

Hi, tested x86_64-linux multilib, committed mainline and 4_6-branch. Thanks, Paolo. /// 2011-11-15 Jason Dick PR libstdc++/51133 * include/tr1/poly_hermite.tcc (__poly_hermite_recursion): Fix wrong sign in recursion relation. Index: include/tr1/poly_h

[PATCH, take 2] Fix PR tree-optimization/49960 ,Fix self data dependence

> > I hope it's clearer now, I will add a comment to the code, and submit it > > before committing it. > > No, it's not clearer, because it is not clear why you need to add the hack > instead of avoiding the 2nd access function. And iff you add the hack it > needs a comment why zero should be sp

Re: [PATCH 3/3, RFC] Fixup COND_EXECs before reload

Hello, On 26.10.2011 21:58, Alexander Monakov wrote: This RFC patch implements conversion of COND_EXEC instructions to control flow for pre-RA selective scheduler. Something like this is needed to employ predication support before reload. Each COND_EXEC is converted separately to a new basic

Re: [PATCH 2/3] Predication support

Hello, On 26.10.2011 21:49, Alexander Monakov wrote: 2011-10-26 Alexander Monakov * common.opt: Add -fsel-sched-predication option. * config/ia64/ia64.c (get_mode_no_for_insn): Support conditional loads. * rtl.h (COND_SET_SRC_PTR, COND_SET_SRC_PTR): New macros.

Re: coverage, propagate visibility

On 11/15/11 07:55, Markus Trippelsdorf wrote: Nothing changed the set of emitted functions. The error message above was just an example. Will post the full error message in the PR (51113). I will also try to come up with a smaller testcase. Something's changed the linkage of ZN2js11WeakMapBase