[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support new IFN SAT_ADD for unsigned vector int

https://gcc.gnu.org/g:ee2048d722933d88146e8393164e02496cd96ec6 commit ee2048d722933d88146e8393164e02496cd96ec6 Author: Pan Li Date: Wed May 15 10:14:06 2024 +0800 Vect: Support new IFN SAT_ADD for unsigned vector int For vectorize, we leverage the existing vect pattern recog to fi

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int

https://gcc.gnu.org/g:4459be85597eaa6fb3c158a3be328e5399bce3ab commit 4459be85597eaa6fb3c158a3be328e5399bce3ab Author: Pan Li Date: Wed May 15 10:14:05 2024 +0800 Internal-fn: Support new IFN SAT_ADD for unsigned scalar int This patch would like to add the middle-end presentation

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support loop len in vectorizable early exit

https://gcc.gnu.org/g:4950489dfbaba5727820631195e4ed26b8edc46d commit 4950489dfbaba5727820631195e4ed26b8edc46d Author: Pan Li Date: Thu May 16 09:58:13 2024 +0800 Vect: Support loop len in vectorizable early exit This patch adds early break auto-vectorization support for target wh

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement vectorizable early exit with vcond_mask_len

https://gcc.gnu.org/g:2e79d0c4dddca3075b9c54f1b4eceed377920e62 commit 2e79d0c4dddca3075b9c54f1b4eceed377920e62 Author: Pan Li Date: Thu May 16 10:02:40 2024 +0800 RISC-V: Implement vectorizable early exit with vcond_mask_len After we support the loop lens for the vectorizable, we

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorizable early exit testsuite

https://gcc.gnu.org/g:620d0469957417f13c715ae6905e23d8b8f2369f commit 620d0469957417f13c715ae6905e23d8b8f2369f Author: Pan Li Date: Thu May 16 10:04:10 2024 +0800 RISC-V: Enable vectorizable early exit testsuite After we supported vectorizable early exit in RISC-V, we would like

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cleanup some temporally files [NFC]

https://gcc.gnu.org/g:46e46702d29e8b357a3317a1aca31c64f47127ca commit 46e46702d29e8b357a3317a1aca31c64f47127ca Author: Pan Li Date: Fri May 17 07:45:19 2024 +0800 RISC-V: Cleanup some temporally files [NFC] Just notice some temporally files under gcc/config/riscv, deleted as u

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] internal-fn: Do not force vcond_mask operands to reg.

https://gcc.gnu.org/g:e8502a71dab6ee193850911c709f287e9a6fa5e2 commit e8502a71dab6ee193850911c709f287e9a6fa5e2 Author: Robin Dapp Date: Fri May 10 12:44:44 2024 +0200 internal-fn: Do not force vcond_mask operands to reg. In order to directly use constants this patch removes force_

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add initial cost handling for segment loads/stores.

https://gcc.gnu.org/g:1db74cdf2656b5b4a70ec91c4fd1a192881704bb commit 1db74cdf2656b5b4a70ec91c4fd1a192881704bb Author: Robin Dapp Date: Mon Feb 26 13:09:15 2024 +0100 RISC-V: Add initial cost handling for segment loads/stores. This patch makes segment loads and stores more expensi

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement IFN SAT_ADD for both the scalar and vector

https://gcc.gnu.org/g:afd3785dfd2198fb6ab01f9398635ca2a4e330fe commit afd3785dfd2198fb6ab01f9398635ca2a4e330fe Author: Pan Li Date: Fri May 17 18:49:46 2024 +0800 RISC-V: Implement IFN SAT_ADD for both the scalar and vector The patch implement the SAT_ADD in the riscv backend as t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Modify _Bfloat16 to __bf16

https://gcc.gnu.org/g:55fe174e53676a046c9918082ef2d875a1fa1f67 commit 55fe174e53676a046c9918082ef2d875a1fa1f67 Author: Xiao Zeng Date: Fri May 17 13:48:21 2024 +0800 RISC-V: Modify _Bfloat16 to __bf16 According to the description in:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

https://gcc.gnu.org/g:a68bda6155f1be2e61a9efa2dee0d60e09579059 commit a68bda6155f1be2e61a9efa2dee0d60e09579059 Author: Xiao Zeng Date: Wed May 15 16:23:16 2024 +0800 RISC-V: Fix "Nan-box the result of movbf on soft-bf16" 1 According to unpriv-isa spec:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve some shift-add sequences

https://gcc.gnu.org/g:720584510bd181d9218bcfb42fa2a39cc15b30a3 commit 720584510bd181d9218bcfb42fa2a39cc15b30a3 Author: Jeff Law Date: Sat May 18 15:08:07 2024 -0600 [to-be-committed,RISC-V] Improve some shift-add sequences So this is a minor fix/improvement for shift-add sequences

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement -m{, no}fence-tso

https://gcc.gnu.org/g:872f7acb32d6508804cb59065a70c12d9843150b commit 872f7acb32d6508804cb59065a70c12d9843150b Author: Palmer Dabbelt Date: Sat May 18 15:15:09 2024 -0600 RISC-V: Implement -m{,no}fence-tso Some processors from T-Head don't implement the `fence.tso` instruction

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

https://gcc.gnu.org/g:9e17aea0b8a6e0a620533645a2024ab0c03f9063 commit 9e17aea0b8a6e0a620533645a2024ab0c03f9063 Author: Jeff Law Date: Sun May 19 09:56:16 2024 -0600 [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn The circumstances which trigger

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] DSE: Fix ICE after allow vector type in get_stored_val

https://gcc.gnu.org/g:f623c17ac3bd482549a7725026d944d5e369c345 commit f623c17ac3bd482549a7725026d944d5e369c345 Author: Pan Li Date: Tue Apr 30 09:42:39 2024 +0800 DSE: Fix ICE after allow vector type in get_stored_val We allowed vector type for get_stored_val when read is less tha

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Regenerate riscv.opt.urls and i386.opt.urls

https://gcc.gnu.org/g:5300baa0bcfe07cbc740ff9168d5b6142ad57f1f commit 5300baa0bcfe07cbc740ff9168d5b6142ad57f1f Author: Mark Wielaard Date: Mon May 20 13:13:02 2024 +0200 Regenerate riscv.opt.urls and i386.opt.urls risc-v added an -mfence-tso option. i386 removed Xeon Phi ISA suppo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

https://gcc.gnu.org/g:fcb6eb413e0cf2cd22f2ddb9a04cd13539778bbf commit fcb6eb413e0cf2cd22f2ddb9a04cd13539778bbf Author: Vineet Gupta Date: Mon May 13 11:46:03 2024 -0700 RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] If the constant used for stack offs

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in alloca epilogue expansion

https://gcc.gnu.org/g:0de6d26c788c1569374ad2c43a177e5f692eaf62 commit 0de6d26c788c1569374ad2c43a177e5f692eaf62 Author: Vineet Gupta Date: Wed Mar 6 15:44:27 2024 -0800 RISC-V: avoid LUI based const mat in alloca epilogue expansion This is continuing on the prev patch in function e

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, v2, RISC-V] Use bclri in constant synthesis

https://gcc.gnu.org/g:ae6b8ddc3cc37598ac6cdc25a52e3119730c8688 commit ae6b8ddc3cc37598ac6cdc25a52e3119730c8688 Author: Jeff Law Date: Fri May 24 07:27:00 2024 -0600 [to-be-committed,v2,RISC-V] Use bclri in constant synthesis Testing with Zbs enabled by default showed a minor logic

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c

https://gcc.gnu.org/g:778f80697689921fadace08e0a48cf64feb1245c commit 778f80697689921fadace08e0a48cf64feb1245c Author: xuli Date: Mon May 20 01:56:47 2024 + RISC-V: Enable vectorization for vect-early-break_124-pr114403.c Because "targetm.slow_unaligned_access" is set to true

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [v2] More logical op simplifications in simplify-rtx.cc

https://gcc.gnu.org/g:52fc2ea9b4f70dd99d8f06555ea73f82552569ca commit 52fc2ea9b4f70dd99d8f06555ea73f82552569ca Author: Jeff Law Date: Sat May 25 12:39:05 2024 -0600 [committed] [v2] More logical op simplifications in simplify-rtx.cc This is a revamp of what started as a target spe

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant

https://gcc.gnu.org/g:4e5987b564f91831ced0b2d9a1553c60d86c3fcb commit 4e5987b564f91831ced0b2d9a1553c60d86c3fcb Author: Jeff Law Date: Sun May 26 10:54:18 2024 -0600 [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant Next step in constant

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Try inverting for constant synthesis

https://gcc.gnu.org/g:f4e34b1d13fc12c5ca141e9cda62aa83a36f9503 commit f4e34b1d13fc12c5ca141e9cda62aa83a36f9503 Author: Jeff Law Date: Sun May 26 17:54:51 2024 -0600 [to-be-committed] [RISC-V] Try inverting for constant synthesis So there's another class of constants we're failing

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V] Reassociate constants in logical ops

https://gcc.gnu.org/g:bf9c14558638fc6eca71b05fcae78e4358925295 commit bf9c14558638fc6eca71b05fcae78e4358925295 Author: Lyut Nersisyan Date: Sun May 26 21:24:40 2024 -0600 [to-be-committed][RISC-V] Reassociate constants in logical ops This patch from Lyut will reassociate operands

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Some basic patterns for zbkb code generation

https://gcc.gnu.org/g:5d05c1c28cc5b8c0cfc6fc624c982a6cc7a89726 commit 5d05c1c28cc5b8c0cfc6fc624c982a6cc7a89726 Author: Lyut Nersisyan Date: Tue May 28 09:17:50 2024 -0600 [to-be-committed] [RISC-V] Some basic patterns for zbkb code generation And here's Lyut's basic Zbkb support.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use pack to handle repeating constants

https://gcc.gnu.org/g:e1c7a5d87c8c0904e473b6355586193f0724c1ba commit e1c7a5d87c8c0904e473b6355586193f0724c1ba Author: Jeff Law Date: Wed May 29 07:41:55 2024 -0600 [to-be-committed] [RISC-V] Use pack to handle repeating constants This patch utilizes zbkb to improve the code we ge

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vwsll combine helpers.

https://gcc.gnu.org/g:ae94f3f5277321d040a4a9bd9f0a4727b09c4d24 commit ae94f3f5277321d040a4a9bd9f0a4727b09c4d24 Author: Robin Dapp Date: Mon May 13 22:09:35 2024 +0200 RISC-V: Add vwsll combine helpers. This patch enables the usage of vwsll in autovec context by adding the nece

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Use widening shift for scatter/gather if applicable.

https://gcc.gnu.org/g:17baa957d9c76641ff876b6a86a744fc3fd37048 commit 17baa957d9c76641ff876b6a86a744fc3fd37048 Author: Robin Dapp Date: Fri May 10 13:37:03 2024 +0200 RISC-V: Use widening shift for scatter/gather if applicable. With the zvbb extension we can emit a widening shift

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vandn combine helper.

https://gcc.gnu.org/g:ef30a89950749055242b2cec39f578ee8ee27b6d commit ef30a89950749055242b2cec39f578ee8ee27b6d Author: Robin Dapp Date: Wed May 15 15:01:35 2024 +0200 RISC-V: Add vandn combine helper. This patch adds a combine pattern for vandn as well as tests for it. gc

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add vector popcount, clz, ctz.

https://gcc.gnu.org/g:fe352bf7a0dc7a7f54c7d1a4718c87f0b6402276 commit fe352bf7a0dc7a7f54c7d1a4718c87f0b6402276 Author: Robin Dapp Date: Wed May 15 17:41:07 2024 +0200 RISC-V: Add vector popcount, clz, ctz. This patch adds the zvbb vcpop, vclz and vctz to the autovec machinery

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Remove dead perm series code and document.

https://gcc.gnu.org/g:6a0310582f636571e5963ad991a6eb4c2aee00dc commit 6a0310582f636571e5963ad991a6eb4c2aee00dc Author: Robin Dapp Date: Fri May 17 12:48:52 2024 +0200 RISC-V: Remove dead perm series code and document. With the introduction of shuffle_series_patterns the explicit h

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable

https://gcc.gnu.org/g:b188bc60760721affcfab6264e7b526861770cee commit b188bc60760721affcfab6264e7b526861770cee Author: Jeff Law Date: Fri May 31 21:45:01 2024 -0600 [to-be-committed] [RISC-V] Use Zbkb for general 64 bit constants when profitable Basically this adds the ability to

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Just the riscv bits from:

https://gcc.gnu.org/g:db3b669e9ac63a6dec629e89907400349639653a commit db3b669e9ac63a6dec629e89907400349639653a Author: Jeff Law Date: Sun Jun 2 13:19:16 2024 -0600 Just the riscv bits from: commit a0d60660f2aae2d79685f73d568facb2397582d8 Author: Andrew Pinski Date: Wed

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zfbfmin extension

https://gcc.gnu.org/g:8fd618e6c32e48ccf5218648d13ffc83a1cfc1c5 commit 8fd618e6c32e48ccf5218648d13ffc83a1cfc1c5 Author: Xiao Zeng Date: Wed May 15 13:56:42 2024 +0800 RISC-V: Add Zfbfmin extension 1 In the previous patch, the libcall for BF16 was implemented:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Introduce -mvector-strict-align.

https://gcc.gnu.org/g:8f726cf36944bb69a86553c3b21847e2da797586 commit 8f726cf36944bb69a86553c3b21847e2da797586 Author: Robin Dapp Date: Tue May 28 21:19:26 2024 +0200 RISC-V: Introduce -mvector-strict-align. this patch disables movmisalign by default and introduces the -mno-ve

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode.

https://gcc.gnu.org/g:fb44c71672eb1533da1f127e728bdcb00077f467 commit fb44c71672eb1533da1f127e728bdcb00077f467 Author: liuhongt Date: Fri Apr 19 10:29:34 2024 +0800 Simplify (AND (ASHIFTRT A imm) mask) to (LSHIFTRT A imm) for vector mode. When mask is (1 << (prec - imm) - 1) which

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Regenerate opt urls.

https://gcc.gnu.org/g:f91cea7b2d41d9def84428a9425422f08c8ad8cc commit f91cea7b2d41d9def84428a9425422f08c8ad8cc Author: Robin Dapp Date: Thu Jun 6 09:32:28 2024 +0200 RISC-V: Regenerate opt urls. I wasn't aware that I needed to regenerate the opt urls when adding an option. Th

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 2

https://gcc.gnu.org/g:3b2293c8697fc7e27b3b40cd87a83c80e7fc4b84 commit 3b2293c8697fc7e27b3b40cd87a83c80e7fc4b84 Author: Pan Li Date: Mon Jun 3 09:35:49 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 2 After the middle-end support the form 2 of unsigned SAT_ADD an

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1

https://gcc.gnu.org/g:49c1d6f0835794784c59b7f59a639838df0a5a39 commit 49c1d6f0835794784c59b7f59a639838df0a5a39 Author: Pan Li Date: Wed May 29 14:15:45 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 1 After the middle-end support the form 1 of unsigned SAT_ADD a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 3

https://gcc.gnu.org/g:0dcdc91e03bda72d04ced593a08daae536e86456 commit 0dcdc91e03bda72d04ced593a08daae536e86456 Author: Pan Li Date: Mon Jun 3 10:24:47 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 3 After the middle-end support the form 3 of unsigned SAT_ADD an

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 4

https://gcc.gnu.org/g:111ec5fb8b079f458dee359c03e27327f6c7fdc3 commit 111ec5fb8b079f458dee359c03e27327f6c7fdc3 Author: Pan Li Date: Mon Jun 3 10:33:15 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 4 After the middle-end support the form 4 of unsigned SAT_ADD an

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_ADD form 5

https://gcc.gnu.org/g:1c438d611ed62e7898a4a3430032b6ab662f5540 commit 1c438d611ed62e7898a4a3430032b6ab662f5540 Author: Pan Li Date: Mon Jun 3 10:43:10 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_ADD form 5 After the middle-end support the form 5 of unsigned SAT_ADD an

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_SUB for unsigned scalar int

https://gcc.gnu.org/g:5cce50ed2ac360cefb788bc1aaa30ca788ffe95d commit 5cce50ed2ac360cefb788bc1aaa30ca788ffe95d Author: Pan Li Date: Wed Jun 5 16:42:05 2024 +0800 RISC-V: Implement .SAT_SUB for unsigned scalar int As the middle support of .SAT_SUB committed, implement the unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates.

https://gcc.gnu.org/g:eaa49bf23232f42ee490beec10921e977715ab6f commit eaa49bf23232f42ee490beec10921e977715ab6f Author: Roger Sayle Date: Sat Jun 8 19:47:08 2024 -0600 [middle-end PATCH] Prefer PLUS over IOR in RTL expansion of multi-word shifts/rotates. This patch tweaks RTL expa

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix false-positive uninitialized variable

https://gcc.gnu.org/g:52054a270021183fa19f799394680aaf5c432feb commit 52054a270021183fa19f799394680aaf5c432feb Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit warning after

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14

https://gcc.gnu.org/g:b161ab40cbeda518f08b6c329f29d9014a002123 commit b161ab40cbeda518f08b6c329f29d9014a002123 Author: Andreas Tobler Date: Sun Jun 9 23:18:04 2024 +0200 FreeBSD: Stop linking _p libs for -pg as of FreeBSD 14 As of FreeBSD version 14, FreeBSD no longer provides pro

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:b8b0c025ad5d43a72ae77ac255620d93835985c7 commit b8b0c025ad5d43a72ae77ac255620d93835985c7 Author: Raphael Zinsly Date: Mon Jun 10 07:03:00 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as (src >> n) &

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object

https://gcc.gnu.org/g:643cf7193d65e1ad4c2e7116d4a07a14360dc59e commit 643cf7193d65e1ad4c2e7116d4a07a14360dc59e Author: Raphael Zinsly Date: Mon Jun 10 14:16:16 2024 -0600 [to-be-committed] [RISC-V] Use bext for extracting a bit into a SImode object bext is defined as (src >> n) &

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Just the testsuite bits from:

https://gcc.gnu.org/g:c9044161a1d22eea9948e1103697e178ba3fc587 commit c9044161a1d22eea9948e1103697e178ba3fc587 Author: Pan Li Date: Mon Jun 10 14:13:38 2024 -0600 Just the testsuite bits from: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI match When enab

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Drop dead round_32 test

https://gcc.gnu.org/g:dccad0a6e0b8d17ebf30c802319baa3117f48080 commit dccad0a6e0b8d17ebf30c802319baa3117f48080 Author: Jeff Law Date: Mon Jun 10 22:39:40 2024 -0600 [committed] [RISC-V] Drop dead round_32 test This test is no longer useful. It doesn't test what it was originally

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement .SAT_SUB for unsigned vector int

https://gcc.gnu.org/g:3f3aa24e5eaeefa73ee9d8d86c16eaa137a731c0 commit 3f3aa24e5eaeefa73ee9d8d86c16eaa137a731c0 Author: Pan Li Date: Tue Jun 11 11:04:22 2024 +0800 RISC-V: Implement .SAT_SUB for unsigned vector int As the middle support of .SAT_SUB committed, implement the unsigne

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add basic Zaamo and Zalrsc support

https://gcc.gnu.org/g:67d574e1327f89f838954018e5cdd1fcf46c3a00 commit 67d574e1327f89f838954018e5cdd1fcf46c3a00 Author: Edwin Lu Date: Wed Feb 7 16:30:28 2024 -0800 RISC-V: Add basic Zaamo and Zalrsc support There is a proposal to split the A extension into two parts: Zaamo and Za

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zalrsc and Zaamo testsuite support

https://gcc.gnu.org/g:8bb23d671f2bb1ee0da5d030e746440877591010 commit 8bb23d671f2bb1ee0da5d030e746440877591010 Author: Patrick O'Neill Date: Mon Jun 10 14:12:40 2024 -0700 RISC-V: Add Zalrsc and Zaamo testsuite support Convert testsuite infrastructure to use Zalrsc and Zaamo rathe

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zalrsc amo-op patterns

https://gcc.gnu.org/g:e22f75a728a2a90bd06eb2d80e4c1b058b65437e commit e22f75a728a2a90bd06eb2d80e4c1b058b65437e Author: Patrick O'Neill Date: Wed Feb 7 16:30:30 2024 -0800 RISC-V: Add Zalrsc amo-op patterns All amo patterns can be represented with lrsc sequences. Add these patt

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move amo tests into subfolder

https://gcc.gnu.org/g:b50ec91dea8865486e3c849569353fb09c762e44 commit b50ec91dea8865486e3c849569353fb09c762e44 Author: Patrick O'Neill Date: Mon Jun 10 16:32:11 2024 -0700 RISC-V: Move amo tests into subfolder There's a large number of atomic related testcases in the riscv folder.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix amoadd call arguments

https://gcc.gnu.org/g:2dc7e9e4be62cbde97b0ed687ac0a849760bcf3d commit 2dc7e9e4be62cbde97b0ed687ac0a849760bcf3d Author: Patrick O'Neill Date: Mon Jun 10 16:58:12 2024 -0700 RISC-V: Fix amoadd call arguments Update __atomic_add_fetch arguments to be a pointer and value rather th

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow any temp register to be used in amo tests

https://gcc.gnu.org/g:5cccfbdb795ed9c3abf6c9b7e9fb22ccaa31b736 commit 5cccfbdb795ed9c3abf6c9b7e9fb22ccaa31b736 Author: Patrick O'Neill Date: Mon Jun 10 17:00:38 2024 -0700 RISC-V: Allow any temp register to be used in amo tests We artifically restrict the temp registers to be a[0-

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Test: Move target independent test cases to gcc.dg/torture

https://gcc.gnu.org/g:fc63e04a99e7b0c964b92cf68f069b0c26434d7f commit fc63e04a99e7b0c964b92cf68f069b0c26434d7f Author: Pan Li Date: Tue Jun 11 10:56:23 2024 +0800 Test: Move target independent test cases to gcc.dg/torture The test cases of pr115387 are target independent, at leas

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add support for subword atomic loads/stores

https://gcc.gnu.org/g:e29a44cfccc8338c6de4ed980d6925847f82b4fa commit e29a44cfccc8338c6de4ed980d6925847f82b4fa Author: Patrick O'Neill Date: Wed Jun 12 17:10:13 2024 -0700 RISC-V: Add support for subword atomic loads/stores Andrea Parri recently pointed out that we were emitting o

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

https://gcc.gnu.org/g:cf83fd6751ca0ceddc486528845a9dae73219738 commit cf83fd6751ca0ceddc486528845a9dae73219738 Author: Pan Li Date: Thu Jun 13 22:06:09 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 After the middle-end support the form 3 of unsigned SAT_SUB a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4

https://gcc.gnu.org/g:9e1054b00cbf7e391a02e6d0489225588d4bed7d commit 9e1054b00cbf7e391a02e6d0489225588d4bed7d Author: Pan Li Date: Thu Jun 13 22:35:21 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 4 After the middle-end support the form 4 of unsigned SAT_SUB a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5

https://gcc.gnu.org/g:b2ef770da6ca9b2f1084b72e02c97454b88c8976 commit b2ef770da6ca9b2f1084b72e02c97454b88c8976 Author: Pan Li Date: Thu Jun 13 22:43:31 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 5 After the middle-end support the form 5 of unsigned SAT_SUB a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6

https://gcc.gnu.org/g:4118e84db1d30f059d35ed5a369eddfa2013a272 commit 4118e84db1d30f059d35ed5a369eddfa2013a272 Author: Pan Li Date: Thu Jun 13 23:05:00 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 6 After the middle-end support the form 6 of unsigned SAT_SUB a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7

https://gcc.gnu.org/g:97bb64f0619cef8431edd277274ab6e9cc00d318 commit 97bb64f0619cef8431edd277274ab6e9cc00d318 Author: Pan Li Date: Fri Jun 14 09:49:22 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 7 After the middle-end support the form 7 of unsigned SAT_SUB a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8

https://gcc.gnu.org/g:4b51d08bb3d1131bf8f3a619df7084c8dc1fbaac commit 4b51d08bb3d1131bf8f3a619df7084c8dc1fbaac Author: Pan Li Date: Fri Jun 14 09:57:22 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 8 After the middle-end support the form 8 of unsigned SAT_SUB a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9

https://gcc.gnu.org/g:6e345559f6f9714f6dad5a692d510c04a7b361d1 commit 6e345559f6f9714f6dad5a692d510c04a7b361d1 Author: Pan Li Date: Fri Jun 14 10:03:15 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 9 After the middle-end support the form 9 of unsigned SAT_SUB a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10

https://gcc.gnu.org/g:13cd70ebd6fc1a05ccecf4b2164e534589e9782b commit 13cd70ebd6fc1a05ccecf4b2164e534589e9782b Author: Pan Li Date: Fri Jun 14 10:08:59 2024 +0800 RISC-V: Add testcases for scalar unsigned SAT_SUB form 10 After the middle-end support the form 10 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the SAT_ARITH test help header files [NFC]

https://gcc.gnu.org/g:a9cf5c3b11e48b9aea8119edc2de4cad54f0a6e4 commit a9cf5c3b11e48b9aea8119edc2de4cad54f0a6e4 Author: Pan Li Date: Sat Jun 15 10:15:17 2024 +0800 RISC-V: Refine the SAT_ARITH test help header files [NFC] Separate the vector part code to one standalone header file,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64

https://gcc.gnu.org/g:706f5754f3100df96f9b30fb13d1d49b6e510ac4 commit 706f5754f3100df96f9b30fb13d1d49b6e510ac4 Author: Jeff Law Date: Sun Jun 16 08:36:27 2024 -0600 [to-be-committed] [RISC-V] Improve (1 << N) | C for rv64 Another improvement for generating Zbs instructions.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for vector unsigned SAT_SUB form 2

https://gcc.gnu.org/g:a2d509a52d75b63e2b83438d17761143aa8da955 commit a2d509a52d75b63e2b83438d17761143aa8da955 Author: Pan Li Date: Sat Jun 15 20:27:01 2024 +0800 RISC-V: Add testcases for vector unsigned SAT_SUB form 2 The previous RISC-V backend .SAT_SUB enabling patch missed th

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve variable bit set for rv64

https://gcc.gnu.org/g:7bbf97d2352cf7369eac58dca6286af0853e377b commit 7bbf97d2352cf7369eac58dca6286af0853e377b Author: Jeff Law Date: Mon Jun 17 07:04:13 2024 -0600 [to-be-committed,RISC-V] Improve variable bit set for rv64 Another case of being able to safely use bset for 1 << n.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add configure check for Zaamo/Zalrsc assembler support

https://gcc.gnu.org/g:295193ae4846c947e52ce3443b154b060b86162a commit 295193ae4846c947e52ce3443b154b060b86162a Author: Patrick O'Neill Date: Mon Jun 17 09:46:05 2024 -0700 RISC-V: Add configure check for Zaamo/Zalrsc assembler support Binutils 2.42 and before don't support Zaamo/Z

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Handle zero_extract destination for single bit insertions

https://gcc.gnu.org/g:f6010dc455757f14482564c8f73ebb6461fa65d3 commit f6010dc455757f14482564c8f73ebb6461fa65d3 Author: Jeff Law Date: Mon Jun 17 17:24:03 2024 -0600 [to-be-committed,RISC-V] Handle zero_extract destination for single bit insertions Combine will use zero_extract de

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve bset generation when bit position is limited

https://gcc.gnu.org/g:26b47ebc613eaf4862049e8db48bdb6526b74009 commit 26b47ebc613eaf4862049e8db48bdb6526b74009 Author: Jeff Law Date: Tue Jun 18 06:40:40 2024 -0600 [to-be-committed,RISC-V] Improve bset generation when bit position is limited So more work in the ongoing effort

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix wrong patch application

https://gcc.gnu.org/g:66ed10c188665dd605f6266608f0b48d06ed1386 commit 66ed10c188665dd605f6266608f0b48d06ed1386 Author: Jeff Law Date: Tue Jun 18 12:10:57 2024 -0600 [committed] [RISC-V] Fix wrong patch application Applied the wrong patch which didn't have the final testsuite adjus

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vwsll combine on rv32 targets

https://gcc.gnu.org/g:6af88fe44f88bcceecc9f4ccc4d2103b71163a59 commit 6af88fe44f88bcceecc9f4ccc4d2103b71163a59 Author: Edwin Lu Date: Tue Jun 11 13:50:02 2024 -0700 RISC-V: Fix vwsll combine on rv32 targets On rv32 targets, vwsll_zext1_scalar_ would trigger an ice in maybe_leg

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move mode assertion out of conditional branch in emit_insn

https://gcc.gnu.org/g:6ba53a4174b4f368e24337f1ff876f5595871994 commit 6ba53a4174b4f368e24337f1ff876f5595871994 Author: Edwin Lu Date: Fri Jun 14 09:46:01 2024 -0700 RISC-V: Move mode assertion out of conditional branch in emit_insn When emitting insns, we have an early assertion t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11

https://gcc.gnu.org/g:e14ea14243f24bb3da97c498df3a43e46ace commit e14ea14243f24bb3da97c498df3a43e46ace Author: Pan Li Date: Tue Jun 18 16:14:23 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11 After the middle-end support the form 11 of unsigned SAT_SU

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

https://gcc.gnu.org/g:d7b67c6459575d6844e22ff01b135e8682d7b0cd commit d7b67c6459575d6844e22ff01b135e8682d7b0cd Author: Pan Li Date: Tue Jun 18 16:22:59 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12 After the middle-end support the form 12 of unsigned SAT_SU

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2

https://gcc.gnu.org/g:0adc6ac7e846c9b8758a5fbc53ee8e1c55854c67 commit 0adc6ac7e846c9b8758a5fbc53ee8e1c55854c67 Author: Pan Li Date: Mon Jun 17 14:39:10 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 2 After the middle-end support the form 2 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 5

https://gcc.gnu.org/g:a663f2a1f155ef1448e9ca83a97dbd566fc3d227 commit a663f2a1f155ef1448e9ca83a97dbd566fc3d227 Author: Pan Li Date: Mon Jun 17 16:31:26 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 5 After the middle-end support the form 5 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

https://gcc.gnu.org/g:d5fcee783f68d6768bd0760ba6f916dc948f33a1 commit d5fcee783f68d6768bd0760ba6f916dc948f33a1 Author: Pan Li Date: Mon Jun 17 22:10:31 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 6 After the middle-end support the form 6 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 8

https://gcc.gnu.org/g:205951602a8676076482414bb88696632ba1b435 commit 205951602a8676076482414bb88696632ba1b435 Author: Pan Li Date: Mon Jun 17 22:31:27 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 8 After the middle-end support the form 8 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3

https://gcc.gnu.org/g:cf7d79d0cba4f37905563694069907c20674a8be commit cf7d79d0cba4f37905563694069907c20674a8be Author: Pan Li Date: Wed Jun 19 18:56:51 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 After the middle-end support the form 3 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 3

https://gcc.gnu.org/g:39d1cd1aad83302d8e9ad7e5b76db0d301878a74 commit 39d1cd1aad83302d8e9ad7e5b76db0d301878a74 Author: Pan Li Date: Mon Jun 17 14:53:12 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 3 After the middle-end support the form 3 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 4

https://gcc.gnu.org/g:f5e626e5556b70bfe90d08b6dde5815573b88388 commit f5e626e5556b70bfe90d08b6dde5815573b88388 Author: Pan Li Date: Wed Jun 19 19:19:23 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 4 After the middle-end support the form 4 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 5

https://gcc.gnu.org/g:17cf1883c6761e1298034c77d26d219bf80f91d0 commit 17cf1883c6761e1298034c77d26d219bf80f91d0 Author: Pan Li Date: Wed Jun 19 19:44:52 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 5 After the middle-end support the form 5 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 4

https://gcc.gnu.org/g:423d8f4f525cfade3ff7564bc7abb0cbf6273b1a commit 423d8f4f525cfade3ff7564bc7abb0cbf6273b1a Author: Pan Li Date: Mon Jun 17 16:09:13 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 4 After the middle-end support the form 4 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 7

https://gcc.gnu.org/g:25e2c848ebc4b96079c751f2643baf1b307d155a commit 25e2c848ebc4b96079c751f2643baf1b307d155a Author: Pan Li Date: Wed Jun 19 20:28:11 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 7 After the middle-end support the form 7 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_ADD vector form 7

https://gcc.gnu.org/g:c518d080aad5bc464537db8ee7e4e7c9294a0c41 commit c518d080aad5bc464537db8ee7e4e7c9294a0c41 Author: Pan Li Date: Mon Jun 17 22:19:54 2024 +0800 RISC-V: Add testcases for unsigned .SAT_ADD vector form 7 After the middle-end support the form 7 of unsigned SAT_ADD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 9

https://gcc.gnu.org/g:cb0263d44bf3ed22abac3cf9fd08b06ad7e19382 commit cb0263d44bf3ed22abac3cf9fd08b06ad7e19382 Author: Pan Li Date: Wed Jun 19 21:02:27 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 9 After the middle-end support the form 9 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6

https://gcc.gnu.org/g:756b2965f7427f1faf8e8165de8d44940d1fc787 commit 756b2965f7427f1faf8e8165de8d44940d1fc787 Author: Pan Li Date: Wed Jun 19 20:15:27 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 6 After the middle-end support the form 6 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 10

https://gcc.gnu.org/g:d17f06644100361c717b179dc1adcf5bbaed3a39 commit d17f06644100361c717b179dc1adcf5bbaed3a39 Author: Pan Li Date: Wed Jun 19 21:14:31 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 10 After the middle-end support the form 10 of unsigned SAT_SU

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB vector form 8

https://gcc.gnu.org/g:26dfa8d05db2644e23b30e8f4e8a282c0cbc46b2 commit 26dfa8d05db2644e23b30e8f4e8a282c0cbc46b2 Author: Pan Li Date: Wed Jun 19 20:38:43 2024 +0800 RISC-V: Add testcases for unsigned .SAT_SUB vector form 8 After the middle-end support the form 8 of unsigned SAT_SUB

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils

https://gcc.gnu.org/g:08e6be28a37dae7b8c50e4ec3dedf3391ff89a06 commit 08e6be28a37dae7b8c50e4ec3dedf3391ff89a06 Author: Patrick O'Neill Date: Tue Jun 18 14:40:15 2024 -0700 RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils Binutils 2.42 and before don't support Zaamo/Zal

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2] RISC-V: Remove float vector eqne pattern

https://gcc.gnu.org/g:242fd71bb3d872bf0f81bcf559f86f77f7f1e63a commit 242fd71bb3d872bf0f81bcf559f86f77f7f1e63a Author: demin.han Date: Wed Jun 19 16:21:13 2024 -0600 [PATCH v2] RISC-V: Remove float vector eqne pattern We can unify eqne and other comparison operations. Tes

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Minor cleanup/improvement to bset/binv patterns

https://gcc.gnu.org/g:0dc80ffa05a126b4ef849ba57009113a9bce46f1 commit 0dc80ffa05a126b4ef849ba57009113a9bce46f1 Author: Jeff Law Date: Thu Jun 20 08:43:37 2024 -0600 [RISC-V] Minor cleanup/improvement to bset/binv patterns Changes since V1: Whitespace fixes noted by the li

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well

https://gcc.gnu.org/g:b5e20e71e2abc4dc4827675240e48fa6c5ea444f commit b5e20e71e2abc4dc4827675240e48fa6c5ea444f Author: Jeff Law Date: Sat Jun 22 10:39:51 2024 -0600 [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well > the test should probably also be skipped on -Oz: > >

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2] RISC-V: Remove integer vector eqne pattern

https://gcc.gnu.org/g:14303d1131332f55e9dfe7c082084b64b0ca891b commit 14303d1131332f55e9dfe7c082084b64b0ca891b Author: demin.han Date: Sat Jun 22 22:02:02 2024 -0600 [PATCH v2] RISC-V: Remove integer vector eqne pattern We can unify eqne and other comparison operations. T

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extracting INTVAL

https://gcc.gnu.org/g:e0b09c958f40e56da84c357a655096e005951cb7 commit e0b09c958f40e56da84c357a655096e005951cb7 Author: Jeff Law Date: Sun Jun 23 08:26:25 2024 -0600 [committed][RISC-V][PR target/114139] Verify we have a CONST_INT before extracting INTVAL Run-of-the-mill checking

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