[gcc r15-1992] RISC-V: Add SiFive extensions, xsfvcp and xsfcease

https://gcc.gnu.org/g:3ea47ea1fcab95fd1b80acc724fdbb27fc436985 commit r15-1992-g3ea47ea1fcab95fd1b80acc724fdbb27fc436985 Author: Kito Cheng Date: Tue Jul 9 15:50:57 2024 +0800 RISC-V: Add SiFive extensions, xsfvcp and xsfcease We have already upstreamed these extensions into binut

[gcc r15-1993] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]

https://gcc.gnu.org/g:63d7d5998e3768f6e3703c29e8774e8b54af108c commit r15-1993-g63d7d5998e3768f6e3703c29e8774e8b54af108c Author: xuli Date: Thu Jul 11 04:29:11 2024 + RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862] The reason is that in

[gcc r15-1994] fortran: Factor the evaluation of MINLOC/MAXLOC's BACK argument

https://gcc.gnu.org/g:a55d24b3cf7f4d07492bb8e6fcee557175b47ea3 commit r15-1994-ga55d24b3cf7f4d07492bb8e6fcee557175b47ea3 Author: Mikael Morin Date: Thu Jul 11 21:55:58 2024 +0200 fortran: Factor the evaluation of MINLOC/MAXLOC's BACK argument Move the evaluation of the BACK argume

[gcc r15-1995] RISC-V: NO_WARNING preferred else value for RVV

https://gcc.gnu.org/g:c6f38e5e6d900b8ed6a4f5c126d3197946cad4dd commit r15-1995-gc6f38e5e6d900b8ed6a4f5c126d3197946cad4dd Author: YunQiang Su Date: Thu Jul 11 20:43:54 2024 +0800 RISC-V: NO_WARNING preferred else value for RVV PR target/115840. In riscv_preferred_else_valu

[gcc r15-1996] [alpha] adjust MEM alignment for block move [PR115459]

https://gcc.gnu.org/g:ccfe7151803956d178947d0afda0bd66ce097275 commit r15-1996-gccfe7151803956d178947d0afda0bd66ce097275 Author: Alexandre Oliva Date: Fri Jul 12 05:42:07 2024 -0300 [alpha] adjust MEM alignment for block move [PR115459] Before issuing loads or stores for a block m

[gcc r15-1997] [libstdc++] [testsuite] require dfprt on some tests

https://gcc.gnu.org/g:26dfb3f2d30f6d49ed126add9d123dcc6566385f commit r15-1997-g26dfb3f2d30f6d49ed126add9d123dcc6566385f Author: Alexandre Oliva Date: Fri Jul 12 05:42:19 2024 -0300 [libstdc++] [testsuite] require dfprt on some tests On a target that doesn't enable decimal float c

[gcc r15-1998] aarch64: Avoid alloca in target attribute parsing

https://gcc.gnu.org/g:7bcef7532b10040bb82567136a208d0c4560767d commit r15-1998-g7bcef7532b10040bb82567136a208d0c4560767d Author: Richard Sandiford Date: Fri Jul 12 10:30:22 2024 +0100 aarch64: Avoid alloca in target attribute parsing The handling of the target attribute used alloc

[gcc r14-10411] RISC-V: NO_WARNING preferred else value for RVV

https://gcc.gnu.org/g:cff270707f107aff207f4afa73092a2d0731b032 commit r14-10411-gcff270707f107aff207f4afa73092a2d0731b032 Author: YunQiang Su Date: Thu Jul 11 20:43:54 2024 +0800 RISC-V: NO_WARNING preferred else value for RVV PR target/115840. In riscv_preferred_else_val

[gcc r11-11573] libstdc++: Add missing exports for ppc64le --with-long-double-format=ibm [PR105417]

https://gcc.gnu.org/g:30ffca55041518b76cfd59877250a740a615b5ba commit r11-11573-g30ffca55041518b76cfd59877250a740a615b5ba Author: Jonathan Wakely Date: Fri Apr 29 12:17:13 2022 +0100 libstdc++: Add missing exports for ppc64le --with-long-double-format=ibm [PR105417] The --with-lo

[gcc r14-10412] libstdc++: Fix std::to_array for trivial-ish types [PR115522]

https://gcc.gnu.org/g:21c8708ba638f57cf904c8af3355318d9cf0f9e0 commit r14-10412-g21c8708ba638f57cf904c8af3355318d9cf0f9e0 Author: Jonathan Wakely Date: Tue Jun 18 13:27:02 2024 +0100 libstdc++: Fix std::to_array for trivial-ish types [PR115522] Due to PR c++/85723 the std::is_triv

[gcc r14-10413] libstdc++: Fix unwanted #pragma messages from PSTL headers [PR113376]

https://gcc.gnu.org/g:d920658cbb200729b7c2ad069fa4b6498e028ff1 commit r14-10413-gd920658cbb200729b7c2ad069fa4b6498e028ff1 Author: Jonathan Wakely Date: Wed Jun 12 16:47:17 2024 +0100 libstdc++: Fix unwanted #pragma messages from PSTL headers [PR113376] When we rebased the PSTL on

[gcc r13-8908] libstdc++: Fix std::to_array for trivial-ish types [PR115522]

https://gcc.gnu.org/g:08463348c5cce84dc3c64ac4fbb20e2795ee104f commit r13-8908-g08463348c5cce84dc3c64ac4fbb20e2795ee104f Author: Jonathan Wakely Date: Tue Jun 18 13:27:02 2024 +0100 libstdc++: Fix std::to_array for trivial-ish types [PR115522] Due to PR c++/85723 the std::is_trivi

[gcc r15-1999] s390: Align *cjump_64 and *icjump_64

https://gcc.gnu.org/g:56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d commit r15-1999-g56de68aba6cb9cf3022d9e303eec6c6cdb49ad4d Author: Stefan Schulze Frielinghaus Date: Fri Jul 12 13:27:08 2024 +0200 s390: Align *cjump_64 and *icjump_64 During machine reorg we optimize backward jumps an

[gcc r15-2000] i386: Some AVX512 ternlog expansion refinements.

https://gcc.gnu.org/g:6b5d263f2c90c3e22cdf576970c94bca268c5296 commit r15-2000-g6b5d263f2c90c3e22cdf576970c94bca268c5296 Author: Roger Sayle Date: Fri Jul 12 12:30:56 2024 +0100 i386: Some AVX512 ternlog expansion refinements. This patch replaces the calls to force_reg in ix86_exp

[gcc r15-2001] s390: Fix output template for movv1qi

https://gcc.gnu.org/g:e6680d3f392f7f7cc2a1515276213e21e9eeab1c commit r15-2001-ge6680d3f392f7f7cc2a1515276213e21e9eeab1c Author: Stefan Schulze Frielinghaus Date: Fri Jul 12 13:40:19 2024 +0200 s390: Fix output template for movv1qi Although for instructions MVI and MVIY it does no

[gcc r15-2002] s390: Fully exploit vgm, vgbm, vrepi

https://gcc.gnu.org/g:61715e9340ab8941d40d62158fe437e9dbe3e068 commit r15-2002-g61715e9340ab8941d40d62158fe437e9dbe3e068 Author: Stefan Schulze Frielinghaus Date: Fri Jul 12 13:42:08 2024 +0200 s390: Fully exploit vgm, vgbm, vrepi Currently instructions vgm and vrepi are utilized

[gcc r15-2003] c++: Introduce USING_DECLs for non-function usings [PR114683]

https://gcc.gnu.org/g:d6bf4b1c93221118b3008a878ec508f6412dfc55 commit r15-2003-gd6bf4b1c93221118b3008a878ec508f6412dfc55 Author: Nathaniel Shead Date: Thu Jun 27 11:08:15 2024 +1000 c++: Introduce USING_DECLs for non-function usings [PR114683] With modules, a non-function using-de

[gcc r15-2004] c++/modules: Handle redefinitions of using-decls

https://gcc.gnu.org/g:1f7a21c6e85d553e7b5114e5ca1395118478dddf commit r15-2004-g1f7a21c6e85d553e7b5114e5ca1395118478dddf Author: Nathaniel Shead Date: Fri Jul 5 13:52:01 2024 +1000 c++/modules: Handle redefinitions of using-decls This fixes an ICE exposed by supporting exported no

[gcc r15-2005] c++/modules: Add testcase for fixed issue with usings [PR115798]

https://gcc.gnu.org/g:13757e50ff0b4e0dccfabc67b1322a2724bf3a5c commit r15-2005-g13757e50ff0b4e0dccfabc67b1322a2724bf3a5c Author: Nathaniel Shead Date: Fri Jul 12 22:59:19 2024 +1000 c++/modules: Add testcase for fixed issue with usings [PR115798] This issue was fixed by r15-2003-g

[gcc r15-2006] [RISC-V] Avoid unnecessary sign extension after memcmp

https://gcc.gnu.org/g:ae829a27785307232e4db0df6a30ca275941b613 commit r15-2006-gae829a27785307232e4db0df6a30ca275941b613 Author: Jeff Law Date: Fri Jul 12 07:53:41 2024 -0600 [RISC-V] Avoid unnecessary sign extension after memcmp Similar to the str[n]cmp work, this adjusts the blo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add SiFive extensions, xsfvcp and xsfcease

https://gcc.gnu.org/g:68a2ba4a346992f1399abb410c5fb788aa9bca25 commit 68a2ba4a346992f1399abb410c5fb788aa9bca25 Author: Kito Cheng Date: Tue Jul 9 15:50:57 2024 +0800 RISC-V: Add SiFive extensions, xsfvcp and xsfcease We have already upstreamed these extensions into binutils, and n

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]

https://gcc.gnu.org/g:d39d88ed512ae6affbd2f5128b1e55d92d8f5c0a commit d39d88ed512ae6affbd2f5128b1e55d92d8f5c0a Author: xuli Date: Thu Jul 11 04:29:11 2024 + RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862] The reason is that in the follow

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: NO_WARNING preferred else value for RVV

https://gcc.gnu.org/g:6322f7af2b8d41d5a298af66b5200d0c6ac79191 commit 6322f7af2b8d41d5a298af66b5200d0c6ac79191 Author: YunQiang Su Date: Thu Jul 11 20:43:54 2024 +0800 RISC-V: NO_WARNING preferred else value for RVV PR target/115840. In riscv_preferred_else_value, we crea

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Avoid unnecessary sign extension after memcmp

https://gcc.gnu.org/g:67116d59607d1897629deb3b95f7ccb9d4d875cb commit 67116d59607d1897629deb3b95f7ccb9d4d875cb Author: Jeff Law Date: Fri Jul 12 07:53:41 2024 -0600 [RISC-V] Avoid unnecessary sign extension after memcmp Similar to the str[n]cmp work, this adjusts the block compare

[gcc r15-2007] modula2: bootstrap fix for string and vector headers.

https://gcc.gnu.org/g:f4047a8614d2215e0d6acf071c521ac08ab1bbb2 commit r15-2007-gf4047a8614d2215e0d6acf071c521ac08ab1bbb2 Author: FX Coudert Date: Fri Jul 12 15:39:50 2024 +0100 modula2: bootstrap fix for string and vector headers. This patch fixes the include of headers ( and ) wh

[gcc r15-2008] rtl-ssa: Fix prev_any_insn [PR115785]

https://gcc.gnu.org/g:6e7053a641393211f52c176e540c8922288ab8db commit r15-2008-g6e7053a641393211f52c176e540c8922288ab8db Author: Richard Sandiford Date: Fri Jul 12 15:50:36 2024 +0100 rtl-ssa: Fix prev_any_insn [PR115785] Bit of a brown paper bag issue, but: due to the representat

[gcc r15-2009] Fix Xcode 16 build break with NULL != nullptr

https://gcc.gnu.org/g:08776bef53835ff6318ecfeade8f6c6896ffd81f commit r15-2009-g08776bef53835ff6318ecfeade8f6c6896ffd81f Author: Daniel Bertalan Date: Tue Jul 9 23:34:46 2024 +0200 Fix Xcode 16 build break with NULL != nullptr As of Xcode 16 beta 2 with the macOS 15 SDK, each re-i

[gcc(refs/users/meissner/heads/work171-bugs)] Disable adding -mvsx when checking for float128 support.

https://gcc.gnu.org/g:0a9e57995990885028fc6af8a53513794890 commit 0a9e57995990885028fc6af8a53513794890 Author: Michael Meissner Date: Fri Jul 12 12:00:20 2024 -0400 Disable adding -mvsx when checking for float128 support. 2024-07-12 Michael Meissner gcc/testsui

[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*

https://gcc.gnu.org/g:a2af9e19c83edeca6fa8a6502fea697715678e95 commit a2af9e19c83edeca6fa8a6502fea697715678e95 Author: Michael Meissner Date: Fri Jul 12 12:01:12 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 17 - 1 file changed, 16 insertions(+), 1 deletio

[gcc(refs/users/meissner/heads/work171-bugs)] Use -mcpu=native instead of -mcpu=power9 when checking for float128 hardware support.

https://gcc.gnu.org/g:89c9983b9157b8eb443a16561ad9a55d2cb10c66 commit 89c9983b9157b8eb443a16561ad9a55d2cb10c66 Author: Michael Meissner Date: Fri Jul 12 14:12:28 2024 -0400 Use -mcpu=native instead of -mcpu=power9 when checking for float128 hardware support. 2024-07-12 Michael M

[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*

https://gcc.gnu.org/g:5414c9a058837198fa9da1da672e28dd84da1f1d commit 5414c9a058837198fa9da1da672e28dd84da1f1d Author: Michael Meissner Date: Fri Jul 12 14:13:30 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 14 ++ 1 file changed, 14 insertions(+) diff --git a

[gcc r15-2010] doc: remove @opindex for fconcepts-ts

https://gcc.gnu.org/g:b3d4a021eff6353a099f800857d3080a7cd27003 commit r15-2010-gb3d4a021eff6353a099f800857d3080a7cd27003 Author: Marek Polacek Date: Fri Jul 12 14:40:59 2024 -0400 doc: remove @opindex for fconcepts-ts We're getting complaints from the CI system about this removed

[gcc r15-2011] [PR rtl-optimization/115876] Fix one of two ubsan reported issues in new ext-dce.cc code

https://gcc.gnu.org/g:a6f551d079de1d151b272bcdd3d42316857c9d4e commit r15-2011-ga6f551d079de1d151b272bcdd3d42316857c9d4e Author: Jeff Law Date: Fri Jul 12 13:11:33 2024 -0600 [PR rtl-optimization/115876] Fix one of two ubsan reported issues in new ext-dce.cc code David Binderman

[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes

https://gcc.gnu.org/g:79427fed78d2531db6adc592f63d47ceaf0d5b49 commit 79427fed78d2531db6adc592f63d47ceaf0d5b49 Author: Michael Meissner Date: Fri Jul 12 19:27:38 2024 -0400 Revert changes Diff: --- gcc/testsuite/lib/target-supports.exp | 8 libgcc/config.host

[gcc r15-2012] doc: Update GNU Modula 2 mailing list links

https://gcc.gnu.org/g:dd2840a45e94946cc4a831cf9a08c708f8a9e1ae commit r15-2012-gdd2840a45e94946cc4a831cf9a08c708f8a9e1ae Author: Gerald Pfeifer Date: Sat Jul 13 01:40:15 2024 +0200 doc: Update GNU Modula 2 mailing list links gcc: * doc/gm2.texi (Community): Update list

[gcc(refs/users/meissner/heads/work171-bugs)] Add checks for building the IEEE 128-bit libgcc support if VSX is not available.

https://gcc.gnu.org/g:097f2463d8c78602186feb731fd8732dce9f3e7c commit 097f2463d8c78602186feb731fd8732dce9f3e7c Author: Michael Meissner Date: Fri Jul 12 20:04:37 2024 -0400 Add checks for building the IEEE 128-bit libgcc support if VSX is not available. In the past, we would buil

[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes

https://gcc.gnu.org/g:d317a05ebc91cb1da2a89d9ea9fe5f7dc0747b8a commit d317a05ebc91cb1da2a89d9ea9fe5f7dc0747b8a Author: Michael Meissner Date: Fri Jul 12 20:06:45 2024 -0400 Revert changes Diff: --- gcc/ChangeLog.bugs | 56 -- 1 file cha

[gcc(refs/users/meissner/heads/work171-bugs)] Revert changes

https://gcc.gnu.org/g:78633b506f6673f1b3bfcd39df55933ae4f1d4eb commit 78633b506f6673f1b3bfcd39df55933ae4f1d4eb Author: Michael Meissner Date: Fri Jul 12 20:27:11 2024 -0400 Revert changes Diff: --- gcc/ChangeLog.bugs | 24 +- libgcc/config.host | 12 - libgcc/co

[gcc(refs/users/meissner/heads/work171-bugs)] Use -mcpu=power7 if needed and not -mvsx to build float128 support.

https://gcc.gnu.org/g:a92ecfb87c48c9a4c7a7e12d5ec1491198ea0e18 commit a92ecfb87c48c9a4c7a7e12d5ec1491198ea0e18 Author: Michael Meissner Date: Fri Jul 12 20:58:20 2024 -0400 Use -mcpu=power7 if needed and not -mvsx to build float128 support. 2024-07-12 Michael Meissner

[gcc(refs/users/meissner/heads/work171-bugs)] Update ChangeLog.*

https://gcc.gnu.org/g:de57e5fc86709f9e18d9d56b599d3d13104f94be commit de57e5fc86709f9e18d9d56b599d3d13104f94be Author: Michael Meissner Date: Fri Jul 12 20:59:30 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 21 + 1 file changed, 21 insertions(+) diff

[gcc r14-10415] s390: Align *cjump_64 and *icjump_64

https://gcc.gnu.org/g:cd11413ff7c4353a3e336db415304f788d23a393 commit r14-10415-gcd11413ff7c4353a3e336db415304f788d23a393 Author: Stefan Schulze Frielinghaus Date: Sat Jul 13 08:01:51 2024 +0200 s390: Align *cjump_64 and *icjump_64 During machine reorg we optimize backward jumps a

[gcc r14-10416] s390: Fix output template for movv1qi

https://gcc.gnu.org/g:5ade7afdefe7a5179c6a139103885c2cf911d9d0 commit r14-10416-g5ade7afdefe7a5179c6a139103885c2cf911d9d0 Author: Stefan Schulze Frielinghaus Date: Sat Jul 13 08:01:59 2024 +0200 s390: Fix output template for movv1qi Although for instructions MVI and MVIY it does n

[gcc r14-10417] LoongArch: TFmode is not allowed to be stored in the float register.

https://gcc.gnu.org/g:89f9342980b7976f98ba43fac6a64a7a2214b6e6 commit r14-10417-g89f9342980b7976f98ba43fac6a64a7a2214b6e6 Author: Lulu Cheng Date: Thu Jul 4 10:37:26 2024 +0800 LoongArch: TFmode is not allowed to be stored in the float register. PR target/115752 g

[gcc r13-8910] LoongArch: TFmode is not allowed to be stored in the float register.

https://gcc.gnu.org/g:616c3290785c204b3019e7aaff8a7d9bb425d336 commit r13-8910-g616c3290785c204b3019e7aaff8a7d9bb425d336 Author: Lulu Cheng Date: Thu Jul 4 10:37:26 2024 +0800 LoongArch: TFmode is not allowed to be stored in the float register. PR target/115752 gc