https://gcc.gnu.org/g:ccfe7151803956d178947d0afda0bd66ce097275
commit r15-1996-gccfe7151803956d178947d0afda0bd66ce097275 Author: Alexandre Oliva <ol...@adacore.com> Date: Fri Jul 12 05:42:07 2024 -0300 [alpha] adjust MEM alignment for block move [PR115459] Before issuing loads or stores for a block move, adjust the MEM alignments if analysis of the addresses enabled the inference of stricter alignment. This ensures that the MEMs are sufficiently aligned for the corresponding insns, which avoids trouble in case of e.g. substitutions into SUBREGs. for gcc/ChangeLog PR target/115459 * config/alpha/alpha.cc (alpha_expand_block_move): Adjust MEMs to match inferred alignment. Diff: --- gcc/config/alpha/alpha.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc index a6fe95e71778..74631a416935 100644 --- a/gcc/config/alpha/alpha.cc +++ b/gcc/config/alpha/alpha.cc @@ -3820,6 +3820,12 @@ alpha_expand_block_move (rtx operands[]) else if (a >= 16 && c % 2 == 0) src_align = 16; } + + if (MEM_P (orig_src) && MEM_ALIGN (orig_src) < src_align) + { + orig_src = shallow_copy_rtx (orig_src); + set_mem_align (orig_src, src_align); + } } tmp = XEXP (orig_dst, 0); @@ -3841,6 +3847,12 @@ alpha_expand_block_move (rtx operands[]) else if (a >= 16 && c % 2 == 0) dst_align = 16; } + + if (MEM_P (orig_dst) && MEM_ALIGN (orig_dst) < dst_align) + { + orig_dst = shallow_copy_rtx (orig_dst); + set_mem_align (orig_dst, dst_align); + } } ofs = 0;