[gcc r16-1196] [i386] Improve "movcc" expander for DImode immediates [PR120553]

https://gcc.gnu.org/g:ed57e5de634eda91f32e0e61724d8f103ef648dd commit r16-1196-ged57e5de634eda91f32e0e61724d8f103ef648dd Author: Uros Bizjak Date: Thu Jun 5 22:53:35 2025 +0200 [i386] Improve "movcc" expander for DImode immediates [PR120553] "movcc" expander uses x86_64_general_op

[gcc r16-393] i386: Do not use explicit operands for MOVS instructions [PR120019]

https://gcc.gnu.org/g:c182f4d14d65b3e012ad65b5014d86352fabc86f commit r16-393-gc182f4d14d65b3e012ad65b5014d86352fabc86f Author: Uros Bizjak Date: Mon May 5 13:59:43 2025 +0200 i386: Do not use explicit operands for MOVS instructions [PR120019] Some assemblers do not support MOVS i

[gcc r16-285] i386: Disable string insn from non-default AS for Pmode != word_mode [PR111657]

https://gcc.gnu.org/g:69669180d29cc420b1b1ac86530a4f9573748d81 commit r16-285-g69669180d29cc420b1b1ac86530a4f9573748d81 Author: Uros Bizjak Date: Tue Apr 29 18:08:05 2025 +0200 i386: Disable string insn from non-default AS for Pmode != word_mode [PR111657] 0x67 prefix is applied

[gcc r16-276] i386: Allow string instructions from non-default address space [PR111657]

https://gcc.gnu.org/g:aa29654b1128a572c97fcaba94095f493662a0db commit r16-276-gaa29654b1128a572c97fcaba94095f493662a0db Author: Uros Bizjak Date: Tue Apr 29 10:25:45 2025 +0200 i386: Allow string instructions from non-default address space [PR111657] MOVS instructions allow segmen

[gcc r16-272] i386: Skip sub-RTXes of memory operand in ix86_update_stack_alignment

https://gcc.gnu.org/g:1547c0a5a46a9730547c36b6e8fccc0a25123f1a commit r16-272-g1547c0a5a46a9730547c36b6e8fccc0a25123f1a Author: Uros Bizjak Date: Tue Apr 29 08:28:37 2025 +0200 i386: Skip sub-RTXes of memory operand in ix86_update_stack_alignment Skip sub-RTXes of the memory opera

[gcc r14-11648] i386: Enable -mnop-mcount for -fpic with PLTs [PR119386]

https://gcc.gnu.org/g:203bce172aba0f09cea8a7853403c99956674b6a commit r14-11648-g203bce172aba0f09cea8a7853403c99956674b6a Author: Ard Biesheuvel Date: Thu Apr 10 14:26:41 2025 +0200 i386: Enable -mnop-mcount for -fpic with PLTs [PR119386] -mnop-mcount can be trivially enabled for

[gcc r14-11647] i386: Prefer PLT indirection for __fentry__ calls under -fPIC [PR119386]

https://gcc.gnu.org/g:1500a9c9cd7e2a264570d8380789981d77041cc2 commit r14-11647-g1500a9c9cd7e2a264570d8380789981d77041cc2 Author: Ard Biesheuvel Date: Thu Apr 10 14:26:40 2025 +0200 i386: Prefer PLT indirection for __fentry__ calls under -fPIC [PR119386] Commit bde21de1205 ("i386:

[gcc r15-9530] i386: Prefer PLT indirection for __fentry__ calls under -fPIC [PR119386]

https://gcc.gnu.org/g:9b0ae0a8d70603960f3c578d261efd18c02b803f commit r15-9530-g9b0ae0a8d70603960f3c578d261efd18c02b803f Author: Ard Biesheuvel Date: Thu Apr 10 14:26:40 2025 +0200 i386: Prefer PLT indirection for __fentry__ calls under -fPIC [PR119386] Commit bde21de1205 ("i386:

[gcc r15-9531] i386: Enable -mnop-mcount for -fpic with PLTs [PR119386]

https://gcc.gnu.org/g:6b4569a3ebdd0df44d87d67a18272ec0b878f2ee commit r15-9531-g6b4569a3ebdd0df44d87d67a18272ec0b878f2ee Author: Ard Biesheuvel Date: Thu Apr 10 14:26:41 2025 +0200 i386: Enable -mnop-mcount for -fpic with PLTs [PR119386] -mnop-mcount can be trivially enabled for -

[gcc r12-11035] rtl-optimization/119689 - compare-debug failure with LRA

https://gcc.gnu.org/g:6675cf3abd09731ec8360ba8ac8928b63b33b7bb commit r12-11035-g6675cf3abd09731ec8360ba8ac8928b63b33b7bb Author: Richard Biener Date: Wed Apr 9 14:36:19 2025 +0200 rtl-optimization/119689 - compare-debug failure with LRA The previous change to fix LRA rematerializ

[gcc r13-9520] [PR115568][LRA]: Use more strict output reload check in rematerialization

https://gcc.gnu.org/g:7578243dcd42855e4a8ae85ef8ab2598f0f6cbe9 commit r13-9520-g7578243dcd42855e4a8ae85ef8ab2598f0f6cbe9 Author: Vladimir N. Makarov Date: Wed Feb 5 14:23:23 2025 -0500 [PR115568][LRA]: Use more strict output reload check in rematerialization In this PR case LRA

[gcc r12-11034] [PR115568][LRA]: Use more strict output reload check in rematerialization

https://gcc.gnu.org/g:3232e151654f3998926c8e82a2ffd911c6e74df4 commit r12-11034-g3232e151654f3998926c8e82a2ffd911c6e74df4 Author: Vladimir N. Makarov Date: Wed Feb 5 14:23:23 2025 -0500 [PR115568][LRA]: Use more strict output reload check in rematerialization In this PR case LRA

[gcc r13-9521] rtl-optimization/119689 - compare-debug failure with LRA

https://gcc.gnu.org/g:1a2e39a5349a36deea33f5fb078edfe658daaf50 commit r13-9521-g1a2e39a5349a36deea33f5fb078edfe658daaf50 Author: Richard Biener Date: Wed Apr 9 14:36:19 2025 +0200 rtl-optimization/119689 - compare-debug failure with LRA The previous change to fix LRA rematerializa

[gcc r14-11600] rtl-optimization/119689 - compare-debug failure with LRA

https://gcc.gnu.org/g:31e31bbeea657496eaa2d8bf629f6e61c6cd1266 commit r14-11600-g31e31bbeea657496eaa2d8bf629f6e61c6cd1266 Author: Richard Biener Date: Wed Apr 9 14:36:19 2025 +0200 rtl-optimization/119689 - compare-debug failure with LRA The previous change to fix LRA rematerializ

[gcc r14-11599] [PR115568][LRA]: Use more strict output reload check in rematerialization

https://gcc.gnu.org/g:dc93babdcceb4293e4a64c0770786dc8aefc1a4e commit r14-11599-gdc93babdcceb4293e4a64c0770786dc8aefc1a4e Author: Vladimir N. Makarov Date: Wed Feb 5 14:23:23 2025 -0500 [PR115568][LRA]: Use more strict output reload check in rematerialization In this PR case LRA

[gcc r15-9338] testsuite/x86: Correctly escape asterisk in scan-assembler

https://gcc.gnu.org/g:3aca82bc3a3ab62f96bf6ebe9e38ccc78cc8dca8 commit r15-9338-g3aca82bc3a3ab62f96bf6ebe9e38ccc78cc8dca8 Author: Uros Bizjak Date: Wed Apr 9 16:21:18 2025 +0200 testsuite/x86: Correctly escape asterisk in scan-assembler Asterisk in []* regexp applies to bracket exp

[gcc r15-8989] i386: Fix offset calculation in ix86_redzone_clobber

https://gcc.gnu.org/g:2af32814cf2ba3c632fd5a3f69f275613383723d commit r15-8989-g2af32814cf2ba3c632fd5a3f69f275613383723d Author: Uros Bizjak Date: Thu Mar 27 21:25:36 2025 +0100 i386: Fix offset calculation in ix86_redzone_clobber plus_constant expects integer as its third argumen

[gcc r12-10977] testsuite: Add tests for already fixed PR [PR119071]

https://gcc.gnu.org/g:9496f5088111d9330bba2659b024f7e7a2175b4b commit r12-10977-g9496f5088111d9330bba2659b024f7e7a2175b4b Author: Jakub Jelinek Date: Tue Mar 4 09:52:22 2025 +0100 testsuite: Add tests for already fixed PR [PR119071] Uros' r15-7793 fixed this PR as well, I'm just c

[gcc r13-9413] combine: Discard REG_UNUSED note in i2 when register is also referenced in i3 [PR118739]

https://gcc.gnu.org/g:3634a7d15d94590cef313f503a32d4698276fd04 commit r13-9413-g3634a7d15d94590cef313f503a32d4698276fd04 Author: Uros Bizjak Date: Wed Feb 12 11:19:57 2025 +0100 combine: Discard REG_UNUSED note in i2 when register is also referenced in i3 [PR118739] The combine p

[gcc r12-10976] combine: Discard REG_UNUSED note in i2 when register is also referenced in i3 [PR118739]

https://gcc.gnu.org/g:77172598dcb07b6ea71f4549917f2647eb34f38a commit r12-10976-g77172598dcb07b6ea71f4549917f2647eb34f38a Author: Uros Bizjak Date: Wed Feb 12 11:19:57 2025 +0100 combine: Discard REG_UNUSED note in i2 when register is also referenced in i3 [PR118739] The combine

[gcc r13-9414] testsuite: Add tests for already fixed PR [PR119071]

https://gcc.gnu.org/g:5ab16e594f29f2c1b4f4b54b2174de171be6c2a6 commit r13-9414-g5ab16e594f29f2c1b4f4b54b2174de171be6c2a6 Author: Jakub Jelinek Date: Tue Mar 4 09:52:22 2025 +0100 testsuite: Add tests for already fixed PR [PR119071] Uros' r15-7793 fixed this PR as well, I'm just co

[gcc r14-11377] testsuite: Add tests for already fixed PR [PR119071]

https://gcc.gnu.org/g:e79fc5a7bc9958c95fd09928188f5aa6c051d4c1 commit r14-11377-ge79fc5a7bc9958c95fd09928188f5aa6c051d4c1 Author: Jakub Jelinek Date: Tue Mar 4 09:52:22 2025 +0100 testsuite: Add tests for already fixed PR [PR119071] Uros' r15-7793 fixed this PR as well, I'm just c

[gcc r14-11376] combine: Discard REG_UNUSED note in i2 when register is also referenced in i3 [PR118739]

https://gcc.gnu.org/g:b7b8307893ef0b6a2a0565d75af831cca4c9511a commit r14-11376-gb7b8307893ef0b6a2a0565d75af831cca4c9511a Author: Uros Bizjak Date: Wed Feb 12 11:19:57 2025 +0100 combine: Discard REG_UNUSED note in i2 when register is also referenced in i3 [PR118739] The combine

[gcc r15-7795] Revert "combine: Reverse negative logic in ternary operator"

https://gcc.gnu.org/g:ebc6c54e1f84170d591aa44c4a589c0164436a02 commit r15-7795-gebc6c54e1f84170d591aa44c4a589c0164436a02 Author: Uros Bizjak Date: Mon Mar 3 17:52:04 2025 +0100 Revert "combine: Reverse negative logic in ternary operator" This reverts commit f1c30c6213fb228f1e8b597

[gcc r15-7794] combine: Reverse negative logic in ternary operator

https://gcc.gnu.org/g:f1c30c6213fb228f1e8b5973d10c868b834a4acd commit r15-7794-gf1c30c6213fb228f1e8b5973d10c868b834a4acd Author: Uros Bizjak Date: Mon Mar 3 17:04:54 2025 +0100 combine: Reverse negative logic in ternary operator Reverse negative logic in !a ? b : c to become a ? c

[gcc r15-7793] combine: Discard REG_UNUSED note in i2 when register is also referenced in i3 [PR118739]

https://gcc.gnu.org/g:a92dc3fe31c95d56019b2fb95a58414bca06241f commit r15-7793-ga92dc3fe31c95d56019b2fb95a58414bca06241f Author: Uros Bizjak Date: Wed Feb 12 11:19:57 2025 +0100 combine: Discard REG_UNUSED note in i2 when register is also referenced in i3 [PR118739] The combine p

[gcc r15-7609] libgcc: i386/linux-unwind.h: always rely on sys/ucontext.h

https://gcc.gnu.org/g:e129b8d7682c9a6c4d874f58de142543d3804169 commit r15-7609-ge129b8d7682c9a6c4d874f58de142543d3804169 Author: Roman Kagan Date: Thu Jan 2 16:32:17 2025 +0100 libgcc: i386/linux-unwind.h: always rely on sys/ucontext.h When gcc is built for x86_64-linux-musl targe

[gcc r15-7594] i386: Simplify PARALLEL RTX scan in ix86_find_all_reg_use

https://gcc.gnu.org/g:565d4e755498ad2b5ed55e368ef61eb9511cda3a commit r15-7594-g565d4e755498ad2b5ed55e368ef61eb9511cda3a Author: Uros Bizjak Date: Mon Feb 17 20:47:14 2025 +0100 i386: Simplify PARALLEL RTX scan in ix86_find_all_reg_use UNSPEC and UNSPEC_VOLATILE never store. Remov

[gcc r15-7593] middle-end: Fixup constant integers when expanding __builtin_crc [PR118288]

https://gcc.gnu.org/g:09684c53bca7dad47d36875b359e83551f9015fd commit r15-7593-g09684c53bca7dad47d36875b359e83551f9015fd Author: Uros Bizjak Date: Sun Feb 16 22:01:27 2025 +0100 middle-end: Fixup constant integers when expanding __builtin_crc [PR118288] Constant integers with MSB

[gcc r15-7335] i386: Fix and improve TARGET_INDIRECT_BRANCH_REGISTER handling some more

https://gcc.gnu.org/g:214224c4973bfb76f73a7efff29c5823eef31194 commit r15-7335-g214224c4973bfb76f73a7efff29c5823eef31194 Author: Uros Bizjak Date: Mon Feb 3 21:01:51 2025 +0100 i386: Fix and improve TARGET_INDIRECT_BRANCH_REGISTER handling some more gcc/ChangeLog:

[gcc r12-10920] i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067]

https://gcc.gnu.org/g:9a1efd1ee2509abb93878bd911d8c07143b10e33 commit r12-10920-g9a1efd1ee2509abb93878bd911d8c07143b10e33 Author: Uros Bizjak Date: Mon Jan 20 16:19:43 2025 +0100 i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067] SImode and DImode mov

[gcc r13-9335] i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067]

https://gcc.gnu.org/g:1fe03d184723ee942c74b5e6f8cde45d2fcdcd60 commit r13-9335-g1fe03d184723ee942c74b5e6f8cde45d2fcdcd60 Author: Uros Bizjak Date: Mon Jan 20 16:12:26 2025 +0100 i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067] SImode and DImode move

[gcc r14-11228] i386: Reorder *movdi_internal ISA attribute by ascending alternative index

https://gcc.gnu.org/g:9a1daeb9cd5fb9093c031af85d9efa59ea5cd61a commit r14-11228-g9a1daeb9cd5fb9093c031af85d9efa59ea5cd61a Author: Uros Bizjak Date: Sun Jan 19 22:29:21 2025 +0100 i386: Reorder *movdi_internal ISA attribute by ascending alternative index Reorder ISA attribute by as

[gcc r14-11227] i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067]

https://gcc.gnu.org/g:94338cdf59531edb9ac944011c95d777b113ae93 commit r14-11227-g94338cdf59531edb9ac944011c95d777b113ae93 Author: Uros Bizjak Date: Fri Dec 20 16:16:15 2024 +0100 i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067] SImode and DImode mov

[gcc r15-7034] i386: Reorder *movdi_internal ISA attribute by ascending alternative index

https://gcc.gnu.org/g:9d4b1e3772547c8c836638d09fc9a84c3c73e277 commit r15-7034-g9d4b1e3772547c8c836638d09fc9a84c3c73e277 Author: Uros Bizjak Date: Sun Jan 19 22:29:21 2025 +0100 i386: Reorder *movdi_internal ISA attribute by ascending alternative index Reorder ISA attribute by asc

[gcc r15-7033] i386/testsuite: Fix gcc.target/i386/pr118067*.c tests

https://gcc.gnu.org/g:7026436fb67854c7c83f0672ed0271c34d6e3d50 commit r15-7033-g7026436fb67854c7c83f0672ed0271c34d6e3d50 Author: Uros Bizjak Date: Sun Jan 19 20:23:20 2025 +0100 i386/testsuite: Fix gcc.target/i386/pr118067*.c tests These tests use int128 type, so require target in

[gcc r15-6394] i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067]

https://gcc.gnu.org/g:219ddae16f9d724baeff86934f8981aa5ef7b95f commit r15-6394-g219ddae16f9d724baeff86934f8981aa5ef7b95f Author: Uros Bizjak Date: Fri Dec 20 16:16:15 2024 +0100 i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067] SImode and DImode move

[gcc r15-6289] i386: Fix tabs vs. spaces in mmx.md

https://gcc.gnu.org/g:56f1863ade1bf416e09da305615ecb2ae04602a8 commit r15-6289-g56f1863ade1bf416e09da305615ecb2ae04602a8 Author: Uros Bizjak Date: Mon Dec 16 20:58:09 2024 +0100 i386: Fix tabs vs. spaces in mmx.md gcc/ChangeLog: * config/i386/mmx.md: Fix tabs vs.

[gcc r15-6288] i386: Add HImode to VALID_SSE2_REG_MODE

https://gcc.gnu.org/g:9d96b03c1edbd5cd47566fbcca61c5d4d5b01625 commit r15-6288-g9d96b03c1edbd5cd47566fbcca61c5d4d5b01625 Author: Uros Bizjak Date: Mon Dec 16 20:51:07 2024 +0100 i386: Add HImode to VALID_SSE2_REG_MODE Move explicit Himode handling for SSE2 XMM regnos from ix86

[gcc r14-11073] i386: Fix unwanted fwprop to 3dNOW! insn [PR117926]

https://gcc.gnu.org/g:c08ae0cf33e7e8339456a4a9ba0c494600eadcf3 commit r14-11073-gc08ae0cf33e7e8339456a4a9ba0c494600eadcf3 Author: Uros Bizjak Date: Fri Dec 6 16:59:16 2024 +0100 i386: Fix unwanted fwprop to 3dNOW! insn [PR117926] The compiler is able to forward propagate a partial

[gcc r15-5994] i386: Add missing part from my previous commit.

https://gcc.gnu.org/g:171aef2974d25c427720a07b1a619ed4a664ce13 commit r15-5994-g171aef2974d25c427720a07b1a619ed4a664ce13 Author: Uros Bizjak Date: Fri Dec 6 19:21:53 2024 +0100 i386: Add missing part from my previous commit. gcc/ChangeLog: * config/i386/i386.cc (i

[gcc r15-5993] i386: Fix gcc.target/i386/pr101716.c (and some related cleanups)

https://gcc.gnu.org/g:6a8ff7de756bc2e048f0a70edf69d6863f43233c commit r15-5993-g6a8ff7de756bc2e048f0a70edf69d6863f43233c Author: Uros Bizjak Date: Fri Dec 6 19:00:34 2024 +0100 i386: Fix gcc.target/i386/pr101716.c (and some related cleanups) Fix pr101716.c testcase scan-assembler

[gcc r15-5991] i386: Fix unwanted fwprop to 3dNOW! insn [PR117926]

https://gcc.gnu.org/g:1acc5cffbb04949a790d6e1a34a46ec71418a57b commit r15-5991-g1acc5cffbb04949a790d6e1a34a46ec71418a57b Author: Uros Bizjak Date: Fri Dec 6 16:59:16 2024 +0100 i386: Fix unwanted fwprop to 3dNOW! insn [PR117926] The compiler is able to forward propagate a partial

[gcc r15-5950] i386: Fix addcarry/subborrow issues [PR117860]

https://gcc.gnu.org/g:b3cb0c3302a7c16e661a08c15c897c8f7bbb5d23 commit r15-5950-gb3cb0c3302a7c16e661a08c15c897c8f7bbb5d23 Author: Uros Bizjak Date: Thu Dec 5 17:02:46 2024 +0100 i386: Fix addcarry/subborrow issues [PR117860] Fix several things to enable combine to handle addcarry/s

[gcc r15-5763] i386: Macroize compound shift patterns some more

https://gcc.gnu.org/g:ab2cce593ef6085a5f517cdca2520c5c44acbfad commit r15-5763-gab2cce593ef6085a5f517cdca2520c5c44acbfad Author: Uros Bizjak Date: Thu Nov 28 17:44:03 2024 +0100 i386: Macroize compound shift patterns some more Merge ashl and compound define_insn_and_split pat

[gcc r14-10996] [PR117105][LRA]: Use unique value reload pseudo for early clobber operand

https://gcc.gnu.org/g:ea36e9d17971210762580489b71b05e7bf7faa2e commit r14-10996-gea36e9d17971210762580489b71b05e7bf7faa2e Author: Vladimir N. Makarov Date: Mon Nov 25 16:09:00 2024 -0500 [PR117105][LRA]: Use unique value reload pseudo for early clobber operand LRA did not generate

[gcc r14-10995] [PR114942][LRA]: Don't reuse input reload reg of inout early clobber operand

https://gcc.gnu.org/g:196ab7853ef5dc225833a914491add0a3adeaf9d commit r14-10995-g196ab7853ef5dc225833a914491add0a3adeaf9d Author: Vladimir N. Makarov Date: Fri May 10 09:15:50 2024 -0400 [PR114942][LRA]: Don't reuse input reload reg of inout early clobber operand The insn in que

[gcc r15-5731] i386: x86 can use x >> y for x >> 32+y [PR36503]

https://gcc.gnu.org/g:093584abb854559393e36cd4cdcf9dc4862dd046 commit r15-5731-g093584abb854559393e36cd4cdcf9dc4862dd046 Author: Uros Bizjak Date: Wed Nov 27 20:45:25 2024 +0100 i386: x86 can use x >> y for x >> 32+y [PR36503] x86 targets mask 32-bit shifts with a 5-bit mask (and

[gcc r15-5657] i386: Generalize x >> 32-y to x >> -y conversion with multiples of 32

https://gcc.gnu.org/g:551fd4d5c98859522dd21db6fbb39fceac3936b2 commit r15-5657-g551fd4d5c98859522dd21db6fbb39fceac3936b2 Author: Uros Bizjak Date: Mon Nov 25 20:04:38 2024 +0100 i386: Generalize x >> 32-y to x >> -y conversion with multiples of 32 Optimize also cases where immedia

[gcc r15-5636] testsuite/x86: Add -mfpmath=sse to add_options_for_float16

https://gcc.gnu.org/g:04f0652c91435987e137a85013a601b8b51d5662 commit r15-5636-g04f0652c91435987e137a85013a601b8b51d5662 Author: Uros Bizjak Date: Sun Nov 24 22:18:31 2024 +0100 testsuite/x86: Add -mfpmath=sse to add_options_for_float16 Add -mfpmath=sse to add_options_for_float16

[gcc r15-5635] i386: x86 can use x >> -y for x >> 32-y [PR36503]

https://gcc.gnu.org/g:1ff69000b50e8ac184e925af71e794e7c3d5d2a6 commit r15-5635-g1ff69000b50e8ac184e925af71e794e7c3d5d2a6 Author: Uros Bizjak Date: Sun Nov 24 22:00:18 2024 +0100 i386: x86 can use x >> -y for x >> 32-y [PR36503] x86 targets mask 32-bit shifts with a 5-bit mask (and

[gcc r13-9201] i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357]

https://gcc.gnu.org/g:724dbdad0d23e2d460ca49aea3be5673e7ad80d1 commit r13-9201-g724dbdad0d23e2d460ca49aea3be5673e7ad80d1 Author: Uros Bizjak Date: Mon Nov 18 22:38:46 2024 +0100 i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357] __builtin_ia32_rsqrtsf2 expander generate

[gcc r12-10822] i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357]

https://gcc.gnu.org/g:540c0c7c424a43c1d99dd22f6db020cc0cd6eaea commit r12-10822-g540c0c7c424a43c1d99dd22f6db020cc0cd6eaea Author: Uros Bizjak Date: Mon Nov 18 22:38:46 2024 +0100 i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357] __builtin_ia32_rsqrtsf2 expander generat

[gcc r14-10940] i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357]

https://gcc.gnu.org/g:fee461613856c98946e15ef55d813831a73d2485 commit r14-10940-gfee461613856c98946e15ef55d813831a73d2485 Author: Uros Bizjak Date: Mon Nov 18 22:38:46 2024 +0100 i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357] __builtin_ia32_rsqrtsf2 expander generat

[gcc r15-5426] i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357]

https://gcc.gnu.org/g:344356f781ddb7bf0abb11edf9bdd13f6802dea8 commit r15-5426-g344356f781ddb7bf0abb11edf9bdd13f6802dea8 Author: Uros Bizjak Date: Mon Nov 18 22:38:46 2024 +0100 i386: Enable *rsqrtsf2_sse without TARGET_SSE_MATH [PR117357] __builtin_ia32_rsqrtsf2 expander generate

[gcc r15-4767] i386: Use assign_stack_temp instead of assign_386_stack_local with SLOT_TEMP

https://gcc.gnu.org/g:ee09fcc4e37a80d1c5cc0b08144bb1c2c4424747 commit r15-4767-gee09fcc4e37a80d1c5cc0b08144bb1c2c4424747 Author: Uros Bizjak Date: Wed Oct 30 08:17:15 2024 +0100 i386: Use assign_stack_temp instead of assign_386_stack_local with SLOT_TEMP It is better to use assign

[gcc r15-4479] i386: Fix the order of operands in andn3 [PR117192]

https://gcc.gnu.org/g:3a12ac403251e0a1542609d7a4d8a464a5e1dc86 commit r15-4479-g3a12ac403251e0a1542609d7a4d8a464a5e1dc86 Author: Uros Bizjak Date: Fri Oct 18 16:04:12 2024 +0200 i386: Fix the order of operands in andn3 [PR117192] Fix the order of operands in andn3 expander to comp

[gcc r12-10774] i386: Fix expand_vector_set for VEC_MERGE/VEC_DUPLICATE RTX [PR117116]

https://gcc.gnu.org/g:a8bd38de88715fdbf0d064ff0d50e2b8734de939 commit r12-10774-ga8bd38de88715fdbf0d064ff0d50e2b8734de939 Author: Uros Bizjak Date: Tue Oct 15 16:51:33 2024 +0200 i386: Fix expand_vector_set for VEC_MERGE/VEC_DUPLICATE RTX [PR117116] Middle end can generate SYMBOL_

[gcc r13-9119] i386: Fix expand_vector_set for VEC_MERGE/VEC_DUPLICATE RTX [PR117116]

https://gcc.gnu.org/g:dc295054c4ba28e44d4856bb68d148e9ac272d05 commit r13-9119-gdc295054c4ba28e44d4856bb68d148e9ac272d05 Author: Uros Bizjak Date: Tue Oct 15 16:51:33 2024 +0200 i386: Fix expand_vector_set for VEC_MERGE/VEC_DUPLICATE RTX [PR117116] Middle end can generate SYMBOL_R

[gcc r14-10797] i386: Fix expand_vector_set for VEC_MERGE/VEC_DUPLICATE RTX [PR117116]

https://gcc.gnu.org/g:8be94d5643176ecd2dcdceaf4448c3b89318037c commit r14-10797-g8be94d5643176ecd2dcdceaf4448c3b89318037c Author: Uros Bizjak Date: Tue Oct 15 16:51:33 2024 +0200 i386: Fix expand_vector_set for VEC_MERGE/VEC_DUPLICATE RTX [PR117116] Middle end can generate SYMBOL_

[gcc r15-4364] testsuite/i386: Require AVX2 effective target in pr107432-9.c

https://gcc.gnu.org/g:0fa5017df91731fb276aef5ded8a153e80bae358 commit r15-4364-g0fa5017df91731fb276aef5ded8a153e80bae358 Author: Uros Bizjak Date: Tue Oct 15 17:45:13 2024 +0200 testsuite/i386: Require AVX2 effective target in pr107432-9.c x86-64-v3 requires AVX2 effective target

[gcc r15-4359] i386: Fix expand_vector_set for VEC_MERGE/VEC_DUPLICATE RTX [PR117116]

https://gcc.gnu.org/g:80d7032067a3a5b76aecd657d9b35b0a8f5a941d commit r15-4359-g80d7032067a3a5b76aecd657d9b35b0a8f5a941d Author: Uros Bizjak Date: Tue Oct 15 16:51:33 2024 +0200 i386: Fix expand_vector_set for VEC_MERGE/VEC_DUPLICATE RTX [PR117116] Middle end can generate SYMBOL_R

[gcc r15-4284] testsuite/i386: Add vector sat_sub testcases [PR112600]

https://gcc.gnu.org/g:a564261245ad3002d53916e017b85939ace816a6 commit r15-4284-ga564261245ad3002d53916e017b85939ace816a6 Author: Uros Bizjak Date: Sat Oct 12 10:04:03 2024 +0200 testsuite/i386: Add vector sat_sub testcases [PR112600] PR middle-end/112600 gcc/tests

[gcc r14-10723] i386: Modernize AMD processor types

https://gcc.gnu.org/g:4697543b765dbfaa9dc12be0537861e586e48202 commit r14-10723-g4697543b765dbfaa9dc12be0537861e586e48202 Author: Uros Bizjak Date: Fri Sep 27 15:58:17 2024 +0200 i386: Modernize AMD processor types Use iterative PTA definitions for members of the same AMD processo

[gcc r15-3927] i386: Modernize AMD processor types

https://gcc.gnu.org/g:a72108920805a024b6bbee5acdd32914382c47a1 commit r15-3927-ga72108920805a024b6bbee5acdd32914382c47a1 Author: Uros Bizjak Date: Fri Sep 27 15:58:17 2024 +0200 i386: Modernize AMD processor types Use iterative PTA definitions for members of the same AMD processor

[gcc r15-3612] i386: Implement SAT_ADD for signed vector integers

https://gcc.gnu.org/g:19d751601d012bbe31512d26f968e75873a408ab commit r15-3612-g19d751601d012bbe31512d26f968e75873a408ab Author: Uros Bizjak Date: Thu Sep 12 20:34:28 2024 +0200 i386: Implement SAT_ADD for signed vector integers Enable V4QI, V2QI and V2HI mode signed saturated ari

[gcc r15-3604] i386: Use offsetable address constraint for double-word memory operands, part 2

https://gcc.gnu.org/g:8c01976b8e34eaa2483ab37d1bd18ebc5c8ada95 commit r15-3604-g8c01976b8e34eaa2483ab37d1bd18ebc5c8ada95 Author: Uros Bizjak Date: Thu Sep 12 16:28:10 2024 +0200 i386: Use offsetable address constraint for double-word memory operands, part 2 Double-word memory ope

[gcc r15-3552] i386: Use offsetable address constraint for double-word memory operands

https://gcc.gnu.org/g:1da79de5275de82bc810d2f8d70fbc98dbce3da5 commit r15-3552-g1da79de5275de82bc810d2f8d70fbc98dbce3da5 Author: Uros Bizjak Date: Mon Sep 9 22:33:52 2024 +0200 i386: Use offsetable address constraint for double-word memory operands Double-word memory operands are

[gcc r15-2419] i386/testsuite: Add testcase for fixed PR [PR51492]

https://gcc.gnu.org/g:8b737ec289da83e9e2a9672be0336980616e8932 commit r15-2419-g8b737ec289da83e9e2a9672be0336980616e8932 Author: Uros Bizjak Date: Tue Jul 30 20:02:36 2024 +0200 i386/testsuite: Add testcase for fixed PR [PR51492] PR target/51492 gcc/testsuite/Chan

[gcc r15-2147] libatomic: Handle AVX+CX16 ZHAOXIN like Intel for 16b atomic [PR104688]

https://gcc.gnu.org/g:9846b0916c1a9b9f3e9df4657670ef4419617134 commit r15-2147-g9846b0916c1a9b9f3e9df4657670ef4419617134 Author: mayshao Date: Thu Jul 18 22:43:00 2024 +0200 libatomic: Handle AVX+CX16 ZHAOXIN like Intel for 16b atomic [PR104688] PR target/104688 l

[gcc r15-2142] libatomic: Improve cpuid usage in __libat_feat1_init

https://gcc.gnu.org/g:f7d01e080a54ea94586c8847857e5aef17906519 commit r15-2142-gf7d01e080a54ea94586c8847857e5aef17906519 Author: Uros Bizjak Date: Thu Jul 18 16:58:09 2024 +0200 libatomic: Improve cpuid usage in __libat_feat1_init Check the result of __get_cpuid and process FEAT1_

[gcc r12-10623] alpha: Fix duplicate !tlsgd!62 assemble error [PR115526]

https://gcc.gnu.org/g:c5a26fc24b0af61498fae65ccad69d51d63d2a8b commit r12-10623-gc5a26fc24b0af61498fae65ccad69d51d63d2a8b Author: Uros Bizjak Date: Wed Jul 17 18:11:26 2024 +0200 alpha: Fix duplicate !tlsgd!62 assemble error [PR115526] Add missing "cannot_copy" attribute to instru

[gcc r13-8920] alpha: Fix duplicate !tlsgd!62 assemble error [PR115526]

https://gcc.gnu.org/g:37bd7d5c4e17c97d2b7d50f630b1cf8b347a31f4 commit r13-8920-g37bd7d5c4e17c97d2b7d50f630b1cf8b347a31f4 Author: Uros Bizjak Date: Wed Jul 17 18:11:26 2024 +0200 alpha: Fix duplicate !tlsgd!62 assemble error [PR115526] Add missing "cannot_copy" attribute to instruc

[gcc r14-10448] alpha: Fix duplicate !tlsgd!62 assemble error [PR115526]

https://gcc.gnu.org/g:3a963d441a68797956a5f67dcb351b2dbd4ac1d0 commit r14-10448-g3a963d441a68797956a5f67dcb351b2dbd4ac1d0 Author: Uros Bizjak Date: Wed Jul 17 18:11:26 2024 +0200 alpha: Fix duplicate !tlsgd!62 assemble error [PR115526] Add missing "cannot_copy" attribute to instru

[gcc r15-2104] alpha: Fix duplicate !tlsgd!62 assemble error [PR115526]

https://gcc.gnu.org/g:0841fd4c42ab053be951b7418233f0478282d020 commit r15-2104-g0841fd4c42ab053be951b7418233f0478282d020 Author: Uros Bizjak Date: Wed Jul 17 18:11:26 2024 +0200 alpha: Fix duplicate !tlsgd!62 assemble error [PR115526] Add missing "cannot_copy" attribute to instruc

[gcc r15-1954] i386: Swap compare operands in ustrunc patterns

https://gcc.gnu.org/g:aae535f3a870659d1f002f82bd585de0bcec7905 commit r15-1954-gaae535f3a870659d1f002f82bd585de0bcec7905 Author: Uros Bizjak Date: Wed Jul 10 23:00:00 2024 +0200 i386: Swap compare operands in ustrunc patterns A last minute change led to a wrong operand order in th

[gcc r11-11568] middle-end: Fix stalled swapped condition code value [PR115836]

https://gcc.gnu.org/g:d67566cefe7325998cc2471a28e9d3a3016455a0 commit r11-11568-gd67566cefe7325998cc2471a28e9d3a3016455a0 Author: Uros Bizjak Date: Wed Jul 10 09:27:27 2024 +0200 middle-end: Fix stalled swapped condition code value [PR115836] emit_store_flag_1 calculates scode (sw

[gcc r12-10610] middle-end: Fix stalled swapped condition code value [PR115836]

https://gcc.gnu.org/g:10904e051f1b970cd8e030dff7dec8374c946b12 commit r12-10610-g10904e051f1b970cd8e030dff7dec8374c946b12 Author: Uros Bizjak Date: Wed Jul 10 09:27:27 2024 +0200 middle-end: Fix stalled swapped condition code value [PR115836] emit_store_flag_1 calculates scode (sw

[gcc r13-8903] middle-end: Fix stalled swapped condition code value [PR115836]

https://gcc.gnu.org/g:cc47ad09e571016f498710fbd8a19f302c9004de commit r13-8903-gcc47ad09e571016f498710fbd8a19f302c9004de Author: Uros Bizjak Date: Wed Jul 10 09:27:27 2024 +0200 middle-end: Fix stalled swapped condition code value [PR115836] emit_store_flag_1 calculates scode (swa

[gcc r14-10404] middle-end: Fix stalled swapped condition code value [PR115836]

https://gcc.gnu.org/g:47a8b464d2dd9a586a9e15242c9825e39e1ecd4c commit r14-10404-g47a8b464d2dd9a586a9e15242c9825e39e1ecd4c Author: Uros Bizjak Date: Wed Jul 10 09:27:27 2024 +0200 middle-end: Fix stalled swapped condition code value [PR115836] emit_store_flag_1 calculates scode (sw

[gcc r15-1939] middle-end: Fix stalled swapped condition code value [PR115836]

https://gcc.gnu.org/g:44933fdeb338e00c972e42224b9a83d3f8f6a757 commit r15-1939-g44933fdeb338e00c972e42224b9a83d3f8f6a757 Author: Uros Bizjak Date: Wed Jul 10 09:27:27 2024 +0200 middle-end: Fix stalled swapped condition code value [PR115836] emit_store_flag_1 calculates scode (swa

[gcc r15-1914] i386: Implement .SAT_TRUNC for unsigned integers

https://gcc.gnu.org/g:d17889dbffd5dcdb2df22d42586ac0363704e1f1 commit r15-1914-gd17889dbffd5dcdb2df22d42586ac0363704e1f1 Author: Uros Bizjak Date: Tue Jul 9 17:34:25 2024 +0200 i386: Implement .SAT_TRUNC for unsigned integers The following testcase: unsigned short foo (un

[gcc r15-1899] i386: Promote {QI, HI}mode x86_movcc_0_m1_neg to SImode

https://gcc.gnu.org/g:2b3027bea3f218599d36379d3d593841df7a1559 commit r15-1899-g2b3027bea3f218599d36379d3d593841df7a1559 Author: Uros Bizjak Date: Mon Jul 8 20:47:52 2024 +0200 i386: Promote {QI,HI}mode x86_movcc_0_m1_neg to SImode Promote HImode x86_movcc_0_m1_neg insn to SImode

[gcc r15-1711] i386: Cleanup tmp variable usage in ix86_expand_move

https://gcc.gnu.org/g:7419b4fe48b48e44b27e2dadc9ff870f5e049077 commit r15-1711-g7419b4fe48b48e44b27e2dadc9ff870f5e049077 Author: Uros Bizjak Date: Fri Jun 28 17:49:43 2024 +0200 i386: Cleanup tmp variable usage in ix86_expand_move Remove extra assignment, extra temp variable and v

[gcc r15-1454] i386: Zhaoxin shijidadao enablement

https://gcc.gnu.org/g:6f6ea27d17e9bbc917b94ffea1c933755e736bdc commit r15-1454-g6f6ea27d17e9bbc917b94ffea1c933755e736bdc Author: mayshao Date: Wed Jun 19 16:03:25 2024 +0200 i386: Zhaoxin shijidadao enablement This patch enables -march/-mtune=shijidadao, costs and tunings are set

[gcc r15-1183] i386: Use CMOV in .SAT_{ADD|SUB} expansion for TARGET_CMOV [PR112600]

https://gcc.gnu.org/g:05b95238be648c9cf8af2516930af6a7b637a2b8 commit r15-1183-g05b95238be648c9cf8af2516930af6a7b637a2b8 Author: Uros Bizjak Date: Tue Jun 11 16:00:31 2024 +0200 i386: Use CMOV in .SAT_{ADD|SUB} expansion for TARGET_CMOV [PR112600] For TARGET_CMOV targets emit insn

[gcc r15-1122] i386: Implement .SAT_SUB for unsigned scalar integers [PR112600]

https://gcc.gnu.org/g:8bb6b2f4ae19c3aab7d7a5e5c8f5965f89d90e01 commit r15-1122-g8bb6b2f4ae19c3aab7d7a5e5c8f5965f89d90e01 Author: Uros Bizjak Date: Sun Jun 9 12:09:13 2024 +0200 i386: Implement .SAT_SUB for unsigned scalar integers [PR112600] The following testcase: unsign

[gcc r15-1113] i386: Implement .SAT_ADD for unsigned scalar integers [PR112600]

https://gcc.gnu.org/g:de05e44b2ad9638d04173393b1eae3c38b2c3864 commit r15-1113-gde05e44b2ad9638d04173393b1eae3c38b2c3864 Author: Uros Bizjak Date: Sat Jun 8 12:17:11 2024 +0200 i386: Implement .SAT_ADD for unsigned scalar integers [PR112600] The following testcase: unsign

[gcc r15-1077] testsuite/i386: Add vector sat_sub testcases [PR112600]

https://gcc.gnu.org/g:366d45c8d4911dc7874d2e64cf2583c0133b8dd5 commit r15-1077-g366d45c8d4911dc7874d2e64cf2583c0133b8dd5 Author: Uros Bizjak Date: Thu Jun 6 19:18:41 2024 +0200 testsuite/i386: Add vector sat_sub testcases [PR112600] PR middle-end/112600 gcc/testsu

[gcc r11-11463] alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

https://gcc.gnu.org/g:835b913aff1b1a813df3b9d2bbef170ae7d8856d commit r11-11463-g835b913aff1b1a813df3b9d2bbef170ae7d8856d Author: Uros Bizjak Date: Fri May 31 15:52:03 2024 +0200 alpha: Fix invalid RTX in divmodsi insn patterns [PR115297] any_divmod instructions are modelled with

[gcc r12-10486] alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

https://gcc.gnu.org/g:c6c2a6cebabc5f78cef3d81cedb4b3b578478b9f commit r12-10486-gc6c2a6cebabc5f78cef3d81cedb4b3b578478b9f Author: Uros Bizjak Date: Fri May 31 15:52:03 2024 +0200 alpha: Fix invalid RTX in divmodsi insn patterns [PR115297] any_divmod instructions are modelled with

[gcc r13-8820] alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

https://gcc.gnu.org/g:ed06ca80bae174f1179222ff8e6b93464006e86a commit r13-8820-ged06ca80bae174f1179222ff8e6b93464006e86a Author: Uros Bizjak Date: Fri May 31 15:52:03 2024 +0200 alpha: Fix invalid RTX in divmodsi insn patterns [PR115297] any_divmod instructions are modelled with i

[gcc r15-993] i386: Force operand 1 of bswapsi2 to a register for !TARGET_BSWAP [PR115321]

https://gcc.gnu.org/g:6ab5145825ca7e96fcbe3aa505d42e4ae8f81009 commit r15-993-g6ab5145825ca7e96fcbe3aa505d42e4ae8f81009 Author: Uros Bizjak Date: Mon Jun 3 15:48:18 2024 +0200 i386: Force operand 1 of bswapsi2 to a register for !TARGET_BSWAP [PR115321] PR target/115321

[gcc r14-10264] alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

https://gcc.gnu.org/g:ec92744de552303a1424085203e1311bd9146f21 commit r14-10264-gec92744de552303a1424085203e1311bd9146f21 Author: Uros Bizjak Date: Fri May 31 15:52:03 2024 +0200 alpha: Fix invalid RTX in divmodsi insn patterns [PR115297] any_divmod instructions are modelled with

[gcc r15-943] alpha: Fix invalid RTX in divmodsi insn patterns [PR115297]

https://gcc.gnu.org/g:0ac802064c2a018cf166c37841697e867de65a95 commit r15-943-g0ac802064c2a018cf166c37841697e867de65a95 Author: Uros Bizjak Date: Fri May 31 15:52:03 2024 +0200 alpha: Fix invalid RTX in divmodsi insn patterns [PR115297] any_divmod instructions are modelled with in

[gcc r15-930] i386: Rewrite bswaphi2 handling [PR115102]

https://gcc.gnu.org/g:e715204f203d318524ae86f3f2a1e8d5d7cb08dc commit r15-930-ge715204f203d318524ae86f3f2a1e8d5d7cb08dc Author: Uros Bizjak Date: Thu May 30 21:27:42 2024 +0200 i386: Rewrite bswaphi2 handling [PR115102] Introduce *bswaphi2 instruction pattern and enable bswaphi2 e

[gcc r15-876] i386: Improve access to _Atomic DImode location via XMM regs for SSE4.1 x86_32 targets

https://gcc.gnu.org/g:91d79053f2b416cb9e97d9c0c3fb5b73075289e6 commit r15-876-g91d79053f2b416cb9e97d9c0c3fb5b73075289e6 Author: Uros Bizjak Date: Tue May 28 20:25:14 2024 +0200 i386: Improve access to _Atomic DImode location via XMM regs for SSE4.1 x86_32 targets Use MOVD/PEXTRD

[gcc r11-11454] ubsan: Use right address space for MEM_REF created for bool/enum sanitization [PR115172]

https://gcc.gnu.org/g:d8985ea10c911c994e00dbd6a08dcae907ebc1f7 commit r11-11454-gd8985ea10c911c994e00dbd6a08dcae907ebc1f7 Author: Jakub Jelinek Date: Wed May 22 09:12:28 2024 +0200 ubsan: Use right address space for MEM_REF created for bool/enum sanitization [PR115172] The follow

[gcc r12-10477] ubsan: Use right address space for MEM_REF created for bool/enum sanitization [PR115172]

https://gcc.gnu.org/g:da9b7a507ef38287cc16bc88e808293019f9f531 commit r12-10477-gda9b7a507ef38287cc16bc88e808293019f9f531 Author: Jakub Jelinek Date: Wed May 22 09:12:28 2024 +0200 ubsan: Use right address space for MEM_REF created for bool/enum sanitization [PR115172] The follow

[gcc r15-634] i386: Rename sat_plusminus expanders to standard names [PR112600]

https://gcc.gnu.org/g:b59de4113262f2bee14147eb17eb3592f03d9556 commit r15-634-gb59de4113262f2bee14147eb17eb3592f03d9556 Author: Uros Bizjak Date: Fri May 17 09:55:49 2024 +0200 i386: Rename sat_plusminus expanders to standard names [PR112600] Rename _3 expander to a standard ssadd

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