https://gcc.gnu.org/g:3a12ac403251e0a1542609d7a4d8a464a5e1dc86
commit r15-4479-g3a12ac403251e0a1542609d7a4d8a464a5e1dc86 Author: Uros Bizjak <ubiz...@gmail.com> Date: Fri Oct 18 16:04:12 2024 +0200 i386: Fix the order of operands in andn<MMXMODEI:mode>3 [PR117192] Fix the order of operands in andn<MMXMODEI:mode>3 expander to comply with the specification, where bitwise-complement applies to operand 2. PR target/117192 gcc/ChangeLog: * config/i386/mmx.md (andn<MMXMODEI:mode>3): Swap operand indexes 1 and 2 to comply with andn specification. gcc/testsuite/ChangeLog: * gcc.target/i386/pr117192.c: New test. Diff: --- gcc/config/i386/mmx.md | 6 +++--- gcc/testsuite/gcc.target/i386/pr117192.c | 16 ++++++++++++++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index ef4ed8b501a1..506f4cab6a81 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -4470,9 +4470,9 @@ (define_expand "andn<mode>3" [(set (match_operand:MMXMODEI 0 "register_operand") (and:MMXMODEI - (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand")) - (match_operand:MMXMODEI 2 "register_operand")))] - "TARGET_SSE2") + (not:MMXMODEI (match_operand:MMXMODEI 2 "register_operand")) + (match_operand:MMXMODEI 1 "register_operand")))] + "TARGET_MMX_WITH_SSE") (define_insn "mmx_andnot<mode>3" [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v") diff --git a/gcc/testsuite/gcc.target/i386/pr117192.c b/gcc/testsuite/gcc.target/i386/pr117192.c new file mode 100644 index 000000000000..8480c72dc0e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr117192.c @@ -0,0 +1,16 @@ +/* PR target/117192 */ +/* { dg-do run } */ +/* { dg-options "-O3 -fno-unswitch-loops" } */ + +int a, b, c, d; +int main() { + int e[6]; + for (d = 0; d < 6; d++) + if (!c) + e[d] = 0; + for (; b < 6; b++) + a = e[b]; + if (a != 0) + __builtin_abort(); + return 0; +}