[gcc r15-6722] RISC-V: Refine registered_functions list for rvv overloaded intrinsics.

https://gcc.gnu.org/g:00b77db92e3e549750050323a50e2cc7977d69cc commit r15-6722-g00b77db92e3e549750050323a50e2cc7977d69cc Author: xuli Date: Wed Jan 8 04:11:30 2025 + RISC-V: Refine registered_functions list for rvv overloaded intrinsics. Before this patch, each rvv overloaded

[gcc r15-6494] RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4

https://gcc.gnu.org/g:55f31c715f75c61b79b37e47e9d0429d062b29db commit r15-6494-g55f31c715f75c61b79b37e47e9d0429d062b29db Author: xuli Date: Fri Dec 13 04:28:48 2024 + RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4 Form2: void __attribute__((noinline))

[gcc r15-5187] RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483]

https://gcc.gnu.org/g:445d8bb6a89eb2275c4930ec87a98d5123e5abdd commit r15-5187-g445d8bb6a89eb2275c4930ec87a98d5123e5abdd Author: xuli Date: Tue Nov 12 02:31:28 2024 + RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483] This patch fixs https://gcc.

[gcc r15-5034] RISC-V: Add testcases for unsigned imm vec SAT_SUB form1

https://gcc.gnu.org/g:7c8f36b420d4dd70702855c69f5b749b04e09dfd commit r15-5034-g7c8f36b420d4dd70702855c69f5b749b04e09dfd Author: xuli Date: Wed Nov 6 06:10:09 2024 + RISC-V: Add testcases for unsigned imm vec SAT_SUB form1 form1: void __attribute__((noinline))

[gcc r15-4995] RISC-V: Add testcases for signed imm SAT_ADD form1

https://gcc.gnu.org/g:1e2ae65a7f01fa3dcdbfd1bb5bc87b860172336d commit r15-4995-g1e2ae65a7f01fa3dcdbfd1bb5bc87b860172336d Author: xuli Date: Mon Nov 4 10:00:45 2024 + RISC-V: Add testcases for signed imm SAT_ADD form1 This patch adds testcase for form1, as shown below:

[gcc r15-4994] Match:Support signed imm SAT_ADD form1

https://gcc.gnu.org/g:da31786910f253bba062d8f7126b269c432083ff commit r15-4994-gda31786910f253bba062d8f7126b269c432083ff Author: xuli Date: Wed Nov 6 01:56:09 2024 + Match:Support signed imm SAT_ADD form1 This patch would like to support .SAT_ADD when one of the op is sing

[gcc r15-4763] Match: Simplify (x != 0 ? x + ~0 : 0) to (x - x != 0).

https://gcc.gnu.org/g:4af8db3eca12b2db3753ce4b098cbd0ae32b4796 commit r15-4763-g4af8db3eca12b2db3753ce4b098cbd0ae32b4796 Author: xuli Date: Tue Oct 22 09:48:03 2024 + Match: Simplify (x != 0 ? x + ~0 : 0) to (x - x != 0). When the imm operand op1=1 in the unsigned scalar sat_s

[gcc r15-4764] RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1.

https://gcc.gnu.org/g:179a682d047500604c6612afb425acf481e1a6b2 commit r15-4764-g179a682d047500604c6612afb425acf481e1a6b2 Author: xuli Date: Wed Oct 23 01:57:51 2024 + RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1. form2: T __attribute__((noinline))

[gcc r15-4712] RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286]

https://gcc.gnu.org/g:75caa17f5cb4e414919baff0435300b549a76eca commit r15-4712-g75caa17f5cb4e414919baff0435300b549a76eca Author: xuli Date: Mon Oct 28 04:41:09 2024 + RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286] This patch fixes following ICE:

[gcc r15-4537] RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = 1.

https://gcc.gnu.org/g:adf4ece4dc48deb1d1790efe104fa0cbcc22c0b6 commit r15-4537-gadf4ece4dc48deb1d1790efe104fa0cbcc22c0b6 Author: xuli Date: Mon Oct 21 04:10:14 2024 + RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = 1. form 1: T __attribute__((noinline))

[gcc r15-4536] Match: Support IMM=1 for unsigned scalar .SAT_SUB IMM form 1

https://gcc.gnu.org/g:4e65e12a9a34d76f9a43fbc7ae32875a909ac708 commit r15-4536-g4e65e12a9a34d76f9a43fbc7ae32875a909ac708 Author: xuli Date: Mon Oct 21 04:08:46 2024 + Match: Support IMM=1 for unsigned scalar .SAT_SUB IMM form 1 This patch would like to support .SAT_SUB when on

[gcc r15-4535] RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = max -1.

https://gcc.gnu.org/g:93b6f287814bca3d10bcf53bb64db40d77eff5d7 commit r15-4535-g93b6f287814bca3d10bcf53bb64db40d77eff5d7 Author: xuli Date: Mon Oct 21 04:01:01 2024 + RISC-V: Add testcases for unsigned .SAT_SUB form 1 with IMM = max -1. form 1: T __attribute__((noinline))

[gcc r15-4534] Match: Support IMM=max-1 for unsigned scalar .SAT_SUB IMM form 1

https://gcc.gnu.org/g:1dccec47ab679926521fd4c9963b63b319b56eb9 commit r15-4534-g1dccec47ab679926521fd4c9963b63b319b56eb9 Author: xuli Date: Tue Oct 22 01:08:56 2024 + Match: Support IMM=max-1 for unsigned scalar .SAT_SUB IMM form 1 This patch would like to support .SAT_SUB whe

[gcc r14-10802] RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883]

https://gcc.gnu.org/g:ab465ce3a948cf57a315ea5b0c71780def0c8425 commit r14-10802-gab465ce3a948cf57a315ea5b0c71780def0c8425 Author: Li Xu Date: Thu Oct 10 08:51:19 2024 -0600 RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883] From: xuli Example

[gcc r15-2776] Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202]

https://gcc.gnu.org/g:06d3f31384a89039c510531cf8012caed05b2ffd commit r15-2776-g06d3f31384a89039c510531cf8012caed05b2ffd Author: Pan Li Date: Tue Aug 6 20:59:37 2024 +0800 Vect: Make sure the lhs type of .SAT_TRUNC has its mode precision [PR116202] The .SAT_TRUNC vect pattern reco

[gcc r15-2775] RISC-V: Update .SAT_TRUNC dump check due to middle-end change

https://gcc.gnu.org/g:1b5c57e53e7ee4087e10f51fcf74968d950d3d83 commit r15-2775-g1b5c57e53e7ee4087e10f51fcf74968d950d3d83 Author: Pan Li Date: Mon Aug 5 16:01:11 2024 +0800 RISC-V: Update .SAT_TRUNC dump check due to middle-end change Due to recent middle-end change, update the .SA

[gcc r15-1993] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]

https://gcc.gnu.org/g:63d7d5998e3768f6e3703c29e8774e8b54af108c commit r15-1993-g63d7d5998e3768f6e3703c29e8774e8b54af108c Author: xuli Date: Thu Jul 11 04:29:11 2024 + RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862] The reason is that in

[gcc r15-763] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c

https://gcc.gnu.org/g:ffab721f3c9ecbb9831844d844ad257b69a77993 commit r15-763-gffab721f3c9ecbb9831844d844ad257b69a77993 Author: xuli Date: Mon May 20 01:56:47 2024 + RISC-V: Enable vectorization for vect-early-break_124-pr114403.c Because "targetm.slow_unaligned_access" is set