[gcc r15-3186] i386: Add bf8 -> fp16 intrin

https://gcc.gnu.org/g:b4ac2c23d8745d98984954e88f02aa73f1c3594b commit r15-3186-gb4ac2c23d8745d98984954e88f02aa73f1c3594b Author: Haochen Jiang Date: Mon Aug 26 10:53:56 2024 +0800 i386: Add bf8 -> fp16 intrin Since BF8 and FP16 have same bits for exponent, the type conversion

[gcc r15-3185] AVX10.2: Support compare instructions

https://gcc.gnu.org/g:576bd309ded9dfe258023f26924c064a7bf12875 commit r15-3185-g576bd309ded9dfe258023f26924c064a7bf12875 Author: Zhang, Jun Date: Mon Aug 26 10:53:54 2024 +0800 AVX10.2: Support compare instructions gcc/ChangeLog: * config/i386/i386-expand.cc

[gcc r15-3184] AVX10.2: Support vector copy instructions

https://gcc.gnu.org/g:f6fe2962daf7b8d8532c768c3b9eab00f99cce5b commit r15-3184-gf6fe2962daf7b8d8532c768c3b9eab00f99cce5b Author: Zhang, Jun Date: Mon Aug 26 10:53:52 2024 +0800 AVX10.2: Support vector copy instructions gcc/ChangeLog: * config.gcc: Add avx10_2copyi

[gcc r15-3183] AVX10.2: Support minmax instructions

https://gcc.gnu.org/g:889f6dd0d8c7317f62578c900c0f662e919786a2 commit r15-3183-g889f6dd0d8c7317f62578c900c0f662e919786a2 Author: Mo, Zewei Date: Mon Aug 26 10:53:50 2024 +0800 AVX10.2: Support minmax instructions gcc/ChangeLog: * config.gcc: Add avx10_2-512minmaxi

[gcc r15-3182] [PATCH 2/2] AVX10.2: Support saturating convert instructions

https://gcc.gnu.org/g:3a97ce179f75ec32b7f591422ba254c814567e4d commit r15-3182-g3a97ce179f75ec32b7f591422ba254c814567e4d Author: Hu, Lin1 Date: Mon Aug 26 10:53:49 2024 +0800 [PATCH 2/2] AVX10.2: Support saturating convert instructions gcc/ChangeLog: * config/i386

[gcc r15-3181] [PATCH 1/2] AVX10.2: Support saturating convert instructions

https://gcc.gnu.org/g:e2c80d237223f8524c2bd930b681aa891a13db99 commit r15-3181-ge2c80d237223f8524c2bd930b681aa891a13db99 Author: Hu, Lin1 Date: Mon Aug 26 10:53:47 2024 +0800 [PATCH 1/2] AVX10.2: Support saturating convert instructions gcc/ChangeLog: * config.gcc:

[gcc r15-3180] [PATCH 2/2] AVX10.2: Support BF16 instructions

https://gcc.gnu.org/g:5cb67ddd8240610f39c211b2f73070dc70b0230b commit r15-3180-g5cb67ddd8240610f39c211b2f73070dc70b0230b Author: konglin1 Date: Mon Aug 26 10:53:45 2024 +0800 [PATCH 2/2] AVX10.2: Support BF16 instructions gcc/ChangeLog: * config/i386/avx10_2-512bf

[gcc r15-3179] [PATCH 1/2] AVX10.2: Support BF16 instructions

https://gcc.gnu.org/g:9023662464ac7a0bbac72d94078ea0845bf99c86 commit r15-3179-g9023662464ac7a0bbac72d94078ea0845bf99c86 Author: konglin1 Date: Mon Aug 26 10:53:43 2024 +0800 [PATCH 1/2] AVX10.2: Support BF16 instructions gcc/ChangeLog: * config.gcc: Add avx10_2-5

[gcc r15-3177] [PATCH 2/2] AVX10.2: Support media instructions

https://gcc.gnu.org/g:af0a06274fce2ca64456f5b13b4bc8ff864a45e4 commit r15-3177-gaf0a06274fce2ca64456f5b13b4bc8ff864a45e4 Author: Haochen Jiang Date: Mon Aug 26 10:53:39 2024 +0800 [PATCH 2/2] AVX10.2: Support media instructions gcc/ChangeLog: * config/i386/avx10_2

[gcc r15-3176] [PATCH 1/2] AVX10.2: Support media instructions

https://gcc.gnu.org/g:8db80b2735782d793a83a9ef7eb012d83be7660d commit r15-3176-g8db80b2735782d793a83a9ef7eb012d83be7660d Author: Hongyu Wang Date: Mon Aug 26 10:53:37 2024 +0800 [PATCH 1/2] AVX10.2: Support media instructions gcc/ChangeLog * config.gcc: Add avx10_

[gcc r15-3175] i386: Refactor m512-check.h

https://gcc.gnu.org/g:cba4566879192abdc54bdf76b010e22d67484129 commit r15-3175-gcba4566879192abdc54bdf76b010e22d67484129 Author: Haochen Jiang Date: Mon Aug 26 10:53:35 2024 +0800 i386: Refactor m512-check.h After AVX10 introduction, we still want to use AVX512 helper functions

[gcc r15-3174] RISC-V: Support IMM for operand 0 of ussub pattern

https://gcc.gnu.org/g:17be00916e51835dcc47e30ed32fc892ee0c581d commit r15-3174-g17be00916e51835dcc47e30ed32fc892ee0c581d Author: Pan Li Date: Sat Aug 3 07:02:57 2024 + RISC-V: Support IMM for operand 0 of ussub pattern This patch would like to allow IMM for the operand 0 of us

[gcc r15-3173] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4

https://gcc.gnu.org/g:8f2f7aabcef8d801af002a26885a97ccf9889099 commit r15-3173-g8f2f7aabcef8d801af002a26885a97ccf9889099 Author: Pan Li Date: Sun Aug 25 14:15:40 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4 This patch would like to add test cases for the

[gcc r15-3172] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4

https://gcc.gnu.org/g:5ab1e238aa23d1773429f8f28abfb6ed16f655f6 commit r15-3172-g5ab1e238aa23d1773429f8f28abfb6ed16f655f6 Author: Pan Li Date: Sun Aug 25 11:02:10 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4 This patch would like to add test cases for the

[gcc r15-3170] RISC-V: Fix double mode under RV32 not utilize vf

https://gcc.gnu.org/g:7f65c38ac1b18773d55c08d6ba920a798462b871 commit r15-3170-g7f65c38ac1b18773d55c08d6ba920a798462b871 Author: demin.han Date: Sun Aug 25 15:53:58 2024 -0600 RISC-V: Fix double mode under RV32 not utilize vf Currently, some binops of vector vs double scalar under

[gcc r15-3169] [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move.

https://gcc.gnu.org/g:dba20679f1bf138ab5e61ad131b887db42083174 commit r15-3169-gdba20679f1bf138ab5e61ad131b887db42083174 Author: Xianmiao Qu Date: Sun Aug 25 11:22:21 2024 -0600 [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move. The previous patch:

[gcc r15-3168] testsuite: Run array54.C only for sync_int_long targets

https://gcc.gnu.org/g:b21d64742e9cffafeb7c4c2b131bf622aaf38dbe commit r15-3168-gb21d64742e9cffafeb7c4c2b131bf622aaf38dbe Author: Dimitar Dimitrov Date: Tue Aug 6 21:47:24 2024 +0300 testsuite: Run array54.C only for sync_int_long targets The test case uses "atomic", which fails to

[gcc r15-3167] Support if conversion for switches

https://gcc.gnu.org/g:c9ccc3961f5b8d333f5081b377cd9ee9e33079f7 commit r15-3167-gc9ccc3961f5b8d333f5081b377cd9ee9e33079f7 Author: Andi Kleen Date: Thu Aug 1 20:10:27 2024 -0700 Support if conversion for switches The gimple-if-to-switch pass converts if statements with multiple

[gcc r15-3166] Write CodeView information about static locals in optimized code

https://gcc.gnu.org/g:382fcf03e0ff6b32ce321fea6a81b87c8aa8f0c2 commit r15-3166-g382fcf03e0ff6b32ce321fea6a81b87c8aa8f0c2 Author: Mark Harmstone Date: Sun Aug 11 02:57:59 2024 +0100 Write CodeView information about static locals in optimized code Write CodeView S_LDATA32 symbols fo

[gcc r15-3165] Write CodeView S_FRAMEPROC symbols

https://gcc.gnu.org/g:3d87080598cf056fcfa25c72fcff0e06f67ee9ab commit r15-3165-g3d87080598cf056fcfa25c72fcff0e06f67ee9ab Author: Mark Harmstone Date: Sun Aug 11 02:48:00 2024 +0100 Write CodeView S_FRAMEPROC symbols Write S_FRAMEPROC symbols, which aren't very useful but seem to b

[gcc r15-3164] Write CodeView information about optimized stack variables

https://gcc.gnu.org/g:be23c8befcf37cabb3cef500d22d1af592139959 commit r15-3164-gbe23c8befcf37cabb3cef500d22d1af592139959 Author: Mark Harmstone Date: Sun Aug 11 02:23:26 2024 +0100 Write CodeView information about optimized stack variables Outputs S_DEFRANGE_REGISTER_REL symbols f

[gcc r15-3163] Write CodeView information about enregistered optimized variables

https://gcc.gnu.org/g:ee020b4a6cb796c3363bed562fb43d7b36603108 commit r15-3163-gee020b4a6cb796c3363bed562fb43d7b36603108 Author: Mark Harmstone Date: Thu Aug 8 03:18:11 2024 +0100 Write CodeView information about enregistered optimized variables Enable variable tracking when outpu

[gcc r15-3162] i386: Update STV's gains for TImode arithmetic right shifts on AVX2.

https://gcc.gnu.org/g:07d62a1711f3e3bbdd2146ab5914d3bc5e246509 commit r15-3162-g07d62a1711f3e3bbdd2146ab5914d3bc5e246509 Author: Roger Sayle Date: Sun Aug 25 09:14:34 2024 -0600 i386: Update STV's gains for TImode arithmetic right shifts on AVX2. This patch tweaks timode_scalar_ch

[gcc r15-3161] Disable late-combine in another RISC-V test

https://gcc.gnu.org/g:70edccf88738ec204036e498a4a50c46e5e4f0c0 commit r15-3161-g70edccf88738ec204036e498a4a50c46e5e4f0c0 Author: Jeff Law Date: Sun Aug 25 07:24:56 2024 -0600 Disable late-combine in another RISC-V test Another test where the output was slightly twiddled by late-co

[gcc r15-3160] [committed] Fix assembly scan for RISC-V VLS tests

https://gcc.gnu.org/g:4c3485897d3e28ecfbe911f21f83fa047ee8b54b commit r15-3160-g4c3485897d3e28ecfbe911f21f83fa047ee8b54b Author: Jeff Law Date: Sun Aug 25 07:16:50 2024 -0600 [committed] Fix assembly scan for RISC-V VLS tests Surya's IRA patch from June slightly improves the code

[gcc r15-3159] Turn off late-combine for a few risc-v specific tests

https://gcc.gnu.org/g:ab9c4bb54e817948f1a55edfb0f1f0481e4046df commit r15-3159-gab9c4bb54e817948f1a55edfb0f1f0481e4046df Author: Jeff Law Date: Sun Aug 25 07:06:45 2024 -0600 Turn off late-combine for a few risc-v specific tests Just minor testsuite adjustments -- several of the s

[gcc r15-3158] modula2 testsuite: new libc unit test

https://gcc.gnu.org/g:91f549537caa8dff2621c22ef2cdd48c55b0ad19 commit r15-3158-g91f549537caa8dff2621c22ef2cdd48c55b0ad19 Author: Gaius Mulley Date: Sun Aug 25 10:14:49 2024 +0100 modula2 testsuite: new libc unit test This patch provides a simple unit test for snprintf and atof aga