https://gcc.gnu.org/g:ab9c4bb54e817948f1a55edfb0f1f0481e4046df
commit r15-3159-gab9c4bb54e817948f1a55edfb0f1f0481e4046df
Author: Jeff Law <j...@ventanamicro.com>
Date: Sun Aug 25 07:06:45 2024 -0600
Turn off late-combine for a few risc-v specific tests
Just minor testsuite adjustments -- several of the shorten-memref tests are
slightly twiddled by the late-combine pass:
> Running /home/jlaw/test/gcc/gcc/testsuite/gcc.target/riscv/riscv.exp ...
> FAIL: gcc.target/riscv/shorten-memrefs-2.c -Os scan-assembler
store1a:\n(\t?\\.[^\n]*\n)*\taddi
> XPASS: gcc.target/riscv/shorten-memrefs-3.c -Os scan-assembler-not
load2a:\n.*addi[ \t]*[at][0-9],[at][0-9],[0-9]*
> FAIL: gcc.target/riscv/shorten-memrefs-5.c -Os scan-assembler
store1a:\n(\t?\\.[^\n]*\n)*\taddi
> FAIL: gcc.target/riscv/shorten-memrefs-8.c -Os scan-assembler
store:\n(\t?\\.[^\n]*\n)*\taddi\ta[0-7],a[0-7],1
This patch just turns off the late-combine pass for those tests. Locally
I'd
adjusted all the shorten-memref patches, but a quick re-rest shows that
only 4
tests seem affected right now.
Anyway, pushing to the trunk to slightly clean up our test results.
gcc/testsuite
* gcc.target/riscv/shorten-memrefs-2.c: Turn off late-combine.
* gcc.target/riscv/shorten-memrefs-3.c: Likewise.
* gcc.target/riscv/shorten-memrefs-5.c: Likewise.
* gcc.target/riscv/shorten-memrefs-8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c | 2 +-
gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
index a9ddb797d06a..29ece481c261 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32 -fno-late-combine-instructions" }
*/
/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
/* shorten_memrefs should rewrite these load/stores into a compressible
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
index 3d561124b818..273a68c373a1 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32 -fno-late-combine-instructions" }
*/
/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
/* These loads cannot be compressed because only one compressed reg is
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
index 11e858ed6da0..f554105f91f1 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv64imc -mabi=lp64" } */
+/* { dg-options "-march=rv64imc -mabi=lp64 -fno-late-combine-instructions" } */
/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
/* shorten_memrefs should rewrite these load/stores into a compressible
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
index 3ff6956b33e4..d533355409ca 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c
@@ -1,4 +1,4 @@
-/* { dg-options "-march=rv32imc -mabi=ilp32" } */
+/* { dg-options "-march=rv32imc -mabi=ilp32 -fno-late-combine-instructions" }
*/
/* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
/* shorten_memrefs should use a correct base address*/
