[Bug target/60109] __builtin_frame_address does not work as documented on ARM

2014-02-07 Thread rearnsha at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60109 --- Comment #1 from Richard Earnshaw --- This is an unresolvable problem. If we made __builtin_frame_address(N > 0) always return 0, then some useful use cases for debugging would be excluded. On the other hand, it is impossible to know whether

[Bug pch/60010] AArch64: sigsegv in cc1plus using pch without defining TRY_EMPTY_VM_SPACE

2014-02-14 Thread rearnsha at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60010 --- Comment #4 from Richard Earnshaw --- Author: rearnsha Date: Fri Feb 14 14:14:03 2014 New Revision: 207785 URL: http://gcc.gnu.org/viewcvs?rev=207785&root=gcc&view=rev Log: PR pch/60010 2014-02-14 Kyle McMartin * config/host-linux.c (T

[Bug regression/60133] [4.8/4.9 Regression] wrong multiarch name on aarch64-linux-gnu

2014-02-17 Thread rearnsha at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60133 Richard Earnshaw changed: What|Removed |Added CC||aoliva at gcc dot gnu.org,

[Bug testsuite/59308] [4.9 Regression] gcc.dg/tree-ssa/ssa-ifcombine-ccmp-[1456] tests fail on arm cortex-a5

2014-03-02 Thread rearnsha at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59308 --- Comment #4 from Richard Earnshaw --- It's not as simple as updating the target selector. LONSC_P depends on BRANCH_COST, which can vary depending on the specific micro-architecture for the target system.

[Bug libgcc/60464] [arm] ARM -mthumb version of libgcc contains ARM (non-thumb) code; not safe for thumb-only architectures

2014-03-10 Thread rearnsha at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60464 --- Comment #8 from Richard Earnshaw --- (In reply to Jeremy Cooper from comment #7) > Is there a reason these were commented out? Is the armv7 multilib unstable? Volume of variants that have to be compiled at build time. Each enabled entry pra

[Bug regression/67415] [5/6 Regression] -mcpu= breaks -print-file-name for ARM crosscompilers

2015-09-02 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67415 --- Comment #5 from Richard Earnshaw --- Your GCC-4.9 is a Linaro build which contains some extensions of their own. It's possible that they've made some changes in the way search paths work. I'd start by asking them.

[Bug libgcc/67624] arm/fp16.c __gnu_f2h_internal has wrong pattern for INF/NAN

2015-09-18 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67624 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug libgcc/67624] arm/fp16.c __gnu_f2h_internal has wrong pattern for INF/NAN

2015-09-24 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67624 --- Comment #3 from Richard Earnshaw --- Author: rearnsha Date: Thu Sep 24 09:40:06 2015 New Revision: 228082 URL: https://gcc.gnu.org/viewcvs?rev=228082&root=gcc&view=rev Log: ARM: fp16 Fix PR 67624 - Incorrect conversion of float Infinity to _

[Bug libgcc/67624] arm/fp16.c __gnu_f2h_internal has wrong pattern for INF/NAN

2015-09-24 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67624 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug sanitizer/68099] arm-*-linux-gnueabihf -fsanitize=undefined warning: '' is used uninitialized in this function

2015-10-26 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68099 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |WAITING Last reconfirmed|

[Bug target/68178] [arm] Relative address expressions bind at as-time, even if symbol is weak

2015-11-02 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68178 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/68178] [arm] Relative address expressions bind at as-time, even if symbol is weak

2015-11-02 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68178 --- Comment #5 from Richard Earnshaw --- This particular case is a very specific situation. A definition of foo is guaranteed to exist (you've provided one); but it can be overridden. The definition (due to the use of hidden) has to exist in th

[Bug target/68178] [arm] Relative address expressions bind at as-time, even if symbol is weak

2015-11-02 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68178 --- Comment #6 from Richard Earnshaw --- Oh, and another point; since this is a function symbol, not a data symbol, it can't be subject to a copy relocation at run time, so even protected symbols should be acceptable here.

[Bug target/68178] [arm] Relative address expressions bind at as-time, even if symbol is weak

2015-11-03 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68178 Richard Earnshaw changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|INVALID

[Bug rtl-optimization/64537] Aarch64 redundant sxth instruction gets generated

2015-01-08 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64537 --- Comment #4 from Richard Earnshaw --- b is used twice, once shifted left by 3 and once directly. We could write this as subsx3, x0, x1, sxth 3 beq .L5 add w0, w2, w1, sxth <= Now extended

[Bug target/64542] ARM use of ARM instruction on Thumb-only target

2015-01-08 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64542 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/64542] ARM use of ARM instruction on Thumb-only target

2015-01-08 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64542 --- Comment #4 from Richard Earnshaw --- Note that armv6-m doesn't support ARM instructions at all, so the .arm directive is meaningless.

[Bug tree-optimization/64597] New: ICE when optimizing with AutoFDO annotation

2015-01-14 Thread rearnsha at gcc dot gnu.org
Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org CC: dehao at gcc dot gnu.org Target: x86_64-linux-gnu Created attachment 34446 --> https://gcc.gnu.org/bugzi

[Bug target/63808] [arm] Extra register saving in FIQ handler

2015-01-15 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63808 Richard Earnshaw changed: What|Removed |Added Priority|P3 |P4

[Bug fortran/64416] RFE: Support REAL128 on arm

2015-01-15 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64416 Richard Earnshaw changed: What|Removed |Added Keywords||EH Target|

[Bug libstdc++/63829] _Lock_policy used in thread.cc can cause incompatibilities with binaries using different -mcpu

2015-01-16 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63829 --- Comment #6 from Richard Earnshaw --- arm linux code should always be using the _S_atomic sequences. When the processor doesn't have the required instructions, kernel helper routines will be used. This ensures that code is forwards compatibl

[Bug c/64789] New: gcc generates unreliable code on arm with -mstructure-size-boundary=32

2015-01-28 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64789 Bug ID: 64789 Summary: gcc generates unreliable code on arm with -mstructure-size-boundary=32 Product: gcc Version: 4.8.3 Status: RESOLVED Severity: normal

[Bug target/64774] [ARM/thumb] missed optimization: pc relative ldr used when constant can be derived from register

2015-01-28 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64774 Richard Earnshaw changed: What|Removed |Added Target||arm Priority|P3

[Bug target/64783] -march=armv8.1-a should be supported

2015-01-29 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64783 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug gcov-profile/64874] New: gcov's magic number possibly increasing too quickly with new gcc version numbering scheme.

2015-01-30 Thread rearnsha at gcc dot gnu.org
IRMED Severity: normal Priority: P3 Component: gcov-profile Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org A comment in gcov-io.h reads: " Although the ident and version are formally 32 bit numbers, they are deri

[Bug target/64975] New: [AArch64] Thunderx should not default to crypto enabled

2015-02-08 Thread rearnsha at gcc dot gnu.org
Priority: P3 Component: target Assignee: pinskia at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org CC: pinskia at gcc dot gnu.org According to https://gcc.gnu.org/ml/gcc-patches/2014-11/msg02118.html the thunderX processors should not default to crypto

[Bug target/64953] Compiling sourcecode for STM32F103 causes USB errors with some optimization settings

2015-02-10 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64953 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |WAITING Last reconfirmed|

[Bug target/64953] Compiling sourcecode for STM32F103 causes USB errors with some optimization settings

2015-02-10 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64953 Richard Earnshaw changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug tree-optimization/65027] New: failure to emit diagnostic when optimizing using undefined behaviour

2015-02-11 Thread rearnsha at gcc dot gnu.org
Severity: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target: x86_64, arm The following code fragment, when compiled at -O3 is quite reasonably optimized

[Bug target/55701] Inline some instances of memset for ARM

2015-02-17 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55701 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |5.0

[Bug target/63521] The AArch64 backend doesn't define REG_ALLOC_ORDER.

2014-10-13 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63521 --- Comment #2 from Richard Earnshaw --- Ideally, a port should not need to define reg_alloc_order; it's rather a blunt instrument. Better would be for the register allocator to have a better understanding of which registers are being used for p

[Bug middle-end/63735] New: [5.0 regression] >5% code size regression since 2014/10/13

2014-11-04 Thread rearnsha at gcc dot gnu.org
mal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target: arm aarch64 Since 2014/10/13 there have been a number of commits that have contributed to a significant overall code-size regression at

[Bug middle-end/63735] [5.0 regression] >5% code size regression since 2014/10/13

2014-11-04 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63735 --- Comment #2 from Richard Earnshaw --- I'll try, but with build breakage as well, it may not prove very much.

[Bug middle-end/63735] [5.0 regression] >5% code size regression since 2014/10/13

2014-11-04 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63735 --- Comment #3 from Richard Earnshaw --- regression is caused by the switch to GNU11. Adding -std=gnu90 gives expected numbers. That's a pretty big penalty for using GNU11 coding!

[Bug middle-end/63735] [5.0 regression] >5% code size regression since 2014/10/13

2014-11-04 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63735 --- Comment #5 from Richard Earnshaw --- Yeah, all the changes are in the linux kernel module. It's only one component of the benchmark (though probably the largest). Adding -fgnu89-inline is also sufficient to fix the code size regression. In

[Bug middle-end/63735] [5.0 regression] >5% code size regression since 2014/10/13

2014-11-04 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63735 --- Comment #6 from Richard Earnshaw --- Confirmed that the compilation time regression is related entirely to the extra code generated.

[Bug target/63742] arm *movhi_insn_arch4 pattern may emit ldrh which is wrong for big-endian

2014-11-05 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63742 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/59593] [arm big-endian] using "ldrh" access a immediate which stored in a memory by word

2014-11-05 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59593 Richard Earnshaw changed: What|Removed |Added CC||fei.yang0953 at gmail dot com --- Com

[Bug bootstrap/63771] internal compiler error: in lra_create_copy, at lra.c:1532

2014-11-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63771 --- Comment #1 from Richard Earnshaw --- > --with-as=/home/slug/optware/cs08q1armel/toolchain/arm-2008q1/bin/arm-none-linux-gnueabi-as > > 9828c9828 > < return \".word\\t0xe7f000f0\"; > --- > > return \".inst\\t0xe7f000f0\"; > 9830c9830 >

[Bug target/63808] [arm] Invalid register saving in FIQ handler causes register corruption

2014-11-11 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63808 --- Comment #1 from Richard Earnshaw --- What CPU are you running this on?

[Bug target/63808] [arm] Invalid register saving in FIQ handler causes register corruption

2014-11-11 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63808 --- Comment #3 from Richard Earnshaw --- (In reply to Sergey Belyashov from comment #2) > Target is armv4: I use gcc options: -marm -march=armv4 Which doesn't really answer my question. Which *CPU* are you seeing this on? My reading of the Arc

[Bug target/63874] vtable address generation goes through memory

2014-11-18 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63874 --- Comment #1 from Richard Earnshaw --- Sounds like this might be confusion between weak definitions and weak references. If we have a weak reference to the object, we cannot convert it into a pc-relative expression, since that would mean we co

[Bug other/63929] GCC sets soft-float ABI even is specified -mfloat-abi=hard when compiling an assembler file.

2014-11-21 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63929 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/63749] [4.9/5 Regression] registers may not be the same

2014-11-21 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63749 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug middle-end/63762] [ARM]GCC generates UNPREDICTABLE STR with Rn = Rt when hard-float abi is used

2014-11-21 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63762 Richard Earnshaw changed: What|Removed |Added CC||doko at gcc dot gnu.org --- Comment #

[Bug target/63949] Aarch64 instruction combiner does not optimize subsi_sxth function as expected (gcc.target/aarch64/extend.c fails)

2014-11-22 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63949 --- Comment #3 from Richard Earnshaw --- make_extraction is unable to generate bit-field extractions in more than one mode. This causes the extractions that it does generate to be wrapped in subregs when SImode results are wanted. Ideally, we s

[Bug target/63663] [NEON] wrong value when computing the leading zero of int16x4_t type at O2

2014-11-26 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63663 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/63663] [NEON] wrong value when computing the leading zero of int16x4_t type at O2

2014-11-26 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63663 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |5.0

[Bug target/64224] [ARM] -mapcs -marm uses deprecated forms (as of ARMv7-A) of LDM in epilogues

2014-12-08 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64224 --- Comment #2 from Richard Earnshaw --- Might be better to just deprecate -mapcs; it's a feature of the old ABI anyway, so there's not much point in trying to make it fully conform to the latest specs.

[Bug target/64149] -mno-lra bitrots, suggest to remove for GCC 5

2014-12-15 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64149 --- Comment #2 from Richard Earnshaw --- Sounds sensible to me. We switched to LRA quite late in gcc-4.9, so keeping a way to switch back in case of problems was pragmatic. But we've been running with the new code now for a year and not encou

[Bug target/61714] New: configure --with-arch and --with-cpu are ignored on aarch64

2014-07-04 Thread rearnsha at gcc dot gnu.org
Priority: P3 Component: target Assignee: rearnsha at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target: aarch64 The --with-arch and --with-cpu options on aarch64 are accepted and validated during configure but have no effect on the compiler. This

[Bug target/61714] configure --with-arch and --with-cpu are ignored on aarch64

2014-07-04 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61714 --- Comment #1 from Richard Earnshaw --- Author: rearnsha Date: Fri Jul 4 10:51:56 2014 New Revision: 212295 URL: https://gcc.gnu.org/viewcvs?rev=212295&root=gcc&view=rev Log: PR target/61714 * aarch64.h (OPTION_DEFAULT_SPECS): Define.

[Bug rtl-optimization/61694] New: thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61694 Bug ID: 61694 Summary: thumb1_reorg crashes Product: gcc Version: 4.9.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization A

[Bug rtl-optimization/61695] New: thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61695 Bug ID: 61695 Summary: thumb1_reorg crashes Product: gcc Version: 4.9.0 Status: RESOLVED Severity: normal Priority: P3 Component: rtl-optimization Assi

[Bug rtl-optimization/61694] thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61694 --- Comment #2 from Richard Earnshaw --- *** Bug 61696 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/61696] New: thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61696 Bug ID: 61696 Summary: thumb1_reorg crashes Product: gcc Version: 4.9.0 Status: RESOLVED Severity: normal Priority: P3 Component: rtl-optimization Assi

[Bug rtl-optimization/61697] New: thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61697 Bug ID: 61697 Summary: thumb1_reorg crashes Product: gcc Version: 4.9.0 Status: RESOLVED Severity: normal Priority: P3 Component: rtl-optimization Assi

[Bug rtl-optimization/61694] thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61694 --- Comment #3 from Richard Earnshaw --- *** Bug 61697 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/61699] New: thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61699 Bug ID: 61699 Summary: thumb1_reorg crashes Product: gcc Version: 4.9.0 Status: RESOLVED Severity: normal Priority: P3 Component: rtl-optimization Assi

[Bug rtl-optimization/61694] thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61694 --- Comment #5 from Richard Earnshaw --- *** Bug 61699 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/61694] thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61694 --- Comment #6 from Richard Earnshaw --- *** Bug 61700 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/61700] New: thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61700 Bug ID: 61700 Summary: thumb1_reorg crashes Product: gcc Version: 4.9.0 Status: RESOLVED Severity: normal Priority: P3 Component: rtl-optimization Assi

[Bug rtl-optimization/61694] thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61694 --- Comment #7 from Richard Earnshaw --- *** Bug 61701 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/61701] New: thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61701 Bug ID: 61701 Summary: thumb1_reorg crashes Product: gcc Version: 4.9.0 Status: RESOLVED Severity: normal Priority: P3 Component: rtl-optimization Assi

[Bug rtl-optimization/61694] thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61694 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug rtl-optimization/61712] thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61712 --- Comment #17 from Richard Earnshaw --- *** Bug 61694 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/61694] thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61694 --- Comment #4 from Richard Earnshaw --- *** Bug 61698 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/61698] New: thumb1_reorg crashes

2014-07-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61698 Bug ID: 61698 Summary: thumb1_reorg crashes Product: gcc Version: 4.9.0 Status: RESOLVED Severity: normal Priority: P3 Component: rtl-optimization Assi

[Bug target/61561] arm gcc internal error

2014-07-11 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61561 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |4.10.0

[Bug sanitizer/61771] Regressions in ASan testsuite on ARM Linux

2014-07-15 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61771 --- Comment #1 from Richard Earnshaw --- The ABI does not document a model for stack chains, so any use of a frame pointer is, by definition, purely private to that function.

[Bug rtl-optimization/61712] thumb1_reorg crashes

2014-07-29 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61712 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/61544] ICE due to thumb1_reorg function mishandles label type insn

2014-07-29 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61544 Richard Earnshaw changed: What|Removed |Added CC||manjian2006 at gmail dot com --- Comm

[Bug target/62014] [AArch64] Using -mgeneral-regs-only may lead to ICE

2014-08-05 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62014 --- Comment #12 from Richard Earnshaw --- aarch64_conditional_register_usage() marks all FP registers as unavailable if !TARGET_FLOAT. So the real question is why this isn't sufficient to disable use of FP registers.

[Bug web/62211] ./configure --with-float= and ARM

2014-09-09 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62211 --- Comment #1 from Richard Earnshaw --- -m{soft,hard}-float for arm should be considered deprecated (we try to support them by mapping them onto the -mfloat-abi option), and deliberately no-longer document them. Rather than clarifying what th

[Bug target/63234] arm used label is removed

2014-09-15 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63234 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |WAITING Last reconfirmed|

[Bug target/63234] arm used label is removed

2014-09-18 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63234 Richard Earnshaw changed: What|Removed |Added Status|WAITING |UNCONFIRMED Ever confirmed|1

[Bug target/63304] Aarch64 pc-relative load offset out of range

2014-09-19 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63304 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/63304] Aarch64 pc-relative load offset out of range

2014-09-19 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63304 Richard Earnshaw changed: What|Removed |Added Priority|P3 |P5 Status|RESOLVED

[Bug target/63359] aarch64: 32bit registers in inline asm

2014-09-24 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/63359] aarch64: 32bit registers in inline asm

2014-09-24 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359 --- Comment #5 from Richard Earnshaw --- So consider: int f(int i){ long x; asm("lsl %0, %1, 33" : "=r"(x) : "r"(i)); // lshift by more than sizeof(int) return x; } We really don't care about the top bits in i, so we don't want to extend

[Bug target/63359] aarch64: 32bit registers in inline asm

2014-09-24 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63359 --- Comment #8 from Richard Earnshaw --- (In reply to James Molloy from comment #6) > Good example, although I might argue slightly pathological. > Agreed, this is somewhat pathological, but I only need to find one valid counter-example :-) Fu

[Bug target/63408] [4.8 regression] GCC emits incorrect FMA instruction on Cortex-M4 target

2014-09-30 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63408 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug rtl-optimization/64818] User specified register don't work correctly in inline-asm operands.

2015-12-11 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64818 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |6.0

[Bug preprocessor/68854] isystem and ansi cause arm assembly preprocessing problem

2015-12-11 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68854 --- Comment #1 from Richard Earnshaw --- ANSI is a dialect of C. Why are you passing that flag to an assembler file?

[Bug target/68934] [ARM] using simd types should be rejected if not fpu=neon

2015-12-16 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68934 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/68674] ARM/AARCH64 attribute target neon internal compiler error: in copy_to_mode_reg, at explow.c:595

2015-12-17 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68674 Richard Earnshaw changed: What|Removed |Added Status|RESOLVED|NEW Resolution|INVALID

[Bug gcov-profile/69004] Building t-engine on ARM fails during -fprofile-use stage

2015-12-23 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69004 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |WAITING Last reconfirmed|

[Bug gcov-profile/69004] Building t-engine on ARM fails during -fprofile-use stage

2015-12-23 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69004 --- Comment #8 from Richard Earnshaw --- (In reply to PeteVine from comment #7) > I think I erroneously attached the preprocessed source from the profile-use > stage; you wanted from profile-generate, right? We need the one from the phase where

[Bug gcov-profile/69004] Building t-engine on ARM fails during -fprofile-use stage

2015-12-23 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69004 --- Comment #10 from Richard Earnshaw --- (In reply to PeteVine from comment #4) > The above error (using -mcpu=cortex-a5 -ffast-math) is a little different > from this one (after taking those two flags out, leaving just -O3 > -fomit-frame-pointe

[Bug gcov-profile/69004] Building t-engine on ARM fails during -fprofile-use stage

2015-12-23 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69004 Richard Earnshaw changed: What|Removed |Added Status|WAITING |NEW --- Comment #12 from Richard Earn

[Bug target/68793] Bad optimization by split-wide-type on NEON

2015-12-23 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68793 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |6.0

[Bug middle-end/67797] builtin functions should be able to know when their first argument is returned

2015-12-23 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67797 Richard Earnshaw changed: What|Removed |Added Priority|P3 |P4 Status|UNCONFIRMED

[Bug lto/69119] More fun with LTO on arm

2016-01-04 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69119 Richard Earnshaw changed: What|Removed |Added Status|WAITING |RESOLVED Resolution|---

[Bug lto/69119] More fun with LTO on arm

2016-01-04 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69119 --- Comment #6 from Richard Earnshaw --- (In reply to PeteVine from comment #5) > Wait, what about #1? Sorry, I hadn't spotted that there were two issues in the one report. Please create separate bug reports for each issue - it's much easier to

[Bug target/69135] [5/6][ARM] instruction cannot be conditional -- `vcvtpne.s32.f32 s0,s0'

2016-01-04 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69135 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/69124] arm miss compiled code since gcc 5

2016-01-04 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69124 --- Comment #4 from Richard Earnshaw --- Does -fno-strict-aliasing help?

[Bug lto/69082] Final link fails on ARM using lto

2016-01-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69082 --- Comment #7 from Richard Earnshaw --- Ah! And the maximum range of offset for these relocations in REL format is -32768,+32767.

[Bug lto/69082] Final link fails on ARM using lto

2016-01-07 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69082 Richard Earnshaw changed: What|Removed |Added Status|WAITING |NEW --- Comment #9 from Richard Earns

[Bug target/69082] Final link fails on ARM using lto

2016-01-08 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69082 Richard Earnshaw changed: What|Removed |Added CC||renlin at gcc dot gnu.org Co

[Bug inline-asm/69248] VFP register constraint 'w' is ignored when optimizations are enabled

2016-01-12 Thread rearnsha at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69248 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

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