[Bug target/99381] New: SVE: ICE with ACLE intrinsics when missing -march=armv8.2-a+sve

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99381 Bug ID: 99381 Summary: SVE: ICE with ACLE intrinsics when missing -march=armv8.2-a+sve Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug target/99381] SVE: ICE with ACLE intrinsics when missing -march=armv8.2-a+sve

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99381 --- Comment #2 from Alex Coplan --- Fixed on trunk. Needs backporting to GCC 10.

[Bug target/99381] SVE: ICE with ACLE intrinsics when missing -march=armv8.2-a+sve

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99381 Alex Coplan changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/99216] ICE in aarch64_sve::function_expander::expand() with LTO

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99216 Alex Coplan changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned at

[Bug target/99216] ICE in aarch64_sve::function_expander::expand() with LTO

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99216 --- Comment #4 from Alex Coplan --- Right, the problem appears to be to do with the way that overloaded functions are implemented for the ACLE. Specifically the m_direct_overloads flag in aarch64_sve::function_builder. If this flag is set, we reg

[Bug target/99216] ICE in aarch64_sve::function_expander::expand() with LTO

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99216 --- Comment #6 from Alex Coplan --- Ok, I'll have a go, thanks.

[Bug rtl-optimization/99469] New: ICE: qsort checking failed with selective scheduling on aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99469 Bug ID: 99469 Summary: ICE: qsort checking failed with selective scheduling on aarch64 Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/99469] ICE: qsort checking failed with selective scheduling on aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99469 --- Comment #1 from Alex Coplan --- FWIW this is easy to reproduce with either csmith or yarpgen, so should be straightforward to procure a new testcase if the above goes latent.

[Bug tree-optimization/97104] [11 Regression] aarch64, SVE: ICE in vect_get_loop_mask since r11-3070-g783dc66f9cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97104 --- Comment #5 from Alex Coplan --- I have a bisect in progress.

[Bug tree-optimization/97104] [11 Regression] aarch64, SVE: ICE in vect_get_loop_mask since r11-3070-g783dc66f9cc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97104 Alex Coplan changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug tree-optimization/99523] New: Declarations for variable names missing in GIMPLE dump

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99523 Bug ID: 99523 Summary: Declarations for variable names missing in GIMPLE dump Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compon

[Bug tree-optimization/99523] Declarations for variable names missing in GIMPLE dump

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99523 --- Comment #5 from Alex Coplan --- Thanks for the fix!

[Bug target/99381] SVE: ICE with ACLE intrinsics when missing -march=armv8.2-a+sve

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99381 Alex Coplan changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/99554] New: SVE: ICE (segfault) in recog.c:extract_asm_operands during expand

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99554 Bug ID: 99554 Summary: SVE: ICE (segfault) in recog.c:extract_asm_operands during expand Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/99554] [10/11 Regression] SVE: ICE (segfault) in recog.c:extract_asm_operands during expand

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99554 Alex Coplan changed: What|Removed |Added Summary|SVE: ICE (segfault) in |[10/11 Regression] SVE: ICE

[Bug rtl-optimization/99554] [10/11 Regression] SVE: ICE (segfault) in recog.c:extract_asm_operands during expand

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99554 Alex Coplan changed: What|Removed |Added Known to fail||10.2.1 Known to work|

[Bug target/99540] [10/11 Regression] ICE: Segmentation fault in aarch64_add_offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99540 Alex Coplan changed: What|Removed |Added CC||acoplan at gcc dot gnu.org --- Comment #2

[Bug target/99560] New: aarch64: ICE (segfault) in LRA with SVE intrinsics

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99560 Bug ID: 99560 Summary: aarch64: ICE (segfault) in LRA with SVE intrinsics Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug target/99560] aarch64: ICE (segfault) in LRA with SVE intrinsics

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99560 Alex Coplan changed: What|Removed |Added Target Milestone|--- |10.3 Keywords|

[Bug target/97252] [10/11 Regression] arm: ICE compiling pure-code/pr94538-2.c with MVE since r10-7293-g3eff57aa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97252 Alex Coplan changed: What|Removed |Added Last reconfirmed||2021-03-15 Known to fail|

[Bug target/99596] [11 Regression] arm: internal error in single_pred_edge

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99596 Alex Coplan changed: What|Removed |Added Target Milestone|--- |11.0 Target|

[Bug target/97252] [10/11 Regression] arm: ICE compiling pure-code/pr94538-2.c with MVE since r10-7293-g3eff57aa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97252 --- Comment #2 from Alex Coplan --- > Unless I'm missing something, I don't think "Uxi" is a valid constraint. > Perhaps the "Ux" constraint was intended instead? D'oh, this is of course the union of the Ux (MVE-specific) constraint and the "i"

[Bug target/97252] [10/11 Regression] arm: ICE compiling pure-code/pr94538-2.c with MVE since r10-7293-g3eff57aa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97252 --- Comment #3 from Alex Coplan --- FWIW, for the related testcase (which we also ICE on): typedef int __attribute((vector_size(16))) V; V v; void f() { v = (V){4095}; } clang pushes the constant out to the constant pool: $ clang -target arm i

[Bug target/97252] [10/11 Regression] arm: ICE compiling pure-code/pr94538-2.c with MVE since r10-7293-g3eff57aa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97252 Alex Coplan changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |acoplan at gcc dot gnu.org --- Com

[Bug target/99647] New: arm: GCC generates invalid MVE vmov instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99647 Bug ID: 99647 Summary: arm: GCC generates invalid MVE vmov instruction Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: ta

[Bug target/99647] arm: GCC generates invalid MVE vmov instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99647 --- Comment #1 from Alex Coplan --- Also fails for GCC 10. Not sure if this counts as a regression since MVE only went in with GCC 10.

[Bug rtl-optimization/99554] [10/11 Regression] SVE: ICE (segfault) in recog.c:extract_asm_operands during expand

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99554 Alex Coplan changed: What|Removed |Added Resolution|--- |DUPLICATE Status|NEW

[Bug target/99540] [10/11 Regression] ICE: Segmentation fault in aarch64_add_offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99540 --- Comment #3 from Alex Coplan --- *** Bug 99554 has been marked as a duplicate of this bug. ***

[Bug target/97252] [10 Regression] arm: ICE compiling pure-code/pr94538-2.c with MVE since r10-7293-g3eff57aa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97252 Alex Coplan changed: What|Removed |Added Summary|[10/11 Regression] arm: ICE |[10 Regression] arm: ICE

[Bug target/99723] New: arm: ICE in build_function_type during selftests

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99723 Bug ID: 99723 Summary: arm: ICE in build_function_type during selftests Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: t

[Bug target/99723] arm: ICE in build_function_type during selftests

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99723 Alex Coplan changed: What|Removed |Added Target|aarch64 |arm --- Comment #1 from Alex Coplan --- @

[Bug target/99725] New: arm: ICE in dwarf2out_frame_debug_adjust_cfa with -mcmse

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99725 Bug ID: 99725 Summary: arm: ICE in dwarf2out_frame_debug_adjust_cfa with -mcmse Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priori

[Bug target/99727] New: [11 Regression] MVE: ICE (segfault) in arm_print_operand at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99727 Bug ID: 99727 Summary: [11 Regression] MVE: ICE (segfault) in arm_print_operand at -O3 Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug target/99727] [11 Regression] MVE: ICE (segfault) in arm_print_operand at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99727 Alex Coplan changed: What|Removed |Added Known to fail||11.0 Known to work|

[Bug target/99727] [11 Regression] MVE: ICE (segfault) in arm_print_operand at -O3 since r11-6616-g25bef689

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99727 Alex Coplan changed: What|Removed |Added CC||clyon at gcc dot gnu.org Summar

[Bug target/99748] New: MVE: Wrong code at -O0 with float to integer conversion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99748 Bug ID: 99748 Summary: MVE: Wrong code at -O0 with float to integer conversion Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priorit

[Bug target/99748] MVE: Wrong code at -O0 with float to integer conversion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99748 --- Comment #1 from Alex Coplan --- I should have mentioned, I found this because a number of the execution tests are failing when testing with --with-arch=armv8.1-m.main+mve --with-float=hard.

[Bug target/99748] MVE: Wrong code at -O0 with float to integer conversion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99748 --- Comment #2 from Alex Coplan --- GCC 10 also has the issue, so not a regression.

[Bug target/99727] [11 Regression] MVE: ICE (segfault) in arm_print_operand at -O3 since r11-6616-g25bef689

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99727 --- Comment #5 from Alex Coplan --- Thanks for the quick fix :)

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766 Alex Coplan changed: What|Removed |Added Last reconfirmed||2021-03-25 Ever confirmed|0

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766 --- Comment #2 from Alex Coplan --- The above ICEs with just -O3 -march=armv8.2-a+sve.

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766 Alex Coplan changed: What|Removed |Added Summary|[11 Regression] ICE: unable |[11 Regression] ICE: unable

[Bug c/99768] New: [11 Regression] Bogus -Wuninitialized diagnostic with type punning

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99768 Bug ID: 99768 Summary: [11 Regression] Bogus -Wuninitialized diagnostic with type punning Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug target/99758] ICE in setup_preferred_alternate_classes_for_new_pseudos, at ira.c:2772

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99758 Alex Coplan changed: What|Removed |Added CC||acoplan at gcc dot gnu.org,

[Bug target/96582] aarch64:ICE during GIMPLE pass: veclower

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96582 Alex Coplan changed: What|Removed |Added CC||acoplan at gcc dot gnu.org --- Comment #5

[Bug target/99773] ARM v8.1-m MVE interaction with -mfloat-abi not clear

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99773 Alex Coplan changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/99766] [11 Regression] ICE: unable to generate reloads with SVE code since r11-7807-gbe70bb5e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99766 --- Comment #7 from Alex Coplan --- Here is a testcase with SVE intrinsics that ICEs in the same way at -Os: $ cat test.cc #include char a; void c(unsigned &, const unsigned &); void d(char, bool, short, int, int, char e, int, short f, unsigned

[Bug target/99792] New: MVE: Assemble failure with "branch out of range" at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99792 Bug ID: 99792 Summary: MVE: Assemble failure with "branch out of range" at -O3 Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priorit

[Bug target/99813] New: SVE: Invalid assembly at -O3 (multiplier out of range in incb instruction)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99813 Bug ID: 99813 Summary: SVE: Invalid assembly at -O3 (multiplier out of range in incb instruction) Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: norma

[Bug target/99216] ICE in aarch64_sve::function_expander::expand() with LTO

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99216 --- Comment #8 from Alex Coplan --- Fixed on trunk. Needs backporting to GCC 10 together with bump to lto-streamer.h:LTO_minor_version.

[Bug target/97252] arm: ICE compiling pure-code/pr94538-2.c with MVE since r10-7293-g3eff57aa

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97252 Alex Coplan changed: What|Removed |Added Resolution|--- |FIXED Summary|[10 Regression] a

[Bug target/99820] New: aarch64: ICE (segfault) in aarch64_analyze_loop_vinfo with -moverride=tune=use_new_vector_costs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99820 Bug ID: 99820 Summary: aarch64: ICE (segfault) in aarch64_analyze_loop_vinfo with -moverride=tune=use_new_vector_costs Product: gcc Version: 11.0 Status: UNCONFIRMED

[Bug target/99820] aarch64: ICE (segfault) in aarch64_analyze_loop_vinfo with -moverride=tune=use_new_vector_costs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99820 Alex Coplan changed: What|Removed |Added Known to fail||11.0 Target Milestone|---

[Bug target/99829] New: MVE: ICE in lra_assign at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99829 Bug ID: 99829 Summary: MVE: ICE in lra_assign at -O3 Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Ass

[Bug rtl-optimization/99830] [11 Regression] ICE: in lra_eliminate_regs_1, at lra-eliminations.c:659 with -O2 -fno-expensive-optimizations -fno-split-wide-types -g

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99830 Alex Coplan changed: What|Removed |Added Last reconfirmed||2021-03-30 CC|

[Bug target/97701] [10 Regression] aarch64: ICE in extract_constrain_insn since r10-4447-g095f78c6

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97701 --- Comment #15 from Alex Coplan --- So fixed everywhere?

[Bug rtl-optimization/98601] [8/9/10/11 Regression] aarch64: ICE in rtx_addr_can_trap_p_1, at rtlanal.c:467

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98601 Alex Coplan changed: What|Removed |Added Summary|aarch64: ICE in |[8/9/10/11 Regression] |

[Bug rtl-optimization/98601] [8/9/10/11 Regression] aarch64: ICE in rtx_addr_can_trap_p_1, at rtlanal.c:467

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98601 Alex Coplan changed: What|Removed |Added Target Milestone|--- |11.0

[Bug rtl-optimization/98601] [8/9/10/11 Regression] aarch64: ICE in rtx_addr_can_trap_p_1, at rtlanal.c:467

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98601 Alex Coplan changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug target/99792] MVE: Assemble failure with "branch out of range" at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99792 --- Comment #2 from Alex Coplan --- Ok, I'd guess it just exposes a latent backend / rtl-optimization issue then

[Bug tree-optimization/97849] [10 Regression] aarch64: ICE (segfault) during GIMPLE pass: ifcvt since r10-3543-gf30b3d28

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97849 Alex Coplan changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/99469] ICE: qsort checking failed with selective scheduling on aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99469 --- Comment #3 from Alex Coplan --- Started with r8-6635-g3f26f054872c375e7f9a80ede7a56036d9b57597.

[Bug target/99748] MVE: Wrong code at -O0 with float to integer conversion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99748 Alex Coplan changed: What|Removed |Added Ever confirmed|0 |1 Assignee|unassigned at gcc dot

[Bug target/99647] arm: GCC generates invalid MVE vmov instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99647 Alex Coplan changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Assignee|unassigned at

[Bug target/99867] [10/11 Regression] ICE in to_constant, at poly-int.h:504

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99867 Alex Coplan changed: What|Removed |Added Ever confirmed|0 |1 CC|

[Bug target/99748] MVE: Wrong code at -O0 with float to integer conversion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99748 --- Comment #5 from Alex Coplan --- Fixed on trunk so far, needs a backport to GCC 10.

[Bug target/99929] New: SVE: Wrong code at -O2 -ftree-vectorize

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99929 Bug ID: 99929 Summary: SVE: Wrong code at -O2 -ftree-vectorize Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/99929] SVE: Wrong code at -O2 -ftree-vectorize

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99929 --- Comment #1 from Alex Coplan --- Slightly cleaner testcase: #include static void e(short *g, short p2) { *g ^= p2; } static short m[23]; int main() { for (unsigned i = 0; i < 23; ++i) m[i] = 4; if (svaddv(svptrue_pat_b32(SV_VL1), svd

[Bug testsuite/99955] New: gcc.c-torture/execute/pr92618.c violates strict aliasing rules

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99955 Bug ID: 99955 Summary: gcc.c-torture/execute/pr92618.c violates strict aliasing rules Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug target/99960] New: MVE: Wrong code storing V2DI vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99960 Bug ID: 99960 Summary: MVE: Wrong code storing V2DI vector Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/99960] MVE: Wrong code storing V2DI vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99960 --- Comment #1 from Alex Coplan --- Looks like both loads and stores are wrong in V2DImode: typedef long long __attribute((vector_size(16))) v2di; v2di load(v2di *p) { return *p; } void store(v2di *p, v2di v) { *p = v; } gives: load: v

[Bug target/99647] arm: GCC generates invalid MVE vmov instruction

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99647 --- Comment #4 from Alex Coplan --- Fixed on trunk so far.

[Bug target/99977] New: arm: ICE with __sync_bool_compare_and_swap and -mcpu=cortex-m23

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99977 Bug ID: 99977 Summary: arm: ICE with __sync_bool_compare_and_swap and -mcpu=cortex-m23 Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug target/99977] arm: ICE with __sync_bool_compare_and_swap and -mcpu=cortex-m23

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99977 --- Comment #1 from Alex Coplan --- I should have mentioned the testcase was reduced from gcc.dg/ia64-sync-3.c.

[Bug target/99977] arm: ICE with __sync_bool_compare_and_swap and -mcpu=cortex-m23

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99977 Alex Coplan changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |acoplan at gcc dot gnu.org Last

[Bug target/99988] New: aarch64: GCC generates excessive consecutive bti j instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99988 Bug ID: 99988 Summary: aarch64: GCC generates excessive consecutive bti j instructions Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug target/99988] aarch64: GCC generates excessive consecutive bti j instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99988 Alex Coplan changed: What|Removed |Added Known to fail||10.3.1, 9.3.1 --- Comment #1 from Alex Cop

[Bug target/99988] aarch64: GCC generates excessive consecutive bti j instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99988 Alex Coplan changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Ever confirmed|0

[Bug target/100000] New: arm: Missed optimisation storing V4DF vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=10 Bug ID: 10 Summary: arm: Missed optimisation storing V4DF vector Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: tar

[Bug rtl-optimization/99328] ICE: in verify_target_availability, at sel-sched.c:1557 with -fselective-scheduling2 on aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99328 Alex Coplan changed: What|Removed |Added Ever confirmed|0 |1 CC|

[Bug analyzer/100042] New: ICE in gimple_call_set_fndecl with -Os -fsanitize=undefined -flto -fanalyzer

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100042 Bug ID: 100042 Summary: ICE in gimple_call_set_fndecl with -Os -fsanitize=undefined -flto -fanalyzer Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: n

[Bug analyzer/100043] New: analyzer: ICE (segfault) in ana::region_model::on_assignment

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100043 Bug ID: 100043 Summary: analyzer: ICE (segfault) in ana::region_model::on_assignment Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/99328] ICE: in verify_target_availability, at sel-sched.c:1557 with -fselective-scheduling2 on aarch64

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99328 --- Comment #2 from Alex Coplan --- The original testcase started ICEing with r8-1511-gf28e54bd06f3733ff147128107a8da6d3e6d428e (so probably latent).

[Bug analyzer/100043] analyzer: ICE (segfault) in ana::region_model::on_assignment

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100043 Alex Coplan changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug analyzer/100011] [11 Regression] ICE in analyzer when generating path for -Wanalyzer-unsafe-call-within-signal-handler

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100011 Alex Coplan changed: What|Removed |Added CC||acoplan at gcc dot gnu.org --- Comment #5

[Bug target/99829] MVE: ICE in lra_assign at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99829 --- Comment #1 from Alex Coplan --- This one: int a, b, c; int d() { long e[210] = {}; long long f[9][1]; long g = c = 0; for (; c < 9; c++) f[c][0] = 9; if (f[4][0]) { long h = (int)&g; a = h; if (b) return (int)

[Bug analyzer/100042] ICE in gimple_call_set_fndecl with -Os -fsanitize=undefined -flto -fanalyzer

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100042 Alex Coplan changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCONFIRMED

[Bug analyzer/98599] [11 Regression] fatal error: Cgraph edge statement index out of range with -Os -flto -fanalyzer

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98599 --- Comment #16 from Alex Coplan --- *** Bug 100042 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/100087] New: Redundant extend with compare against zero for baseline Armv8-M

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100087 Bug ID: 100087 Summary: Redundant extend with compare against zero for baseline Armv8-M Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug target/99540] [10 Regression] ICE: Segmentation fault in aarch64_add_offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99540 --- Comment #12 from Alex Coplan --- Looks like this can be closed?

[Bug target/100106] New: [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106 Bug ID: 100106 Summary: [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e Product: gcc Version: 11.0 Status: UNCONFIRMED

[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106 Alex Coplan changed: What|Removed |Added Target||arm Keywords|

[Bug target/99960] MVE: Wrong code storing V2DI vector

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99960 Alex Coplan changed: What|Removed |Added Last reconfirmed||2021-04-20 Ever confirmed|0

[Bug target/99988] aarch64: GCC generates excessive consecutive bti j instructions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99988 --- Comment #4 from Alex Coplan --- Fixed on trunk. Keeping open for backports (once it's had some decent baking time).

[Bug rtl-optimization/99332] ICE:inreset_sched_cycles_in_current_ebb, at sel-sched.c:7147 with -fprofile-generate -O3 -fselective-scheduling -fselective-scheduling2 -fsel-sched-pipelining

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99332 Alex Coplan changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/100200] New: [10/11/12 Regression] UB evaluating aarch64_plus_immediate predicate

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100200 Bug ID: 100200 Summary: [10/11/12 Regression] UB evaluating aarch64_plus_immediate predicate Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal

[Bug tree-optimization/100201] New: Signed integer overflow in poly-int.h

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100201 Bug ID: 100201 Summary: Signed integer overflow in poly-int.h Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: tree-optim

[Bug tree-optimization/100201] Signed integer overflow in poly-int.h

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100201 --- Comment #2 from Alex Coplan --- (In reply to Martin Liška from comment #1) > Can you please show back-trace (export UBSAN_OPTIONS="print_stacktrace=1")? I didn't know ubsan did that, thanks! Here is the backtrace: /home/alecop01/toolchain/

[Bug target/100200] [10/11/12 Regression] UB evaluating aarch64_plus_immediate predicate

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100200 --- Comment #1 from Alex Coplan --- Backtrace is: #0 0x4340bc0 in aarch64_plus_immediate(rtx_def*, machine_mode) /home/alecop01/toolchain/src/gcc/gcc/config/aarch64/predicates.md:129 #1 0x2e0d168 in aarch64_rtx_costs /home/alecop01/tool

[Bug target/100200] [10/11/12 Regression] UB evaluating aarch64_plus_immediate predicate

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100200 --- Comment #2 from Alex Coplan --- Started with r10-3389-g835d50c66aa5bde2f354a6e63a2afa7d2f76a05a for the above testcase. That commit just introduces a use of aarch64_plus_immediate. The actual issue must be older.

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