[Bug target/99560] New: aarch64: ICE (segfault) in LRA with SVE intrinsics

[acoplan at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99560

            Bug ID: 99560
           Summary: aarch64: ICE (segfault) in LRA with SVE intrinsics
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: acoplan at gcc dot gnu.org
  Target Milestone: ---

For the following testcase on AArch64:

#include <arm_sve.h>
int foo(int x, int y);
void bar(int f, int g, int h, int i, int *j, int k[3][8][7]) {
  while (1) {
    int p = i ? foo(g, f) : 0;
    while (p) {
      j[p] = svaddv(svptrue_b8(),
          svadd_z(
            svmov_z(svnot_z(svptrue_b8(),
                svptrue_pat_b16(SV_VL5)),
                svptrue_pat_b8(SV_VL7)),
            svdup_u8(0),
            8));
       p += svaddv(
           svptrue_b8(),
           svadd_z(
               svptrue_b8(),
               svadd_z(svptrue_b8(), svdup_s64(j[f]), h - 4),
               svadd_z(
                   svptrue_b8(),
                   svadd_z(
                       svptrue_b8(),
                       svadd_z(svptrue_b8(),
                               svadd_z(svptrue_b8(), svdup_s64(0), 0),
                               svadd_z(svptrue_pat_b8(SV_VL16),
                                       svdup_s64(k[f][g][p]),
                                       svadd_z(svptrue_pat_b16(SV_VL5),
                                         svdup_s64(0), 0))
                               ),
                       f),
                   0)));
    }
  }
}

we ICE in LRA with:

$ aarch64-linux-gnu-gcc -c test.c -march=armv8.2-a+sve -O -ftrapv
during RTL pass: reload
test.c: In function ‘bar’:
test.c:34:1: internal compiler error: Segmentation fault
   34 | }
      | ^
0xdf33db crash_signal
        /home/alecop01/toolchain/src/gcc/gcc/toplev.c:327
0x198d63f recog_485
        /home/alecop01/toolchain/src/gcc/gcc/config/aarch64/aarch64.md:7305
0x198d63f recog(rtx_def*, rtx_insn*, int*)
        /home/alecop01/toolchain/src/gcc/gcc/config/aarch64/iterators.md:441
0xc0d47a recog_memoized
        /home/alecop01/toolchain/src/gcc/gcc/recog.h:273
0xc0d47a lra_set_insn_recog_data(rtx_insn*)
        /home/alecop01/toolchain/src/gcc/gcc/lra.c:964
0xc0e987 lra_get_insn_recog_data
        /home/alecop01/toolchain/src/gcc/gcc/lra-int.h:487
0xc0e987 lra_update_insn_regno_info(rtx_insn*)
        /home/alecop01/toolchain/src/gcc/gcc/lra.c:1625
0xc0ed4f lra_push_insn_1
        /home/alecop01/toolchain/src/gcc/gcc/lra.c:1780
0xc0ed4f lra_push_insn(rtx_insn*)
        /home/alecop01/toolchain/src/gcc/gcc/lra.c:1788
0xc0ef67 push_insns
        /home/alecop01/toolchain/src/gcc/gcc/lra.c:1831
0xc0f3df lra_process_new_insns(rtx_insn*, rtx_insn*, rtx_insn*, char const*)
        /home/alecop01/toolchain/src/gcc/gcc/lra.c:1871
0xc27f21 curr_insn_transform
        /home/alecop01/toolchain/src/gcc/gcc/lra-constraints.c:4664
0xc297a0 lra_constraints(bool)
        /home/alecop01/toolchain/src/gcc/gcc/lra-constraints.c:5158
0xc10443 lra(_IO_FILE*)
        /home/alecop01/toolchain/src/gcc/gcc/lra.c:2336
0xbc275a do_reload
        /home/alecop01/toolchain/src/gcc/gcc/ira.c:5834
0xbc275a execute
        /home/alecop01/toolchain/src/gcc/gcc/ira.c:6020
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