https://gcc.gnu.org/bugzilla/show_bug.cgi?id=32648
--- Comment #5 from Andrew Pinski ---
We even miss f3 into f4:
unsigned f3(unsigned a)
{
long b5 = (a & 0x20)>>5;
long b3 = (a & 0x08)>>3;
return b5 ^ b3;
}
unsigned f4(unsigned a)
{
unsigned b5 = (a ^ (a << 2));
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=32648
--- Comment #4 from Andrew Pinski ---
For ARM64 we get:
f1:
ubfxx1, x0, 5, 1
ubfxx0, x0, 3, 1
eor w0, w1, w0
ret
f2:
eor w0, w0, w0, lsl 2
ubfxx0, x0, 5, 1
ret
Which mi
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32648
--- Comment #3 from Andrew Pinski 2012-02-27
02:50:36 UTC ---
Right now on the trunk we produce:
movl%edi, %edx
movl%edi, %eax
shrl$3, %edx
shrl$5, %eax
xorl%edx, %eax
andl$1, %eax
ret
Which is
--- Comment #2 from rob1weld at aol dot com 2007-07-07 03:10 ---
There is a whole list of these optimizations at:
http://graphics.stanford.edu/~seander/bithacks.html
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=32648
--- Comment #1 from rguenth at gcc dot gnu dot org 2007-07-06 12:54 ---
Confirmed. This needs VRP of bits. The IL we generate is currently
bool b3;
bool b5;
int D.2483;
int D.2482;
int D.2481;
:
D.2481_2 = a_1(D) & 32;
b5_3 = D.2481_2 != 0;
D.2482_4 = a_1(D) & 8;
b3
