https://gcc.gnu.org/bugzilla/show_bug.cgi?id=32648
--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
For ARM64 we get:
f1:
ubfx x1, x0, 5, 1
ubfx x0, x0, 3, 1
eor w0, w1, w0
ret
f2:
eor w0, w0, w0, lsl 2
ubfx x0, x0, 5, 1
ret
Which might be just as the same really depending if the lsl is not split away
from the eor.
