https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
Uroš Bizjak changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
Uroš Bizjak changed:
What|Removed |Added
CC||maxim.yegorushkin at gmail dot
com
--- Co
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
--- Comment #11 from uros at gcc dot gnu.org ---
Author: uros
Date: Mon Sep 16 18:37:28 2019
New Revision: 275754
URL: https://gcc.gnu.org/viewcvs?rev=275754&root=gcc&view=rev
Log:
PR target/91719
* config/i386/i386.h (TARGET_USE_
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
--- Comment #10 from vekumar at gcc dot gnu.org ---
xchg is faster than mov+mfence on AMD Zen. We can add m_ZNVER1 | m_ZNVER2 to
the tuning.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
--- Comment #9 from vekumar at gcc dot gnu.org ---
(In reply to Jakub Jelinek from comment #8)
> CCing AMD too.
Sure Let me check if this tuning helps AMD Zen Arch.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
Jakub Jelinek changed:
What|Removed |Added
CC||vekumar at gcc dot gnu.org
--- Comment #
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
--- Comment #7 from Uroš Bizjak ---
Created attachment 46861
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=46861&action=edit
Proposed patch that introduces use_xchg_for_atomic_store
The patch introduces use_xchg_for_atomic_store and enabl
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
--- Comment #6 from Jakub Jelinek ---
Tried:
unsigned int a;
int
main ()
{
for (int i = 0; i < 1; i++)
__atomic_store_n (&a, i, __ATOMIC_SEQ_CST);
return 0;
}
and:
unsigned int a;
int
main ()
{
for (int i = 0; i < 1; i
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
Jakub Jelinek changed:
What|Removed |Added
CC||rth at gcc dot gnu.org
--- Comment #5 fr
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
--- Comment #4 from Uroš Bizjak ---
(In reply to Jakub Jelinek from comment #3)
> So, I guess we need to benchmark both and if xchg is beneficial on some
> CPUs, use it there guarded by some tuning flag.
Yes, my patch assumes that XCHG is benefi
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
--- Comment #3 from Jakub Jelinek ---
We do that if mfence isn't supported:
/* For seq-cst stores, when we lack MFENCE, use XCHG. */
if (is_mm_seq_cst (model) && !(TARGET_64BIT || TARGET_SSE2))
{
emit_insn (gen_atom
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91719
Uroš Bizjak changed:
What|Removed |Added
Status|UNCONFIRMED |ASSIGNED
Last reconfirmed|
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