https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102
--- Comment #8 from Kaze Emanuar ---
This code is just an example, but I have seen this issue appear in many of my
collision functions. I agree it's not a huge issue in my use case, but it'd
still be cool to have this work well. I can work aroun
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102
--- Comment #7 from Andrew Pinski ---
Also is this function from real code or just an example to show the issue?
I suspect in real code you either have 2 extra nops or a scheduling bubble. the
nops might not make a huge difference ...
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102
--- Comment #6 from Andrew Pinski ---
It just happened the scheduler didn't schedule it that way. Scheduling is NP
complete problem too.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102
--- Comment #5 from Andrew Pinski ---
/* True if mflo and mfhi can be immediately followed by instructions
which write to the HI and LO registers.
According to MIPS specifications, MIPS ISAs I, II, and III need
(at least) two instructi
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102
--- Comment #4 from Kaze Emanuar ---
I'm using the vr4300 (Nintendo 64). It does have the hazard between mult and
mflos. MULT can't be within 2 instructions of the MFLO. This shouldn't be an
issue here though since there were 3 instructions avai
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102
--- Comment #3 from Andrew Pinski ---
Which mips arch are you really trying to compile for?
Mips 1, 2, 4 or mips32 (r1-r5 or r6).
There are many different ones and mips32 (and above) does not have any delay
slots/hazards for the mult instruction
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102
--- Comment #2 from Andrew Pinski ---
-march=mips32r2 removes the nops. Iirc there was a hazard between the mflo and
mult instructions for older architectures.
