https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112102
--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
/* True if mflo and mfhi can be immediately followed by instructions
which write to the HI and LO registers.
According to MIPS specifications, MIPS ISAs I, II, and III need
(at least) two instructions between the reads of HI/LO and
instructions which write them, and later ISAs do not. Contradicting
the MIPS specifications, some MIPS IV processor user manuals (e.g.
the UM for the NEC Vr5000) document needing the instructions between
HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
MIPS64 and later ISAs to have the interlocks, plus any specific
earlier-ISA CPUs for which CPU documentation declares that the
instructions are really interlocked. */
#define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
|| TARGET_MIPS5500 \
|| TARGET_MIPS5900 \
|| TARGET_LOONGSON_2EF)
So the question becomes what are you compiling for?
