[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748 Kito Cheng changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748 --- Comment #3 from CVS Commits --- The master branch has been updated by Kito Cheng : https://gcc.gnu.org/g:8421f279e9eb00a2342ee3630dcdaf735b734fe8 commit r14-538-g8421f279e9eb00a2342ee3630dcdaf735b734fe8 Author: Juzhe-Zhong Date: Fri May

[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread pan2.li at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748 --- Comment #2 from Li Pan --- No, should be introduced by one optimization of Juzhe in GCC 14. Juzhe is working on fixing this, just open a bug on behalf of Juzhe for tracking.

[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748 --- Comment #1 from Kito Cheng --- Is this also happened in GCC 13 branch?