[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

[pan2.li at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748

--- Comment #2 from Li Pan <pan2.li at intel dot com> ---
No, should be introduced by one optimization of Juzhe in GCC 14. Juzhe is
working on fixing this, just open a bug on behalf of Juzhe for tracking.