https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
JuzheZhong changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #14 from CVS Commits ---
The master branch has been updated by Robin Dapp :
https://gcc.gnu.org/g:701b9309b687ed46188b9caeb7d88ad60b0212e5
commit r14-3910-g701b9309b687ed46188b9caeb7d88ad60b0212e5
Author: Juzhe-Zhong
Date: Tue S
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #13 from rsandifo at gcc dot gnu.org
---
(In reply to rguent...@suse.de from comment #6)
> I wonder whether SVE/GCN have those.
Just to answer this: yeah, SVE does have both vector and predicate
SEL (vcond_mask). So the fold is use
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #12 from Robin Dapp ---
Yes, as far as I know. I would also go ahead and merge the test suite patch
now as there is already a v2 fix posted. Even if it's not the correct one it
will be done soon so we should not let that block enab
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #11 from JuzheZhong ---
(In reply to Robin Dapp from comment #10)
> I would be OK with the riscv implementation, then we don't need to touch
> isel. Maybe a future vector extension will also help us here so we could
> just switch th
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #10 from Robin Dapp ---
I would be OK with the riscv implementation, then we don't need to touch isel.
Maybe a future vector extension will also help us here so we could just switch
the implementation then.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #9 from JuzheZhong ---
So, should we support this pattern in RISC-V backend ?
Or adjust gimple-isel to generate these 4 STMTs naturally?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #8 from Robin Dapp ---
Yes, I doubt we would get much below 4 instructions with riscv specifics.
A quick grep yesterday didn't reveal any aarch64 or gcn patterns for those (as
long as they are not hidden behind some pattern replacem
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #7 from JuzheZhong ---
(In reply to rguent...@suse.de from comment #6)
> On Tue, 12 Sep 2023, juzhe.zhong at rivai dot ai wrote:
>
> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
> >
> > --- Comment #5 from JuzheZhong ---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #6 from rguenther at suse dot de ---
On Tue, 12 Sep 2023, juzhe.zhong at rivai dot ai wrote:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
>
> --- Comment #5 from JuzheZhong ---
> Oh. I see.
>
>
> (define_expand "@vcond_
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #5 from JuzheZhong ---
Oh. I see.
(define_expand "@vcond_mask_"
[(match_operand:VB 0 "register_operand")
(match_operand:VB 3 "register_operand")
(match_operand:VB 1 "nonmemory_operand")
(match_operand:VB 2 "register_oper
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #4 from rguenther at suse dot de ---
On Tue, 12 Sep 2023, juzhe.zhong at rivai dot ai wrote:
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
>
> --- Comment #3 from JuzheZhong ---
> (In reply to Richard Biener from comment #
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
--- Comment #3 from JuzheZhong ---
(In reply to Richard Biener from comment #2)
> vect_patt_67.34_168 = VEC_COND_EXPR }>;
> vect_patt_68.35_169 = (vector([4,4]) int) vect_patt_67.34_168;
>
> ->
>
> vect_patt_68.35_169 = VEC_COND_EXPR }
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111337
Richard Biener changed:
What|Removed |Added
CC||rsandifo at gcc dot gnu.org
--- Commen
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