[Bug target/119210] [SME] 'smstart za' seems not to dominate the block that uses za register

2025-03-10 Thread xiezhiheng at huawei dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119210 --- Comment #7 from xiezhiheng at huawei dot com --- For other information, https://godbolt.org/z/xdPYGsjYd LLVM seems always dominate block .LBB0_14 .LBB0_11: add x23, x23, #1 msr TPIDR2_EL0, xzr cmp x23

[Bug target/119210] [SME] 'smstart za' seems not to dominate the block that uses za register

2025-03-10 Thread xiezhiheng at huawei dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119210 --- Comment #5 from xiezhiheng at huawei dot com --- (In reply to Andrew Pinski from comment #3) > So: > mrs x16, tpidr2_el0 > cbnzx16, .L22 <== it will branch to .L22, and miss 'smstart za' &g

[Bug target/119210] [SME] 'smstart za' seems not to dominate the block that uses za register

2025-03-10 Thread xiezhiheng at huawei dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119210 --- Comment #4 from xiezhiheng at huawei dot com --- (In reply to Andrew Pinski from comment #3) > So: > mrs x16, tpidr2_el0 > cbnzx16, .L22 <== it will branch to .L22, and miss 'smstart za' &g

[Bug target/119210] [SME] 'smstart za' seems not to dominate the block that uses za register

2025-03-10 Thread xiezhiheng at huawei dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119210 --- Comment #2 from xiezhiheng at huawei dot com --- (In reply to Andrew Pinski from comment #1) > Created attachment 60705 [details] > testcase > > -O2-march=armv9-a+sve+sve2+sme-f64f64 > > > Next time please att

[Bug c/119210] New: [SME] 'smstart za' seems not to dominate the block that uses za register

2025-03-10 Thread xiezhiheng at huawei dot com via Gcc-bugs
Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: xiezhiheng at huawei dot com Target Milestone: --- For this test case, https://godbolt.org/z/ceW9vPxz8 .L12: ldr d1, [x21, x19, lsl 3] mov

[Bug middle-end/94442] [10/11 regression] Redundant loads/stores emitted at -O3

2021-02-27 Thread xiezhiheng at huawei dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94442 --- Comment #9 from xiezhiheng at huawei dot com --- (In reply to Jakub Jelinek from comment #8) > So, is this fixed by any of the > r11-2190-gbf592b2ff776aef71c91924cdb5e0d10488496cf > r11-2448-g072a8b8fb6e861d8ac2db847bcc81dbcb1ef1

[Bug rtl-optimization/96756] New: [AArch64] Missed FPSR description on saturating instruction patterns

2020-08-23 Thread xiezhiheng at huawei dot com
Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: xiezhiheng at huawei dot com Target Milestone: --- Target: aarch64 Test case: #include #include typedef union { struct { int _xxx:24; unsigned

[Bug tree-optimization/94442] [10/11 regression] Redundant loads/stores emitted at -O3

2020-06-28 Thread xiezhiheng at huawei dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94442 --- Comment #6 from xiezhiheng at huawei dot com --- I'm trying to modify get_inner_reference to handle the case for MEM[ptr, off]. I extract the "off" and add it to the recorded offset, then I build a MEM[ptr, 0] and return it la

[Bug tree-optimization/94442] [10/11 regression] Redundant loads/stores emitted at -O3

2020-05-06 Thread xiezhiheng at huawei dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94442 --- Comment #4 from xiezhiheng at huawei dot com --- (In reply to Richard Biener from comment #3) > So I wonder why > > a$vect_s8$0_4 = MEM[(const struct __m256i &)output_5(D) + 32].vect_s8[0]; > > necessarily emits t

[Bug rtl-optimization/94442] New: [AArch64] Redundant ldp/stp instructions emitted at -O3

2020-04-01 Thread xiezhiheng at huawei dot com
Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: xiezhiheng at huawei dot com Target Milestone: --- Target: aarch64 Test case: #include struct __m256i { int8x16_t vect_s8[2]; }; __attribute__((inline)) __m256i