[Bug target/118501] [14 regression] aarch64: ICE in simplify_context::simplify_subreg

2025-04-16 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118501 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/119133] [14 Regression] ICE: SIGSEGV in mark_label_nuses (emit-rtl.cc:3896) with -O -fno-tree-ter and _Float16 since r14-1131

2025-04-16 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119133 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/115258] [14 Regression] register swaps for vector perm in some cases after r14-6290

2025-04-16 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115258 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/119399] [12/13/14 Backport] Overlap check in vectorized code may invoke UB

2025-04-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119399 Richard Sandiford changed: What|Removed |Added Summary|Overlap check in vectorized |[12/13/14 Backport] Overlap

[Bug target/119610] [12/13/14/15 regression] aarch64: Wrong unwind info with -fstack-clash-protection -fstack-protector-strong since r14-3900-g3e4afea3b192c2

2025-04-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #5 from Richard Sandiford --- Mine.

[Bug tree-optimization/119399] Overlap check in vectorized code may invoke UB

2025-04-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119399 --- Comment #5 from Richard Sandiford --- (In reply to rguent...@suse.de from comment #4) > >, so for a 4-element > > vector, the only problem cases are p==q+4, p==q+8 and p==q+12. That's > > equivalent to testing whether the unsigned value p-(

[Bug tree-optimization/119399] Overlap check in vectorized code may invoke UB

2025-04-09 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #3 from Richard Sandiford --- Taking for the pointer difference. (In reply to Richard Biener from comment #2) > Still the actual alias check looks prone to overflow issues since we do > not distinguish before/after pla

[Bug bootstrap/119689] [15 Regression] Bootstrap comparison failure on i586-linux since r15-9239

2025-04-09 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119689 --- Comment #14 from Richard Sandiford --- (In reply to Richard Biener from comment #13) > diff --git a/gcc/lra-remat.cc b/gcc/lra-remat.cc > index 2f3afffcf5b..5f823193aa7 100644 > --- a/gcc/lra-remat.cc > +++ b/gcc/lra-remat.cc > @@ -460,7 +46

[Bug bootstrap/119689] [15 Regression] Bootstrap comparison failure on i586-linux since r15-9239

2025-04-09 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #10 from Richard Sandiford --- Mine.

[Bug tree-optimization/104200] [12/13/14/15 Regression] FAIL: gcc.target/aarch64/atomic-inst-cas.c (test for excess errors) fails

2025-04-09 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104200 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-04-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116398 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug c++/116595] default-initialization of vfloat32m1x4_t (RISCV V) or svfloat32x4_t (Armv9-a SVE) causes ICE

2025-04-03 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116595 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug rtl-optimization/97286] simplified subreg used outside of the loop can cause conflict and cause an extra move inside the loop

2025-04-01 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97286 --- Comment #9 from Richard Sandiford --- (In reply to ktkachov from comment #8) > Richard, do you think this is something early-ra in aarch64 is well-placed > to address? Or is there perhaps a realistic IRA solution? I don't think the RAs can ha

[Bug rtl-optimization/97286] simplified subreg used outside of the loop can cause conflict and cause an extra move inside the loop

2025-04-01 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97286 --- Comment #10 from Richard Sandiford --- (In reply to Richard Sandiford from comment #9) > … Or perhaps we > could do the optimisation in gimple, so that there is only one loop-carried > dependency coming into expand. That is, replace: [loc

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-03-31 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #28 from Richard Sandiford --- I'm back from holiday, so taking. (In reply to Segher Boessenkool from comment #26) > So, the one thing I really worry about a bit: will everything still work if > we can lose some l

[Bug target/119495] 8% slowdown of 436.cactusADM on AMD Zen2 since r15-7895-gb191e8bdecf881

2025-03-31 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119495 --- Comment #2 from Richard Sandiford --- (In reply to Filip Kastl from comment #0) > So my understanding is that this slowdown isn't really that important. > However, it seemed reasonable to at least notify Richard Sandiford about > this in ca

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-03-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116398 --- Comment #23 from Richard Sandiford --- (In reply to Segher Boessenkool from comment #22) > (In reply to Richard Sandiford from comment #18) > > but: the problem in PR101523 was that, after each > > successful 2->2 attempt, distribute_links w

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-03-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116398 --- Comment #20 from Richard Sandiford --- (In reply to Richard Sandiford from comment #18) > Still more than 0% of course, but nevertheless much less than before. than before the fix for PR101523 went in, I mean.

[Bug rtl-optimization/116398] [15 Regression] gcc.target/aarch64/ashltidisi.c fails since r15-268

2025-03-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116398 --- Comment #18 from Richard Sandiford --- Created attachment 60754 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60754&action=edit Proof of concept patch with hard-coded limit I'd been reluctant to get involved in this for fear of creat

[Bug tree-optimization/119287] [15 regression] ICE when building linux-6.12.19 (error: type mismatch in binary expression) since r15-8025

2025-03-14 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119287 --- Comment #4 from Richard Sandiford --- (In reply to Jakub Jelinek from comment #3) > tree_nop_conversion_p certainly doesn't imply the two types are compatible > types. > So, I think we should go with > --- gcc/match.pd.jj 2025-03-13 14:05:

[Bug testsuite/113965] gcc.target/aarch64/sve/mask_struct_load_3_run.c still fails with qemu due to _Float16 rounding error

2025-03-13 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113965 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug testsuite/113965] gcc.target/aarch64/sve/mask_struct_load_3_run.c still fails with qemu due to _Float16 rounding error

2025-03-13 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org CC||rsandifo at gcc dot gnu.org Ever confirmed|0 |1 Last reconfirmed||2025-03-13 --- Comment #4 from Richard Sandiford --- Mine

[Bug target/115248] [15 regresion] aarch64/sve/pre_cond_share_1.c fails since r15-276-gbed6ec161be8c5

2025-03-13 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115248 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/115248] [15 regresion] aarch64/sve/pre_cond_share_1.c fails since r15-276-gbed6ec161be8c5

2025-03-12 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115248 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/116901] [15 Regression] pr110625_4.c fails on aarch64 since r15-3794-g2c04f175de4f39

2025-03-12 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116901 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/118956] [15 regression] gcc.target/aarch64/sve/pred-not-gen-[14].c fail after r15-268-g9dbff9c05520a74e

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118956 --- Comment #4 from Richard Sandiford --- XFAILed for GCC 15, keeping open for the actual fix.

[Bug tree-optimization/118976] [12 Regression] Correctness Issue: SVE vectorization results in data corruption when cpu has 128bit vectors but compiled with -mcpu=neoverse-v1 (which is only for 256bit

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118976 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 116238, which changed state. Bug 116238 Summary: [12 Regression] ICE building 526.blender_r on aarch64 SVE after r15-1619-g3b9b8d6cfdf593 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116238 What|Removed

[Bug rtl-optimization/116238] [12 Regression] ICE building 526.blender_r on aarch64 SVE after r15-1619-g3b9b8d6cfdf593

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116238 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/117045] [12 Backport] Incorrect fold of SVE's svwhilele

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117045 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/117045] [12 Backport] Incorrect fold of SVE's svwhilele

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117045 --- Comment #8 from Richard Sandiford --- Fixed

[Bug rtl-optimization/116564] [12/13/14/15 Regression] aarch64: gcc hangs when compiling vst2_f64 instrinsic at -O1 and above since r12-4910-g66f206b853

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116564 --- Comment #7 from Richard Sandiford --- (In reply to Alex Coplan from comment #6) > So I'm testing the following to do this (which so far survives bootstrap on > aarch64): > > diff --git a/gcc/df-problems.cc b/gcc/df-problems.cc > index f3218

[Bug target/119114] [14/15 regression] RISC-V: miscompile at -O3 since r14-4077-g86451305d8b

2025-03-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119114 --- Comment #21 from Richard Sandiford --- Perhaps I'm missing the point, but I don't think we should look at 1 vs -1 for . has only a single bit. That bit is interpreted as a sign bit for extension purposes, but that only matters when an ext

[Bug target/116901] [15 Regression] pr110625_4.c fails on aarch64 since r15-3794-g2c04f175de4f39

2025-03-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116901 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug rtl-optimization/119174] [15 Regression] IRA allocating value live across a call to call clobbered register

2025-03-10 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119174 --- Comment #13 from Richard Sandiford --- (In reply to Jeffrey A. Law from comment #11) > Andrew. You're missing the point. This scenario isn't the kind of thing > that reload and LRA are supposed to fix. They fix constraint problems. ie, >

[Bug target/119133] [14 Regression] ICE: SIGSEGV in mark_label_nuses (emit-rtl.cc:3896) with -O -fno-tree-ter and _Float16 since r14-1131

2025-03-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119133 Richard Sandiford changed: What|Removed |Added Summary|[14/15 Regression] ICE: |[14 Regression] ICE:

[Bug tree-optimization/116125] [12/13/14 Regression] Does not fully checking for overlapping memory regions with the vectorizer

2025-03-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116125 Richard Sandiford changed: What|Removed |Added Summary|[12/13/14/15 Regression]|[12/13/14 Regression] Does

[Bug target/119156] Placement of PTRUE instructions prevents PTEST elimination

2025-03-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119156 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/119156] New: Placement of PTRUE instructions prevents PTEST elimination

2025-03-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
-optimization Severity: enhancement Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org CC: tnfchris at gcc dot gnu.org Target Milestone: --- Target: aarch64*-*-* Tamar

[Bug tree-optimization/116125] [12/13/14/15 Regression] Does not fully checking for overlapping memory regions with the vectorizer

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116125 --- Comment #5 from Richard Sandiford --- (In reply to Richard Biener from comment #3) > We document > > class dr_with_seg_len > { > ... > /* The minimum common alignment of DR's start address, SEG_LEN and > ACCESS_SIZE. */ > unsign

[Bug target/119142] [15 Regression] Many regressions since r15-7852 on i686-linux

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119142 --- Comment #1 from Richard Sandiford --- Sorry, I thought Honza had regression-tested it on x86, but I realise now that I didn't confirm whether he had. I reverted the patch in r15-7862-g2c6ab4c443ae3278.

[Bug target/118957] [15 Regression] 5-9% slowdown of 511.povray_r and 453.povray since r15-7400-gd3ff498c478ace

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118957 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/118959] [15 Regression] 5-14% slowdown of 400.perlbench since r15-7400-gd3ff498c478ace

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118959 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/117477] Register allocator chooses a slot location instead a new callee saved register and not taking inot account pair allocation

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117477 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/119133] [14/15 Regression] ICE: SIGSEGV in mark_label_nuses (emit-rtl.cc:3896) with -O -fno-tree-ter and _Float16 since r14-1131

2025-03-06 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #2 from Richard Sandiford --- Mine.

[Bug target/118531] [14 Regression] aarch64/ins_bitfield_1.c generates INS instructions even for +nosimd

2025-03-04 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118531 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Known to work|

[Bug tree-optimization/118976] [12/13/14 regression] Correctness Issue: SVE vectorization results in data corruption when cpu has 128bit vectors but compiled with -mcpu=neoverse-v1 (which is only for

2025-03-04 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118976 Richard Sandiford changed: What|Removed |Added Summary|[12/13/14/15 regression]|[12/13/14 regression]

[Bug rtl-optimization/119002] [15 Regression] Comparison miscompilation on ppc64le and s390x since r15-6777

2025-03-04 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119002 Richard Sandiford changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug tree-optimization/116125] [12/13/14/15 Regression] Does not fully checking for overlapping memory regions with the vectorizer

2025-03-03 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116125 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug tree-optimization/118976] [12/13/14/15 regression] Correctness Issue: SVE vectorization results in data corruption when cpu has 128bit vectors but compiled with -mcpu=neoverse-v1 (which is only f

2025-03-03 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118976 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug rtl-optimization/116604] [15 regression] regressions on aarch64 since r15-1619-g3b9b8d6cfdf593

2025-02-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116604 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/118956] New: [15 regression] gcc.target/aarch64/sve/pred-not-gen-[14].c fail after r15-268-g9dbff9c05520a74e

2025-02-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
Status: UNCONFIRMED Keywords: missed-optimization, testsuite-fail Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rsandifo at gcc dot gnu.org Target Milestone

[Bug rtl-optimization/118956] [15 regression] gcc.target/aarch64/sve/pred-not-gen-[14].c fail after r15-268-g9dbff9c05520a74e

2025-02-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118956 --- Comment #1 from Richard Sandiford --- Created attachment 60541 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60541&action=edit candidate patch This patch changes the patterns so that they don't require a scratch register post-reload.

[Bug target/118952] AArch64 get_fpcr and set_fpcr builtins don't block reordering of operations past them

2025-02-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118952 --- Comment #3 from Richard Sandiford --- (In reply to ktkachov from comment #2) > Thanks, yeah I don't see PR34678 getting generally resolved any time soon. > Is there something we could do with these particular builtins to make them a > strong

[Bug target/118952] AArch64 get_fpcr and set_fpcr builtins don't block reordering of operations past them

2025-02-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
||a/show_bug.cgi?id=34678 CC||rsandifo at gcc dot gnu.org --- Comment #1 from Richard Sandiford --- I think this is essentially the same problem as PR34678.

[Bug rtl-optimization/116604] [15 regression] regressions on aarch64 since r15-1619-g3b9b8d6cfdf593

2025-02-19 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116604 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/117978] Optimise 128-bit-predicated SVE loads to Advanced SIMD LDRs

2025-02-18 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117978 --- Comment #5 from Richard Sandiford --- (In reply to ktkachov from comment #4) > Do we also need to guard this under TARGET_NON_STREAMING? Hopefully it should work for all cases. LDR Q and STR Q are still available in streaming mode.

[Bug target/118892] [14/15 Regression] ICE (segfault) in rebuild_jump_labels on aarch64-linux-gnu since r14-5289

2025-02-18 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118892 --- Comment #10 from Richard Sandiford --- (In reply to Tamar Christina from comment #9) > I swear that was something that was fixed. But in any case, the simplest > fix is to force it into a reg again indeed. > > I'm slightly worried that thi

[Bug rtl-optimization/118611] LRA inserts unneeded reload on FMA chain

2025-02-17 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118611 --- Comment #9 from Richard Sandiford --- (In reply to Vladimir Makarov from comment #7) > Unfortunately, although the patch solves the problem but it adds 2 x86-64 > failures of tests expecting smaller number of moves. It also adds 2 > failure

[Bug tree-optimization/108608] [12 Regression] AArch64 vectorizer ICE in vect_transform_reduction and __builtin_fmax

2025-02-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108608 --- Comment #12 from Richard Sandiford --- (In reply to fengfei.xi from comment #11) > could you please explain under what specific circumstances this change might > lead to slower performance? > Also, is there a more complete fix or any plans f

[Bug rtl-optimization/118755] [15 Regression] ccmp_3.c fails on aarch64

2025-02-11 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118755 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/118328] Implement preserve_none for AArch64

2025-02-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118328 --- Comment #14 from Richard Sandiford --- (In reply to Sam James from comment #13) > The request here notwithstanding, bug report(s) with testcases for missed > opportunities in ipa-ra would be welcome too. Agreed, if we find any. But just in

[Bug target/117477] Register allocator chooses a slot location instead a new callee saved register and not taking inot account pair allocation

2025-02-07 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117477 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug target/115673] [15 regression] gcc.target/i386/force-indirect-call-2.c test failure since r15-1619-g3b9b8d6cfdf593

2025-01-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115673 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/118429] [15 regression] ICE when building poppler-24.11.0 on arm64 (in process_uses_of_deleted_def, at rtl-ssa/changes.cc:276) since r15-6551

2025-01-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118429 Richard Sandiford changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/118320] [14/15 Regression] internal compiler error: Segmentation fault in aarch64-ldp-fusion.cc

2025-01-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
||rsandifo at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #13 from Richard Sandiford --- Mine

[Bug target/118429] [15 regression] ICE when building poppler-24.11.0 on arm64 (in process_uses_of_deleted_def, at rtl-ssa/changes.cc:276) since r15-6551

2025-01-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #12 from Richard Sandiford --- Mine

[Bug rtl-optimization/117922] [15 Regression] 1000% compilation time slow down on the testcase from pr26854

2025-01-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117922 --- Comment #23 from Richard Sandiford --- FWIW, running locally on x86 with fold_mem_offsets disabled (admittedly with rtl checking), I see: combiner : 0.91 ( 0%)21M ( 0%) late combiner

[Bug rtl-optimization/117922] [15 Regression] 1000% compilation time slow down on the testcase from pr26854

2025-01-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117922 --- Comment #21 from Richard Sandiford --- I should have said, but: another reason for suggesting rtl-ssa is that it is usually self-updating. My long-term hope is that we'll be able to maintain it between passes, when we have consecutive passe

[Bug rtl-optimization/117922] [15 Regression] 1000% compilation time slow down on the testcase from pr26854

2025-01-29 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117922 --- Comment #19 from Richard Sandiford --- Mind if I take this and try converting it to rtl-ssa? I think that would be more forward-looking, rather than adding more custom (dominator walk) code to the pass itself. Also, the switch to rtl-ssa d

[Bug target/117202] RISC-V: SLP permutation for VLA vectors broken

2025-01-28 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117202 Richard Sandiford changed: What|Removed |Added CC||juzhe.zhong at rivai dot ai,

[Bug tree-optimization/117202] SLP permutation for VLA vectors broken

2025-01-28 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117202 --- Comment #5 from Richard Sandiford --- FWIW, gcc.target/riscv/rvv/autovec/struct/mask_struct_store_run-3.c seems to produce similar VEC_PERM_EXPRs for SVE, but it works there. The idea is that we're unpacking one vector of [16,16] chars into

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

2025-01-28 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 117270, which changed state. Bug 117270 Summary: [15 Regression] 9% exec time slowdown of 538.imagick_r on aarch64 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117270 What|Removed |Adde

[Bug target/117270] [15 Regression] 9% exec time slowdown of 538.imagick_r on aarch64

2025-01-28 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117270 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/118638] [14/15 Regression] Miscompile with -Os and -O0/1/2/3 since r14-4810

2025-01-27 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118638 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug tree-optimization/118669] Misaligned store after vectorization without using misaligned type with SVE

2025-01-27 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|UNCONFIRMED Assignee|rsandifo at gcc dot gnu.org|unassigned at gcc dot gnu.org --- Comment #9 from Richard Sandiford --- Probably best if I unassign myself then, because I don't really see where the wrong code is.

[Bug tree-optimization/118650] `(even + unknown) & 1` is not optimized to just `unknown & 1` at gimple level

2025-01-27 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118650 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/118669] Misaligned store after vectorization without using misaligned type with SVE

2025-01-27 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org Status|NEW |ASSIGNED --- Comment #7 from Richard Sandiford --- diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc index c0550acf6b2..06cd6e42355 100644 --- a/gcc/tree-vect-stmts.cc

[Bug target/118669] Misaligned store after vectorization without using misaligned type with SVE

2025-01-27 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118669 --- Comment #6 from Richard Sandiford --- (In reply to rguent...@suse.de from comment #5) > On Mon, 27 Jan 2025, rsandifo at gcc dot gnu.org wrote: > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118669 > > > > ---

[Bug target/118669] Misaligned store after vectorization without using misaligned type with SVE

2025-01-27 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118669 --- Comment #4 from Richard Sandiford --- Just to be sure I understand: is the PR simply about making the RTL representation of the memory more correct? Or is it about generating different code?

[Bug target/118103] [15 Regression] GCC miscompile rvv intrinsics at `-O3`, missing the `fsrm` instruction to the recover status of frm CSR

2025-01-24 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
gcc dot gnu.org|unassigned at gcc dot gnu.org --- Comment #7 from Richard Sandiford --- The problem seems to be in the modelling of the FRM register. CALL_USED_REGISTERS says that the register is call-clobbered/caller-save, which means: (a) it is not treated as live on entry to the

[Bug target/118103] [15 Regression] GCC miscompile rvv intrinsics at `-O3`, missing the `fsrm` instruction to the recover status of frm CSR

2025-01-24 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
||2025-01-24 Status|UNCONFIRMED |ASSIGNED CC||rsandifo at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #6 from Richard Sandiford --- Mine.

[Bug rtl-optimization/118611] LRA inserts unneeded reload on FMA chain

2025-01-24 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
|UNCONFIRMED |NEW Ever confirmed|0 |1 CC||rsandifo at gcc dot gnu.org --- Comment #4 from Richard Sandiford --- I think the problem is IRA rather than LRA. As a result of the quoted instruction, IRA realises

[Bug rtl-optimization/118562] [15 Regression] SEGV in late-combine (rtl_ssa::function_info::remove_use)

2025-01-23 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118562 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug rtl-optimization/118562] [15 Regression] SEGV in late-combine (rtl_ssa::function_info::remove_use)

2025-01-22 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118562 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug middle-end/118594] expansion of bf16 to float should not produce (subreg (mem ())

2025-01-22 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118594 --- Comment #9 from Richard Sandiford --- (In reply to Richard Sandiford from comment #8) > But that doesn't work because force_operand considers the subreg to be valid > (and general_operand agrees). …because the subreg isn't paradoxical, I for

[Bug middle-end/118594] expansion of bf16 to float should not produce (subreg (mem ())

2025-01-22 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118594 --- Comment #8 from Richard Sandiford --- I was going to say that force_subreg should call force_operand: diff --git a/gcc/explow.cc b/gcc/explow.cc index 7799a98053b..3f378174268 100644 --- a/gcc/explow.cc +++ b/gcc/explow.cc @@ -759,7 +759,9

[Bug target/118184] [14 backport] glibc regression on aarch64 due to early_ra deleting movti instruction since r15-5422-g279475fd7236a9

2025-01-22 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118184 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug middle-end/118443] [Meta bug] Bugs triggered by and blocking more smtgcc testing

2025-01-22 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118443 Bug 118443 depends on bug 117186, which changed state. Bug 117186 Summary: [12/13 Regression] aarch64 wrong code for (a < b) < (b < a) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117186 What|Removed |Added ---

[Bug rtl-optimization/117186] [12/13 Regression] aarch64 wrong code for (a < b) < (b < a)

2025-01-22 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117186 Richard Sandiford changed: What|Removed |Added Summary|[12/13/14 Regression] |[12/13 Regression] aarch64

[Bug target/118348] [15 Regression] [SVE] HACCKernels seems to miscompile with VLS SVE after 0c5c0c959c2e592b84739f19ca771fa69eb8dfee

2025-01-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118348 Richard Sandiford changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/118384] unexpected call to __muldi3 generated for riscv target

2025-01-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118384 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/118531] [14 Regression] aarch64/ins_bitfield_1.c generates INS instructions even for +nosimd

2025-01-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118531 Richard Sandiford changed: What|Removed |Added Summary|[14/15 Regression] |[14 Regression] |

[Bug target/118501] [14 regression] aarch64: ICE in simplify_context::simplify_subreg

2025-01-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118501 Richard Sandiford changed: What|Removed |Added Summary|[14/15 regression] aarch64: |[14 regression] aarch64:

[Bug target/118348] [15 Regression] [SVE] HACCKernels seems to miscompile with VLS SVE after 0c5c0c959c2e592b84739f19ca771fa69eb8dfee

2025-01-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
||rsandifo at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org --- Comment #6 from Richard Sandiford --- Mine (after discussing with Tamar).

[Bug target/117270] [15 Regression] 9% exec time slowdown of 538.imagick_r on aarch64

2025-01-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117270 Richard Sandiford changed: What|Removed |Added Assignee|tnfchris at gcc dot gnu.org|rsandifo at gcc dot gnu.org

[Bug target/118501] [14/15 regression] aarch64: ICE in simplify_context::simplify_subreg

2025-01-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118501 Richard Sandiford changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rsandifo at gcc dot gnu.org

[Bug testsuite/118547] gcc.c-torture/compile/pr106433.c and others fail on aarch64 with an older binutils

2025-01-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118547 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug tree-optimization/118544] -fopt-info misreports unroll factor when using #pragma GCC unroll

2025-01-20 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118544 Richard Sandiford changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org

[Bug target/117013] aarch64 should define spaceship4 optab

2025-01-17 Thread rsandifo at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117013 Richard Sandiford changed: What|Removed |Added Status|NEW |ASSIGNED --- Comment #5 from Richar

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