https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120447
--- Comment #8 from Richard Sandiford <rsandifo at gcc dot gnu.org> ---
I think we've already got the right condition for partial modes:
/* If the predicate in operands[2] is a patterned SVE PTRUE predicate
with patterns VL1, VL2, VL4, VL8, or VL16 and at most the bottom
128 bits are loaded/stored, emit an ASIMD load/store. */
int vl = aarch64_partial_ptrue_length (operands[2]);
int width = vl * GET_MODE_UNIT_BITSIZE (mode);
if (width <= 128
&& pow2p_hwi (vl)
&& (vl == 1
|| (!BYTES_BIG_ENDIAN
&& aarch64_classify_vector_mode (mode) == VEC_SVE_DATA)))
{
That is, we allow partial modes if the load is a zero-extend of a single
element (vl==1), but disallow them when the loaded data spans multiple elements
(vl>1). This is something that I remember considering during the review.
Like I say, please don't rush into an AArch64 workaround!
