[Bug testsuite/77317] x86_64 --target_board=''unix/ unix/-m32'' parallel testrun gives inconsistent results in gcc.dg/vect

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77317 --- Comment #1 from Robert Suchanek --- I see what the problem is. During mechanical change I "fixed" global variable name(s) in this and in a few other procedures that appeared that they should have cached the result. A quick look at my patch

[Bug rtl-optimization/66204] New: [MIPS] LRA: Non-optimal code / regression

-optimization Assignee: unassigned at gcc dot gnu.org Reporter: robert.suchanek at imgtec dot com Target Milestone: --- Hi Vlad, Whilst looking into whether pr65862 is resolved for good, I came across a case where data is not loaded into a floating-pointer register directly with

[Bug rtl-optimization/65862] [MIPS] IRA/LRA issue: integers spilled to floating-point registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65862 --- Comment #12 from Robert Suchanek --- Thanks Vlad. The regression in clean on MIPS. I'll send a patch along with the testcase(s) once the core part it's committed on the trunk.

[Bug rtl-optimization/65862] [MIPS] IRA/LRA issue: integers spilled to floating-point registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65862 --- Comment #10 from Robert Suchanek --- Hi Vlad, I'm pleased with the results so far. In the larger codebase, it behaves as the original patch reverted and I haven't seen a missed case. The code size doesn't seem to be hurt either. I see ~0.5

[Bug rtl-optimization/65862] [MIPS] IRA/LRA issue: integers spilled to floating-point registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65862 --- Comment #5 from Robert Suchanek --- Sorry for late reply, I was on vacation. > The costs are equal if cost of moving general regs to/from fp regs or > memory are equal. So it looks ok to me. > > r218 spilled in IRA is reassigned to a fp re

[Bug middle-end/65877] New: ICE: various internal errors with attribute(target) when mixing generic and non-generic vectors

Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: robert.suchanek at imgtec dot com I came across some ICEs whilst implementing target attribute for MIPS and it appears to be more generic. At least

[Bug rtl-optimization/65862] [MIPS] IRA/LRA issue: integers spilled to floating-point registers

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65862 --- Comment #2 from Robert Suchanek --- That's correct. It was just easier to expose this problem by compiling the kernel.

[Bug rtl-optimization/65862] New: [MIPS] IRA/LRA issue: integers spilled to floating-point registers

Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: robert.suchanek at imgtec dot com CC: matthew.fortune at imgtec dot com, vmakarov at redhat dot com, wdijkstr at arm dot com Following

[Bug rtl-optimization/63823] [5.0 Regression] MIPS will not build due to LRA ICE with 64 bit ABI

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63823 --- Comment #8 from Robert Suchanek --- Yes, the patch works. Glibc built fine on mips64-linux-gnu target. Thanks Vlad.

[Bug rtl-optimization/63823] [5.0 Regression] MIPS will not build due to LRA ICE with 64 bit ABI

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63823 --- Comment #5 from Robert Suchanek --- It appears that enabling the debug info can trigger the ICE. In the testcase, after the patch, an instruction 1136 gets deleted and all references to pseudo 704 meant to be updated. The following change in

[Bug target/59460] [4.9 Regression] ICE with -mips16 and __attribute__((nomips16))

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59460 --- Comment #1 from Robert Suchanek --- Ping Where should I look at or what else could be done to resolve this without reverting the patch for pr58115?

[Bug target/59460] New: [4.9 Regression] ICE with -mips16 and __attribute__((nomips16))

Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: robert.suchanek at imgtec dot com Target: mips16 A number of failures started to appear on the trunk for mips-elf target (possibly other targets too) and all of the new

[Bug rtl-optimization/59317] [4.9 Regression] [LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59317 Robert Suchanek changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug rtl-optimization/59317] [4.9 Regression] [LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59317 --- Comment #5 from Robert Suchanek --- Dump attached. Ah, it's not triggered on mips16-linux target but mips-elf. I double checked it with the same svn revision.

[Bug rtl-optimization/59317] [4.9 Regression] [LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59317 --- Comment #4 from Robert Suchanek --- Created attachment 31384 --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=31384&action=edit LRA dump for testcase

[Bug rtl-optimization/59317] [4.9 Regression] [LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints)

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59317 --- Comment #2 from Robert Suchanek --- The latest patches do not seem to resolve the issue. Although the newly generated pseudos get ALL_REGS class assigned, the class change does not happen later. As the class is not changed, hard regs are foun

[Bug rtl-optimization/59317] New: [4.9 Regression] [LRA,MIPS] ICE: in check_rtl, at lra.c (insn does not satisfy constraints)

Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: robert.suchanek at imgtec dot com CC: vmakarov at redhat dot com Created attachment 31311 --> http://gcc.gnu.org/bugzi