[Bug target/121821] [16 regression] profiledbootstrap fails to build on armv8l since r16-496-gcc74e2f2b39b6d

2025-09-09 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121821 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|2025-09-06 00:0

[Bug target/121821] [16 regression] profiledbootstrap fails to build on armv8l since r16-496-gcc74e2f2b39b6d

2025-09-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121821 --- Comment #3 from Richard Earnshaw --- Created attachment 62347 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=62347&action=edit compressed pre-processed source Confirmed. Another possibility is that it's something to do with the switc

[Bug target/121810] Out-of-range literal pool entry for MVE const vector

2025-09-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121810 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/121810] Out-of-range literal pool entry for MVE const vector

2025-09-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121810 Richard Earnshaw changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rearnsha at gcc dot gnu.org

[Bug target/121810] New: Out-of-range literal pool entry for MVE const vector

2025-09-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- Target: arm Created attachment 62317 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=62317&acti

[Bug target/121775] arm: wrong code in vset_lane*

2025-09-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121775 Richard Earnshaw changed: What|Removed |Added Known to work||16.0 --- Comment #3 from Richard Ear

[Bug target/121775] arm: wrong code in vset_lane*

2025-09-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121775 Richard Earnshaw changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rearnsha at gcc dot gnu.org

[Bug target/121775] New: arm: wrong code in vset_lane*

2025-09-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- Target: arm #include #include "arm_neon.h" volatile uint8_t v40 = 255; volatile uint8x8_t result = { #if __BY

[Bug rtl-optimization/121773] New: Combine over-simplifies a subreg write

2025-09-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org CC: segher at gcc dot gnu.org Target Milestone: --- Target: arm With this testcase, compiled with -march=armv7-a+simd -mfpu=auto

[Bug target/121752] g++.dg/tree-ssa/vector-compare-1.C fails on arm

2025-09-02 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121752 --- Comment #3 from Richard Earnshaw --- The manual says: > @deftypefn {Target Hook} bool TARGET_SLOW_UNALIGNED_ACCESS ... > ... > The hook must return true whenever @code{STRICT_ALIGNMENT} is true. But STRICT_ALIGNMENT must be true because e

[Bug rtl-optimization/121619] [16 Regression] wrong code at -O{s,2,3} with "-fno-gcse -fno-tree-ter -fno-guess-branch-probability -fno-forward-propagate" on x86_64-linux-gnu (the generated code hangs)

2025-08-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121619 Richard Earnshaw changed: What|Removed |Added CC||sjames at gcc dot gnu.org --- Commen

[Bug target/121618] [16 regression] Failed bootstrap on armv7a-unknown-linux-gnueabihf since r16-3301-g724d88900b7aa8

2025-08-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121618 Richard Earnshaw changed: What|Removed |Added Resolution|FIXED |DUPLICATE --- Comment #8 from Richar

[Bug tree-optimization/121679] Takes 2 DSE to remove some dead calls in some cases

2025-08-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121679 --- Comment #5 from Richard Earnshaw --- (In reply to Richard Biener from comment #4) > DSE/DCE sometimes need "iteration", removing of trivially dead stmts in DSE > helped to some extent, but yes, some of this is expected. Is it worth iteratin

[Bug c++/121679] New: Much better code at -O1 than at O2

2025-08-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: c++ Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- #include struct A { int a; int b; const char *s; uint8_t array[64]; }; static A f1(int a, int b) { A obj { .a = a

[Bug target/121471] New: arm: mcrr2 and mrrc2 were obsolted in arm8-a

2025-08-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
: target Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- The Armv8-a Arm ARM removes all references to mcrr2 and mrrc2, so the intrinsics that expand to these instructions should be rejected when compiled with -march=armv8-a

[Bug target/121471] arm: mcrr2 and mrrc2 were obsolted in arm8-a

2025-08-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121471 Richard Earnshaw changed: What|Removed |Added Keywords||accepts-invalid Target Milestone|-

[Bug target/121464] MCRR{2} and MRRC{2} wrongfully reject opc1 >7

2025-08-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121464 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |13.5

[Bug target/121464] MCRR{2} and MRRC{2} wrongfully reject opc1 >7

2025-08-08 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121464 Richard Earnshaw changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug libgcc/117600] [15 regression] libgcc arm build doesn't respect --disable-werror

2025-08-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117600 --- Comment #6 from Richard Earnshaw --- libgcc is always built with the target compiler. --disable-werror is intended to allow compliers other than the one being built to work when they generate warnings based on different algorithms. It woul

[Bug rtl-optimization/121199] Miscompiled code at O2 for ARMv7 with ldrd instruction when sched2

2025-08-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121199 Richard Earnshaw changed: What|Removed |Added Resolution|--- |DUPLICATE Status|WAITING

[Bug bootstrap/88714] [9 regression] bootstrap comparison failure on armv7l since r265398

2025-08-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88714 Richard Earnshaw changed: What|Removed |Added CC||hanwei62 at huawei dot com --- Commen

[Bug rtl-optimization/121199] Miscompiled code at O2 for ARMv7 with ldrd instruction when sched2

2025-07-22 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121199 --- Comment #2 from Richard Earnshaw --- It looks a bit like this was fixed in gcc-9. Based on https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88714#c19 I suspect this is just a dup of that.

[Bug target/86772] [meta-bug] tracking port status for CVE-2017-5753

2025-06-23 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86772 Bug 86772 depends on bug 86802, which changed state. Bug 86802 Summary: riscv port needs updating for CVE-2017-5753 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86802 What|Removed |Added

[Bug target/86802] riscv port needs updating for CVE-2017-5753

2025-06-23 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86802 Richard Earnshaw changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|INVALID

[Bug middle-end/117811] [12 Regression] bad code for conditional right shift with autovec and neon since r12-897-gde56f95afaaa22

2025-06-17 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117811 Richard Earnshaw changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug middle-end/117811] [12 Regression] bad code for conditional right shift with autovec and neon since r12-897-gde56f95afaaa22

2025-06-13 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117811 Richard Earnshaw changed: What|Removed |Added Summary|[12/13/14 Regression] bad |[12 Regression] bad code

[Bug libstdc++/120567] [16 Regression] std::stacktrace tests now fail on arm-eabi

2025-06-06 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120567 --- Comment #1 from Richard Earnshaw --- Many fortran tests also use libbacktrace. So these days I just have site.exp: set board_info(arm-qemu,extra_ldflags) "--specs=sync-none.specs" In my bare-metal test configuration. That's enough f

[Bug c/116892] forward declaration of enum followed by packed on the enum type causes an ICE in verify_type

2025-06-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116892 --- Comment #10 from Richard Earnshaw --- (In reply to uecker from comment #9) > (In reply to Richard Earnshaw from comment #8) > > Forward declarations of enums in C requires c23, when you can use the size > > type specifier. For earlier versi

[Bug c/116892] forward declaration of enum followed by packed on the enum type causes an ICE in verify_type

2025-06-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116892 Richard Earnshaw changed: What|Removed |Added Keywords|ice-on-valid-code |ice-on-invalid-code --- Comment #8 f

[Bug target/120347] [15/16 regression] invalid arm32/thumb assembly output

2025-05-19 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120347 --- Comment #7 from Richard Earnshaw --- The address in offsettable_address is always validated as a 'byte' sized address (it's generic code). So it's not generally useful to use this on Arm for validating anything that's more restricted than l

[Bug target/120347] [15/16 regression] invalid arm32/thumb assembly output

2025-05-19 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120347 --- Comment #5 from Richard Earnshaw --- (In reply to Arnd Bergmann from comment #4) > I have reduced another build failure (in some configurations but many files) > and found that also to be caused by -flate-combine-instructions > > https://go

[Bug target/120351] [15 regression] Assemble failure on armv7-a with -mfpu=neon (ldrex r1, [s14], invalid use of NEON registers) since r15-1579-g792f97b44ffc5e

2025-05-19 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120351 Richard Earnshaw changed: What|Removed |Added Summary|[15/16 regression] Assemble |[15 regression] Assemble

[Bug target/120351] [15/16 regression] Assemble failure on armv7-a with -mfpu=neon (ldrex r1, [s14], invalid use of NEON registers) since r15-1579-g792f97b44ffc5e

2025-05-19 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120351 Richard Earnshaw changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rearnsha at gcc dot gnu.org

[Bug target/120347] [15/16 regression] invalid arm32/thumb assembly output

2025-05-19 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
||a/show_bug.cgi?id=20972 CC|richard.earnshaw at arm dot com|rearnsha at gcc dot gnu.org --- Comment #1 from Richard Earnshaw --- This is somewhat of a heisenbug. The instruction is unpredictable because the increment may take place

[Bug target/119644] __builtin_arm_set_fpscr ICE with -mgeneral-regs-only on Arm targets

2025-04-07 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119644 Richard Earnshaw changed: What|Removed |Added Keywords|ice-on-invalid-code |ice-on-valid-code --- Comment #4 fro

[Bug libstdc++/119550] cross compilation of libstdc++ fail for arm-none-eabi due to tzname tests

2025-03-31 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119550 --- Comment #4 from Richard Earnshaw --- At some point crosstool will run GCC's 'configure' script. What I need to see is the options it passes to that command. Sorry, I've never used crosstool, so I can't help with that. It is possible that

[Bug libstdc++/119550] cross compilation of libstdc++ fail for arm-none-eabi due to tzname tests

2025-03-31 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119550 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |WAITING Last reconfirmed|

[Bug rtl-optimization/115506] Possible but missed "cmp" instruction merging (x86 & ARM, optimization)

2025-03-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115506 --- Comment #4 from Richard Earnshaw --- (In reply to Uroš Bizjak from comment #2) > then RTL CSE2 pass would be able to merge: > > (insn 31 30 32 4 (set (reg:CCZ 17 flags) > (compare:CCZ (reg:QI 111 [ _30 ]) > (const_int -

[Bug testsuite/115827] [13/14/15 Regression] uninit-17.c no longer emits expected warning on arm soft-float

2025-03-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115827 --- Comment #7 from Richard Earnshaw --- (In reply to Richard Biener from comment #6) > IMO a testsuite issue then. Why would a missing warning from return f; /* { dg-warning "may be used" "unconditional" } */ be a testsuite issue?

[Bug middle-end/117811] [12/13/14/15 Regression] bad code for conditional right shift with autovec and neon since r12-897-gde56f95afaaa22

2025-03-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117811 Richard Earnshaw changed: What|Removed |Added Assignee|pinskia at gcc dot gnu.org |rearnsha at gcc dot gnu.org

[Bug middle-end/118939] [14/15 Regression] ada: executable segfaults on arm-linux-gnueabi when assigning an access to controlled type since r14-2653-g2971ff7b1d564a

2025-03-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118939 --- Comment #19 from Richard Earnshaw --- (In reply to Eric Botcazou from comment #18) > > So the real question is why has the size of the frame changed once it's too > > late to change the frame layout? > > The frame size has not changed, rath

[Bug middle-end/118939] [14/15 Regression] ada: executable segfaults on arm-linux-gnueabi when assigning an access to controlled type since r14-2653-g2971ff7b1d564a

2025-03-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118939 --- Comment #17 from Richard Earnshaw --- (In reply to Richard Earnshaw from comment #16) > That can't be right. If the frame size has changed, then the frame needs to > be laid out again and any earlier layout assumptions revisited. Here's a

[Bug middle-end/118939] [14/15 Regression] ada: executable segfaults on arm-linux-gnueabi when assigning an access to controlled type since r14-2653-g2971ff7b1d564a

2025-03-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118939 --- Comment #16 from Richard Earnshaw --- (In reply to Eric Botcazou from comment #13) > Possible kludge to work around the questionable mechanism: > > diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc > index 59b41e3d046..2d51874a05b

[Bug target/91614] [12/13/14 regression][arm] gcc.target/arm/unaligned-memcpy-2.c FAIL since r274986

2025-03-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91614 Richard Earnshaw changed: What|Removed |Added Summary|[12/13/14/15|[12/13/14 regression][arm]

[Bug middle-end/117811] [12/13/14/15 Regression] bad code for conditional right shift with autovec and neon since r12-897-gde56f95afaaa22

2025-03-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117811 --- Comment #21 from Richard Earnshaw --- Patch posted: https://gcc.gnu.org/pipermail/gcc-patches/2025-March/678597.html

[Bug rtl-optimization/101995] [12/13/14/15 Regression] regression built-in memset missed-optimization arm -Os since r9-3594

2025-03-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101995 --- Comment #16 from Richard Earnshaw --- Still present. Perhaps more significantly (and possibly related) class x { public: x (); int func (); private: int a; }; int g () { x b; return b.func(); } generates: g(): push

[Bug target/119372] Aarch64: Compiling with -march=armv8-a+pauth -mbranch-protection=standard produces autiasp and retaa in the function epilogue

2025-03-19 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119372 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2025-03-19 Version|14.2.1

[Bug target/117931] gcc.target/arm/lp1243022.c fails since gcc-6-4265-g477ee35f511

2025-03-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117931 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug tree-optimization/119196] New: Missed folding of vector comparisons

2025-03-10 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- c-c++-common/vector-compare-3.c contains the code: void g (T *x, T const *y, T *z, T *t) { *z = *x < *y | *x == *y; *t =

[Bug tree-optimization/119196] Missed folding of vector comparisons

2025-03-10 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119196 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed|

[Bug target/118942] [14/15 Only] vld1q_s{8,16}_x{3,4} use incorrect pointer type since they were added with r14-7202-gc8ec3e1327cb1e

2025-03-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118942 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug libgcc/117600] [15 regression] libgcc arm build doesn't respect --disable-werror

2025-03-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117600 --- Comment #2 from Richard Earnshaw --- libgcc should only be built with the current compiler, so I don't think it's unreasonable to expect -Werror to be always enabled.

[Bug rtl-optimization/119107] New: inconsistent elimination of redundant *_extend operations

2025-03-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- GCC often relies on combine to identify and eliminate redundant (zero|sign)_extend

[Bug debug/118221] gdb and objdump referencing functions that do not exist in binary

2025-02-18 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118221 --- Comment #10 from Richard Earnshaw --- Fixing this properly would require rewriting all of GCC's dwarf output code so that each function in a separate section had its own debug data (and perhaps using section groups to describe the relationsh

[Bug rtl-optimization/117712] [15 regression] ICE when building x265: internal compiler error: in expand_fix, at optabs.cc:5936 since r15-2890

2025-02-18 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117712 Richard Earnshaw changed: What|Removed |Added See Also||https://gcc.gnu.org/bugzill

[Bug target/117525] [15 Regression] canvas.cc:1675:1: internal compiler error: in expand_fix, at optabs.cc:5952 since r15-2890

2025-02-18 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117525 --- Comment #19 from Richard Earnshaw --- I'm not convinced this is correct. See the discussion on the patch here: https://gcc.gnu.org/pipermail/gcc-patches/2003-March/098380.html and the related PR (https://gcc.gnu.org/bugzilla/show_bug.cgi?id

[Bug target/118089] [12/13/14/15 regression] arm thumb2 return sequence is suboptimal, especially at -O2

2025-02-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118089 --- Comment #4 from Richard Earnshaw --- Partially fixed. Still to do is implementing stack deallocation by using a POP of dead callee saved regs (for -Os).

[Bug rtl-optimization/116028] [15 Regression] gcc.dg/pr10474.c test failure since r15-1619-g3b9b8d6cfdf593

2025-02-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116028 --- Comment #13 from Richard Earnshaw --- (In reply to Surya Kumari Jangala from comment #3) > The parameter register is > saved in a volatile register which is saved on stack in the entry bb. > Instead, if the volatile register is saved just be

[Bug middle-end/118732] New: [15 regression] caller-saves optimization can inhibit shrink wrapping

2025-02-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
-optimization Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org CC: jskumari at gcc dot gnu.org, vmakarov at redhat dot com Target Milestone

[Bug target/118642] -specs=sync-none.specs doesn't work with LTO.

2025-01-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118642 Richard Earnshaw changed: What|Removed |Added Keywords||rejects-valid --- Comment #3 from Ri

[Bug target/118501] [14 regression] aarch64: ICE in simplify_context::simplify_subreg

2025-01-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118501 --- Comment #14 from Richard Earnshaw --- (In reply to Matthias Klose from comment #13) > the backport requires some more work: > > ../../src/gcc/config/aarch64/aarch64.md:7255:13: error: > 'force_lowpart_subreg' was not declared in this scope;

[Bug target/118642] -specs=sync-none.specs doesn't work with LTO.

2025-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
|1 Assignee|unassigned at gcc dot gnu.org |rearnsha at gcc dot gnu.org Status|UNCONFIRMED |NEW --- Comment #1 from Richard Earnshaw --- mine

[Bug target/118642] New: -specs=sync-none.specs doesn't work with LTO.

2025-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
onent: target Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- Target: arm-none-eabi The arm-none-eabi port provides some alternative implementations of __sync_synchronize for different implementations of the archite

[Bug target/116448] gcc.target/arm/vfp-1.c uses the wrong instructions on Cortex-M55

2025-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116448 --- Comment #5 from Richard Earnshaw --- If -fno-math-errno doesn't work, then we could consider moving those specific tests to a different file, with different optimization flags.

[Bug target/116448] gcc.target/arm/vfp-1.c uses the wrong instructions on Cortex-M55

2025-01-24 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116448 --- Comment #4 from Richard Earnshaw --- (In reply to Torbjorn SVENSSON from comment #3) > Compiling the test case with -Os resolves the failed checks, but it also > starts failing on the sqrt() and sqrtf() calls. These are no longer expanded >

[Bug target/116448] gcc.target/arm/vfp-1.c uses the wrong instructions on Cortex-M55

2025-01-22 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116448 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/118564] DSP instruction support missing for ARM Cortex M4

2025-01-21 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118564 Richard Earnshaw changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRM

[Bug target/118460] [14/15 Regression] ICE on armv8.1-m.main with -mfloat-abi=hard

2025-01-17 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118460 --- Comment #6 from Richard Earnshaw --- Yes, that would work as a work-around. It's a bit of a hack though. The expectation is that we would use vsel for pretty much everything when it is available (particularly for fast-math), but we fail to

[Bug target/118460] [14/15 Regression] ICE on armv8.1-m.main with -mfloat-abi=hard

2025-01-17 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118460 --- Comment #4 from Richard Earnshaw --- arm_vsel_comparison_operator is rejecting the comparison (LT) because it is not one that the vsel instruction can handle. We should be reversing the order of operands to the compare instruction and then

[Bug lto/118136] Linking start code built with -flto with application where main signature does not match causes warning

2024-12-20 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118136 Richard Earnshaw changed: What|Removed |Added Resolution|INVALID |--- Last reconfirmed|

[Bug target/118089] [12/13/14/15 regression] arm thumb2 return sequence is suboptimal, especially at -O2

2024-12-17 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118089 --- Comment #1 from Richard Earnshaw --- > I suspect this is a consequence of moving to an rtl-based prologue. Or more accurately: epilogue. :)

[Bug target/118089] New: [12/13/14 regression] arm thumb2 return sequence is suboptimal, especially at -O2

2024-12-17 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Keywords: missed-optimization Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- Target: arm This is a regression that originally appeared in

[Bug target/118008] [14/15 regression] ICE when bootstrapping with Go on arm (gen_movdi, at config/arm/arm.md:6296)

2024-12-16 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118008 --- Comment #11 from Richard Earnshaw --- For the bare metal cross you probably need to configure with '--with-arch=armv7-a+fp --with-float-abi=hard' If that still doesn't trigger it, try adding '--with-mode=thumb'

[Bug target/116447] g++.dg/cpp23/ext-floating13.C fails on Cortex-M55 due to undefined reference

2024-12-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
, ||rearnsha at gcc dot gnu.org --- Comment #6 from Richard Earnshaw --- So I think this issue might be related to something Christophe and I were discussing the other day. The arm port defaults to not creating the type _fp16 by default, but on some CPUs this

[Bug target/117941] Partial backtrace on C++ exception on ARM

2024-12-09 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117941 --- Comment #5 from Richard Earnshaw --- > Is it then possible to have dwarf data on ARM in addition to the EABI defined > unwind section? I don't know, honesty, because I've not tried it. I'd be surprised if it worked though, at least, not wi

[Bug target/117941] Partial backtrace on C++ exception on ARM

2024-12-09 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117941 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116625] [15 regression] regressions on arm-eabi since r15-1619-g3b9b8d6cfdf593

2024-12-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116625 Richard Earnshaw changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/116447] g++.dg/cpp23/ext-floating13.C fails on Cortex-M55 due to undefined reference

2024-12-02 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116447 --- Comment #1 from Richard Earnshaw --- How was the compiler configured and what's the full command line used when building the test?

[Bug target/117766] Confusion over whether ARM32 -march=armv8-a implies floating point support

2024-11-25 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117766 --- Comment #14 from Richard Earnshaw --- (In reply to Tom Lane from comment #13) > After further experimentation, it seems to me that: > > * There was a behavioral change between gcc 9.3.1 and the later releases I > tested. Specifically, in 9

[Bug target/114801] [14/15 Regression] arm: ICE in find_cached_value, at rtx-vector-builder.cc:100 with MVE intrinsics

2024-11-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114801 Richard Earnshaw changed: What|Removed |Added Keywords|ice-on-valid-code |ice-on-invalid-code --- Comment #40

[Bug testsuite/117419] test failures for enum-alias-{1,2,3} on arm-eabi

2024-11-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117419 --- Comment #4 from Richard Earnshaw --- enum size is ABI (affects data layout). So you can't use -f[no-]short-enums for executable tests. The best way to deal with this is to ensure that the size of the enum defaults to int (eg by adding a du

[Bug target/56513] Wrong code generation with -O3 on ARM

2024-11-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56513 --- Comment #8 from Richard Earnshaw --- For something this old, we should probably just close it as fixed as of Richi's patch.

[Bug target/114801] [14/15 Regression] arm: ICE in find_cached_value, at rtx-vector-builder.cc:100 with MVE intrinsics

2024-10-31 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114801 --- Comment #36 from Richard Earnshaw --- I've been looking at this. I think the real problem is that trunc_int_for mode is doing something incompatible with what the later code expects. We have /* Canonicalize BImode to 0 and STORE_FLAG_VA

[Bug target/116856] Generated Code with unaligned uint32_t potentially hardfaults on ARM (due to LDRD)

2024-09-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116856 --- Comment #8 from Richard Earnshaw --- BTW, rewriting the code as: #include typedef uint32_t __attribute__((aligned(1))) u32_u; void f() { static uint8_t array[64]; for (uint8_t i = 0; i < sizeof(array); i++) {

[Bug target/116856] Generated Code with unaligned uint32_t potentially hardfaults on ARM (due to LDRD)

2024-09-27 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116856 Richard Earnshaw changed: What|Removed |Added Resolution|--- |INVALID Status|WAITING

[Bug target/116856] Generated Code with unaligned uint32_t potentially hardfaults on ARM (due to LDRD)

2024-09-26 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116856 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |WAITING Ever confirmed|0

[Bug target/113780] [ARM] Incorrect indirect tailcall generated for PAC-enabled function.

2024-09-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113780 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |13.4

[Bug target/116597] [arm] indirect tailcalls with incomplete prototypes generate wrong code when using PACM

2024-09-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116597 Richard Earnshaw changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |rearnsha at gcc dot gnu.org

[Bug target/116597] New: [arm] indirect tailcalls with incomplete prototypes generate wrong code when using PACM

2024-09-04 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
Keywords: wrong-code Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rearnsha at gcc dot gnu.org Target Milestone: --- void (*f)(); // Or void (*f)(int, ...}; void g () { return f (1, 2, 3, 4

[Bug target/116517] ICE in arm_print_operand_address

2024-08-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116517 --- Comment #3 from Richard Earnshaw --- The invalid insn is created during late-combine.

[Bug target/116517] ICE in arm_print_operand_address

2024-08-28 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116517 Richard Earnshaw changed: What|Removed |Added Last reconfirmed||2024-08-28 Status|UNCONF

[Bug target/116329] no sibcalling for thumb1 (cortex-m0)

2024-08-22 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116329 Richard Earnshaw changed: What|Removed |Added Resolution|--- |WONTFIX Status|UNCONFIRM

[Bug rtl-optimization/86901] [AArch64] Suboptimal register allocation for int/float reinterpret

2024-07-23 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86901 --- Comment #4 from Richard Earnshaw --- But why not: f2: fmovw1, s0 ubfxw1, w1, 20, 11 cmp w1, 1015 bhi .L7 fmuls0, s0, s0 str s0, [x0] ret .L7: b g

[Bug target/96373] [11 Regression] SVE miscompilation on vectorized division loop, leading to FP exception

2024-07-12 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96373 --- Comment #25 from Richard Earnshaw --- (In reply to Kewen Lin from comment #24) > OK, thanks for the comments, I'll mark PR108977 as won't fix then. It would be more normal to mark it as fixed, but set the fix version to the earliest release

[Bug target/115611] mve: vsetq_lane for 64-bits has wrong codegen when setting lane 1

2024-07-11 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115611 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |11.5

[Bug target/105090] BFI instructions are not generated on arm-none-eabi-g++

2024-07-10 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090 --- Comment #9 from Richard Earnshaw --- It looks like the compiler now merges b into a rather than a into b. The result is the same, though and we don't need an lsr this way. Technically it ought to be better. But we do end up in a dance wit

[Bug target/103100] [11 Regression] unaligned access generated with memset or {} and -O2 -mstrict-align

2024-07-05 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103100 Richard Earnshaw changed: What|Removed |Added Target Milestone|11.5|12.5

[Bug c/115770] Undefined arm instruction (udf #255) is generated when optimizer is on O2

2024-07-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115770 --- Comment #2 from Richard Earnshaw --- Correction: the option to add is -fno-delete-null-pointer-checks Sorry for the confusion.

[Bug c/115770] Undefined arm instruction (udf #255) is generated when optimizer is on O2

2024-07-03 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115770 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/115732] Arm32 architecture definitions for v8+ appear to have wrong FPU/SIMD defaults

2024-07-02 Thread rearnsha at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115732 Richard Earnshaw changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

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