problem :
except for TARGET_CPU_CPP_BUILTINS i dont know how
to rewrite the existing macros for 3.4.6
Can anybody help me in this regard?
Thanks in advance
Regards,
Shafi.
__
Do You Yahoo!?
Tired of spam? Yahoo! Mail has the best spam protection around
http://mail.yahoo.com
of GNU supported
processors i found that all of the macros previously
defined in target.h in now defined in target.c in gcc
3.4.6
Does that mean that i need to re write my target.h and
target.c file for the migration of the compiler?
regards,
shafi
#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
#undef TARGET_STRUCT_VALUE_RTX
#define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
Can anyone suggest an option?
Thanks in advance.
Regards,
Shafi.
__
Do You Yahoo!?
Tired of spam? Yahoo
ir)/config/fp-bit.c
cat $(srcdir)/config/fp-bit.c > dp-bit.c
Can someone help me?
Regards,
Shafi.
this.
The format for my hardware is s7.40
Should i go for adding a new data type in the front end?
I am new to GCC internals.So any help that you can offer is of great value for
me.
Regards,
Shafi.
ibgcc
cpu3/libgcc
libgcc
That includes i variant for each cpu and a default version. Is there
any way to restrict GCC from building the default version?
Regards,
Shafi
ping !!!. Any help on http://gcc.gnu.org/ml/gcc/2011-09/msg00150.html
shafi
On 14 September 2011 15:07, Mohamed Shafi wrote:
> Hi,
>
> I am working on a 32bit private target which has the following restriction
>
> 1. store/load can happen only through a general purpose registe
rg1 are different, one is Pmode
and other is word_mode.
This is present in m32c target which also has different Pmode and word_mode.
Is this a know failure? I cannot find a bug entry for this issue.
Should i report this?
Regards,
Shafi
On 29 May 2012 17:31, Richard Guenther wrote:
> On Tue, May 29, 2012 at 1:57 PM, Mohamed Shafi wrote:
>> Hi,
>>
>> I am porting a private target in GCC 4.6.3 version. For my target
>> pointer size is 24bits and word size is 32bits. Moreover a byte is
>> 32bit
>
macro
ASM_OUTPUT_BSS, again by looking for the attribute value. For .sbss
section there is no need to define EXTRA_SECTIONS and
EXTRA_SECTION_FUNCTIONS
Can anyone please confirm this?
Regards,
Shafi
not sure how to implement this in the back-end. Can anyone give
me any ideas?
Regards,
Shafi
On Tue, Apr 1, 2008 at 2:10 AM, Jim Wilson <[EMAIL PROTECTED]> wrote:
> Mohamed Shafi wrote:
> > For the source or the destination register Rd/Ra, the restriction is
> > that it should be one more than the base register . So the following
> > instructions are valid:
&
that if delay slot 1 is filled
with pattern A then don't fill the delay slot 2?
Regards,
Shafi.
On Thu, Apr 3, 2008 at 6:49 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
>
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
> > It is not necessary that a pattern with a single constrain will have
> > only one instruction in the template.
> >
On Thu, Apr 3, 2008 at 7:35 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
>
> > Say the target has two delay slots for call instructions.
> > So we can have something like this
> > (define_attr
On Thu, Apr 3, 2008 at 8:28 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
>
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
> > On Thu, Apr 3, 2008 at 7:35 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> >> "Mohamed Shafi" <
. But since
the last scheduled instruction is a jump instruction scheduling stops
and comes out. Due to this the assertion fails. Looking at the code i
am not able to find out where
the problem might be. Can anyone help me?
Thanks for your time.
Regards,
Shafi.
x27; after scheduling a region?
Regards,
Shafi
Hello all,
I have noticed that when strict_low_part is used in a patten we need
to use '+' as the constraint modifier if any constraints are used in
the patterns.
Why is this so?
Regards,
Shafi
On Fri, Apr 11, 2008 at 12:41 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
> > I have noticed that when strict_low_part is used in a patten we need
> > to use '+' as the constraint modifie
On Tue, Apr 8, 2008 at 8:32 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
>
> > Like you said i tried to split the move_immediate pattern after
> > reload. This is how i did this :
> >
&g
ad it
been documented.
Regards,
Shafi
On Sun, Apr 13, 2008 at 6:23 AM, Hans-Peter Nilsson
<[EMAIL PROTECTED]> wrote:
> > Date: Fri, 11 Apr 2008 15:32:02 +0200
> > From: Bernd Schmidt <[EMAIL PROTECTED]>
>
> > Mohamed Shafi wrote:
> > > In cris i saw th
the indirect_jump pattern has to utilized. Now my
question is how will i be able to specify the limit of the offset so
the gcc generates indirect_jump pattern instead of the jump pattern? I
hope i am clear.
Thank you for your time.
Regards,
Shafi
On Sat, Apr 12, 2008 at 12:13 AM, Jim Wilson <[EMAIL PROTECTED]> wrote:
> Mohamed Shafi wrote:
>
> > This looks like reordering is proper. When schedule-insn2 is run for
> > the above region/block the no:of instructions in the region
> > (rgn_n_insns) is 3.
> >
back-end using pragmas?
Regards,
Shafi.
On Mon, Apr 14, 2008 at 11:44 PM, Jim Wilson <[EMAIL PROTECTED]> wrote:
>
> Mohamed Shafi wrote:
>
> > For a function call will i be able to implement long call/short call
> > for the same function at different locations?
> > Say fun1 calls bar and fun2 c
espective of whether '#' is present in the output template or
not all the alternatives are being spilt.
Should i be having a define_split specific for an alternative or only
the '#' alternative will be split?
Thanks for you time.
Regards,
Shafi
On Tue, Apr 15, 2008 at 11:27 AM, Mohamed Shafi <[EMAIL PROTECTED]> wrote:
>
> On Mon, Apr 14, 2008 at 11:44 PM, Jim Wilson <[EMAIL PROTECTED]> wrote:
> >
> > Mohamed Shafi wrote:
> >
> > > For a function call will i be able to implement long ca
On Mon, Apr 14, 2008 at 11:07 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
>
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
> > I have read in the internals that indirect_jump and jump pattern are
> > necessary in any back-end for the compiler to b
On Thu, Apr 17, 2008 at 9:31 AM, Jim Wilson <[EMAIL PROTECTED]> wrote:
>
> On Tue, 2008-04-15 at 11:27 +0530, Mohamed Shafi wrote:
> > On Mon, Apr 14, 2008 at 11:44 PM, Jim Wilson <[EMAIL PROTECTED]> wrote:
>
> > > A simple grep command shows that both
not sure how to
write the patterns for the above instructions.
Can anybody help me with this?
Thank you for your time.
Regards,
Shafi.
On Thu, Apr 24, 2008 at 12:01 PM, Mohamed Shafi <[EMAIL PROTECTED]> wrote:
> Hello all,
>
> The target that i am porting in gcc 4.1.2, has the following instructions
>
> setb Rx, bitno
> clrb Rx, bitno
>
> where bit bitno of Rx will either be set or reset.
>
&g
s not
possible to do something like
short k;
__OUT(port no) = k;
So hoe can i do that.
Is inline assembly the only solution?
Thanks for your time.
Regards,
Shafi
_internal} (nil)
(nil)
(nil))
>>>>>>
What could be the problem?
Thanks for your time.
Regards,
Shafi
ow can i handle instances like this? Should i be doing insertion
of nops in reorg pass?
Thanks for your time.
Regards,
Shafi
On Sat, May 3, 2008 at 3:13 PM, Richard Sandiford
<[EMAIL PROTECTED]> wrote:
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
> > The gcc port that i am currently working on has both long calls and
> > short calls. If no 'shortcall' attribute is provi
n in delay slots which can have only 2. So my
question was how do i overcome this?
Should i do delay slot scheduling myself in reorg pass or is there
some other way?
Thanks for your time,
Regards,
Shafi
On Mon, May 5, 2008 at 1:12 PM, Boris Boesler <[EMAIL PROTECTED]> wrote:
> Hi!
>
> Am 05.05.2008 um 09:06 schrieb Mohamed Shafi:
>
>
>
> >
> > >
> > > > But how can i handle instances like this? Should i be doing insertion
> > > > of
Any help is appreciated.
Thanks for your time.
Regards,
Shafi
for representation?
What is the size of this data type? Will i be able to control the size
of this like we can for other data types?
Regards,
Shafi
ode from sizetype.
>
> No. We pick the mode that's *at least* 3 bits wider than sizetype, so
> it's usually the next larger integer mode.
>
Does this mean that if the sizetype is 32bit then bitsizetype is 64bit?
Regards,
Shafi
.
Regards,
Shafi.
On Fri, May 9, 2008 at 12:03 AM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
> > For the 16-bit target that i porting now to gcc 4.1.2 doesn't have any
> > branch instructions. It only has jump instr
is the only conclusion that i can come to. But
i am not sure if this is way live information is handled.
Can some one give any thoughts on this?
Regards,
Shafi
On Tue, Apr 1, 2008 at 2:10 AM, Jim Wilson <[EMAIL PROTECTED]> wrote:
> Mohamed Shafi wrote:
>>
>> For the source or the destination register Rd/Ra, the restriction is
>> that it should be one more than the base register . So the following
>> instructions are v
getting emitted for a library call. This
definition actually defines one of the parameters of the library call.
This call also returns 2 register value, i.e in R0 and R1. So as far
as live analysis is concerned there is a use for R1 but no definition.
And hence it stays live through out the program. I now just need to
find out why the instruction is not getting emitted.
But thanks for taking your time to read this.
Regards,
Shafi
rands if they
contain registers inside an unpsec expression? I still haven't
encountered this.
What about live analysis. How are the registers inside an unspec
expression handled there?
Regards,
Shafi
profiling information.
>
> 3. Suppose assume that executable is built without ¨Cpg option, but want
> to create gmon.out at run-time. Is there any way or guidelines to
> implement?
A call to the profiling function (mcount) should be there to generate
profiling information. Without that
Regards,
Shafi
On Tue, May 20, 2008 at 1:54 PM, <[EMAIL PROTECTED]> wrote:
> Dear Shafi
>
> Thanks you very much for the clear details. Definitely your inputs are
> helpful.
>
> 1) I am sure that in gcc-4.0 I found there is file gmon.c in the path
> gcc-4.0.0/gcc/gmon.c. Anyhow let
On Wed, May 21, 2008 at 1:42 AM, Jeff Law <[EMAIL PROTECTED]> wrote:
> Ian Lance Taylor wrote:
>>
>> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>>
>>> For the 16 bit target that i am currently porting can have only
>>> positive offset
nd"
"R00,R02,R04,R06,R08,R12,R14,m"))]
Is this the proper way to do this?
Thank you for taking the time to read this.
Regards,
Shafi
On Sat, May 24, 2008 at 12:26 AM, Omar Torres <[EMAIL PROTECTED]> wrote:
> Mohamed Shafi wrote:
>> Hello Omar,
>>
>> I saw your mail to gcc mailing list regarding splitting of HImode
>> patterns into QImode patterns. I am also involved in porting. My
>> pro
for movqi will generate SImode register, reg28 and does
the operations. But this is not reflected in the subsequent
instructions (insn 14). And hence insn 13 is getting deleted as its
operands are never used.
What i am i doing wrong? Am i implementing the addressing mode properly?
Any help is appreciated.
Regards,
Shafi
re nop
gets inserted when it's not really required.
How will it be possible to solve this issue?
Regards,
Shafi
will have
add %0, %1\naddc %N0, %N1
sub %0, %1\nsubc %N0, %N1
Will it be possible for me to write separate patterns for the
instructions add and addc?
Regards,
Shafi
ructions add and addc?
>>
>
> You can look into config/i386.md, how i.e. adddi3 is expanded and split in
> case of !TARGET_64BIT.
But is it scheduling safe?
I mean you can't have addc executed before add. If i am right there
will be no dependency between the two instructions. So there can be a
case where addc gets scheduled before add. Am i right on both counts?
Regards,
Shafi
patterns instead of the target macros.
So is the rename pass allowed to rename a callee saved register? Where
might this going wrong?
Thanks for you help.
Regards,
Shafi
2008/6/19 Ian Lance Taylor <[EMAIL PROTECTED]>:
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
>> Before register renaming pass, callee registers was being used in the
>> body of the code. Hence function prologue saved the register and
>> epilogue res
2008/6/19 Ian Lance Taylor <[EMAIL PROTECTED]>:
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
>>> Which version of gcc? I was under the impression that this
>>> longstanding buglet was cleaned up by the dataflow work.
>>>
>>
&
2008/6/20 Andrew Pinski <[EMAIL PROTECTED]>:
> On Thu, Jun 19, 2008 at 11:56 PM, Mohamed Shafi <[EMAIL PROTECTED]> wrote:
>> Can you tell me what was done in gcc 4.3 so that i can back port
>> the changes to gcc 4.1.2
>
> It was a rewrite of life information of
set any status flags.
Will it be possible to implement this in the Gcc backend ?
Does any other targets have similar instructions?
Regards,
Shafi
comparison of sign-extended 8bit values are
proper. So i can use the normal comparison for char and the modified
one for 16bit values. So my question is in the back-end will i be able
to identify between comparisons of signed-extended 8bit and 16bit
operands?
Regards,
Shafi
Hello all,
Is there a way to know whether an operand is signed or unsigned from its rtx?
Regards,
Shafi
s that for some processing during comparison i need
to know whether is the char operand is signed or unsigned. So i guess
i can get this looking at what type of comparison is. But if the
comparison code is EQ or NE will i be able to get the information?
Shafi
other
function?
Or is this a gcc bug?
Hope my question is clear.
Regards,
Shafi
that GCC has used only the argument
registers, stack pointer and callee saved registers. So out of the 16
available registers ony 5+1+4 registers were used, even though there
was 6 caller save registers were available
>
> HTH.
>
>
> cheers
> Ramana
>
> On Tue, Jul 15, 2008
nt registers, caller save registers and finally
the callee save registers.
>
>
> cheers
> Ramana
>>
>>>
>>> HTH.
>>>
>>>
>>> cheers
>>> Ramana
>>>
>>> On Tue, Jul 15, 2008 at 7:50 AM, Mohamed Shafi <[EMAIL PROT
g function shouldn't the
mode of the argument be SImode instead of DImode since long long is
only 32bit for the target?
Regards,
Shafi
2008/7/16 Ian Lance Taylor <[EMAIL PROTECTED]>:
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
>> I am involved in the porting of gcc 4.1.2 for 16 bit target. For this
>> target size of long long is 32bits. For the following code
>>
>> #defi
of the
instruction.
Could any one tell me the functions that i can use to find out whether
an register is being used and/or defined in a particular instruction?
Regards,
Shafi
initialized and prologue will
set stack space accordingly. Based on the live information
'propagate_one_insn()' is trying to delete the insn from the
prologue. My question is is gcc suppose to delete insn 9, even before
prologue generation ?
If its not the case where am i going wrong?
Regards,
Shafi
246 224 26 18 "" [0 uses])
;; End of basic block 26, registers live:
(nil)
"
Note that if i compile a code which has SImode EQ comparisons the
basic blocks and code is generated properly. Right now i am stuck in
debugging.
Could anybody please provide me with any pointers?
Regards,
Shafi
- Original Message
> From: Omar Torres <[EMAIL PROTECTED]>
> To: [EMAIL PROTECTED]
> Cc: gcc@gcc.gnu.org
> Sent: Saturday, August 30, 2008 12:11:36 AM
> Subject: Re: insn does not satisfy its constraints
>
> shafi wrote:
> >Operand 0 is a regi
;
[(set_attr "type" "arith")
(set_attr "length" "2")]
)
The instruction macf will store the result in last operand i.e %3+=%2 * %1
Regards,
Shafi
On 5/4/07, Andrew Haley <[EMAIL PROTECTED]> wrote:
Mohamed Shafi writes:
> I am trying to implement a builtin function __macf for a private target.
> I have added the required target hooks for this.
> Say for the following code
>
> int main()
> {
> int oper
in "profil" system call.
1. What should i do to implement this?
2. How do other targets implement "profil" system call?
3. If profil system call is not present, how to collect the histogram records?
Thanks for you time.
Regards,
Shafi
thus created is recognized by gprof? Or am i missing something?
Thanks for your time.
Regards,
Shafi.
has to be used when compiling the program?
Thanks for your time.
Regards,
Shafi
garbage,
in wrong order in the block. From this block, stored in the wrong
order, __builtin_apply passes the arguments to foo, and
__builtin_apply function is doing the job properly.
Is there any way to control the behavior of __builtin_apply_args?
Regards,
Shafi
On 01 Jun 2007 07:22:39 -0700, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
"Mohamed Shafi" <[EMAIL PROTECTED]> writes:
> I am working with a private target(GCC v4.1.1).
> For my target the function arguments are passed through registers.
> For this purpose 4 re
target that does similar to this?
Thanks for your time,
Regards,
Shafi.
On 13 Jun 2007 10:47:33 -0700, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
"Mohamed Shafi" <[EMAIL PROTECTED]> writes:
> I am working for a private GCC target.
> The target has 4 registers, each 32 bits reserved for arguments.
> When passing arguments depend
Hello all,
I want to know whether its possible to run the gcc testsuite without
actually building the complier.
I have the dejagnu framework, compiler executables and i have the gcc
test suite. So is it possible to run the testsuite without building
the complier?
Regards,
Shafi
On 10/5/07, Brian Dessent <[EMAIL PROTECTED]> wrote:
> Mohamed Shafi wrote:
>
> > I want to know whether its possible to run the gcc testsuite without
> > actually building the complier.
> >
> > I have the dejagnu framework, compiler executables and i have the g
On 10/8/07, Ben Elliston <[EMAIL PROTECTED]> wrote:
> On Fri, 2007-10-05 at 16:09 +0530, Mohamed Shafi wrote:
>
> > > Use the contrib/test_installed script.
>
> > I used the script and even tried to execute the runtest command
> > directly but the framework is
:
DW_AT_digit_count :
Any help would be appreciated.
Regards,
Shafi
101 - 187 of 187 matches
Mail list logo
