On Thu, Apr 3, 2008 at 8:28 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
>
> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
>
> > On Thu, Apr 3, 2008 at 7:35 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> >> "Mohamed Shafi" <[EMAIL PROTECTED]> writes:
> >>
> >>
> >> > Say the target has two delay slots for call instructions.
> >> > So we can have something like this
> >> > (define_attr "slottable" "no,yes,has_slot" (const_string "yes"))
> >> >
> >> > (define_delay (eq_attr "slottable" "has_slot")
> >> > [(eq_attr "slottable" "yes") (nil) (nil)
> >> > (eq_attr "slottable" "yes") (nil) (nil)])
> >> >
> >> > So in define_insn for call i can have
> >> > (set_attr "slottable" "has_slot")
> >> >
> >> >
> >> > Now imagine that i have 3 patterns : Pattern A with two instructions
> >> > in its template, Pattern B and Pattern C with only one instruction in
> >> > its template.
> >> > When it comes to filling the call instruction delay slot if slot 1 is
> >> > filled with Pattern A then there is no need to fill slot 2. But if its
> >> > filled with Pattern C or Pattern B, then slot 2 should be filled with
> >> > Pattern B or Pattern C, but not Pattern A.
> >> > Will i be able to do this in the back-end?
> >>
> >> Ah, OK. It's easy enough to say that you can't put pattern A in slot
> >> 2. But there is no way to say that if pattern A is in slot 1, then
> >> slot 2 is not available.
> >>
> > Ok i guess you are saying that this is not possible.
> > But then this should be something that all the targets should deal
> > with. How are they doing it?
>
> It's not a standard problem. On most machines a single insn does not
> take up two slots.
>
> To put it another way, you say that pattern A has two instructions in
> its template, and I assumed that that was a requirement for some
> reason. If the instructions can be executed independently, then the
> normal approach would be to use a define_split which runs after reload
> to produce two insns for scheduling and delay slot filling.
>
In order to load immediate values, the target that i am working on
uses two instructions - liu and lil.
'lil' will load the immediate value into the lower byte of the
specified register. The upper byte is set to zero.
'liu' will load the immediate value into the upper byte of the
specified register. The lower byte of the register is unaffected.
Like you said i tried to split the move_immediate pattern after
reload. This is how i did this :
(define_split
[(set (match_operand:HI 0 "register_operand" "")
(match_operand:HI 1 "immediate_operand" ""))]
"reload_completed"
[(set (match_dup 0) (unspec:HI [(match_dup 2)] UNSPEC_LIL))
(set (match_dup 0) (unspec:HI [(match_dup 3)] UNSPEC_LIU))]
"
{
operands[2] = GEN_INT (INTVAL (operands[1]) & 0x00ff);
operands[3] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0x00ff);
}"
)
But after the instruction is split 'lil_pattern' get deleted for every
split. This is because both the newly generated patterns are
same, even though the value of the immediate constant is different for
the patterns. This happens in the 'CSA' pass.
How can i make this work?
For delay slots will i be able to control filling of delay slots based
on the instruction cycles required for the instructions ?
Regards,
Shafi
