Hello Everyone,
I have the following source code
static int i;
static char a;
char foo_gen(int);
void foo_assert(char);
void foo ()
{
int *x = &i;
a = foo_gen(0);
a |= 1; /* 1-*/
if (*x) goto end:
a | =1; /* -2--*/
foo_assert(a);
end:
return;
}
Now I expect th
On 1/15/07, Richard Guenther <[EMAIL PROTECTED]> wrote:
On 1/15/07, pranav bhandarkar <[EMAIL PROTECTED]> wrote:
> Hello Everyone,
> I have the following source code
>
> static int i;
> static char a;
>
> char foo_gen(int);
> void foo_assert(char);
> v
I am wondering where to define the prototypes for functions in
.c Shall the prototypes be defined in -protos.h or in
.h or in .c. As far as I understand the prototypes
should be defined in -protos.h, right? But if I do so several
errors/warnings arise because of undeclared prototypes.
Another que
On 1/16/07, Markus Franke <[EMAIL PROTECTED]> wrote:
Thank you for your response. I understood everything you said but I am
still confused about the file -protos.h. Which prototypes have
to be defined there?
Thanks in advance,
Markus Franke
IMO and from what I have gathered from the documentat
Also this is removed for the case of integers by the CSE pass
IIRC . The problem arises only for the type being a char or a short.
Yes, That is true. With gcc 4.1 one of the 'or's gets eliminated for
'int'. I am putting below two sets of logs. The first just before
cse_main and the second just a
On 1/17/07, Mircea Namolaru <[EMAIL PROTECTED]> wrote:
> Thanks. Another question I have is that, in this case, will the
following
>
> http://gcc.gnu.org/wiki/Sign_Extension_Removal
>
> help in removal of the sign / zero extension ?
First, it seems to me that in your case:
(1) a = a | 1 /* a |=
On 1/18/07, Richard Kenner <[EMAIL PROTECTED]> wrote:
> I'm not immediately aware of too many cases where lowering the IL is
> going to expose new opportunities to track and optimize nonzero/zero
> bits stuff.
Bitfield are the big one. If you have both bitfield and logical operations,
you can o
Hi All,
I am using recog_memoized in the machine dependent reorg pass.
However, It is causing an ICE because unwittingly a CODE_LABEL is
getting passed to it.
I understand that CODE_LABEL is in the RTX_EXTRA class and intuitively
It is wrong to use INSN_CODE ( which is used in recog_memoized) on
Hello all,
I added a small optimization which does the following . It converts
a = a + 1
if ( a > 0 )
to
if ( a > -1)
a is a signed int.
However this is causing 920612-1.c to fail, which is reproduced below
for convenience.
f(j)int j;{return++j>0;}
main(){ if(f((~0U)>>1)) abort(); exit(0); }
T
On 2/22/07, Paolo Bonzini <[EMAIL PROTECTED]> wrote:
> My question is that, IMO the test is checking overflow behaviour. Is
> it right to have such a test ?
Would you care to prepare a patch that moved it under gcc.dg, adding a {
dg-options "-O2 -fno-strict-overflow" } marker (or maybe "-O2
-fn
On Thu, Mar 31, 2011 at 4:04 PM, Iyer, Balaji V wrote:
> Hello Everyone,
> I see in GCC that when we use the flag "-f-tree-optimized" it
> will dump the contents of the input file after doing all the tree-based
> optimization. Is it possible for me to modify this file and then subm
Hi,
Is it possible for a component_ref node to have its arg 0 to be NULL ?
I would think not because from tree.def I gather that arg 0 tells me
what structures field this component_ref refers to. For convenience, I
have pasted here what tree.def tells me about a component_ref
/* Value is structu
Richard,
> If you are not working on trunk this can happen because the way
> MEM_EXPRs are "canonicalized".
Thanks. Yes, I am not on trunk and may not be able to move right away.
I would appreciate some pointers about where I should look, If I want
to fix this ?
Thanks,
Pranav
> Look at
>
> 2009-07-14 Richard Guenther
> Andrey Belevantsev
>
> * tree-ssa-alias.h (refs_may_alias_p_1): Declare.
> (pt_solution_set): Likewise.
> * tree-ssa-alias.c (refs_may_alias_p_1): Export.
> * tree-ssa-structalias.c (pt_solution_set): New functio
Hi,
A possible silly question about the dead store elimination pass. From
the documentation it is clear that the store S1 below is removed by
this pass (in dse.c)
*(addr) = value1; // S1
.
.
*(addr) = value2 // S2 .. No read of "addr" between S1 and S2.
..
> Are you talking about the tree dead-store elimination pass or
> the RTL one? Basically *addr = value1; cannot be removed
> if addr does not point to local memory or if the pointed-to
> memory escapes through a call-site that is dominated by this store.
I am talking about the RTL dead-store elim
On Thu, Mar 18, 2010 at 10:29 AM, roy rosen wrote:
> Hi,
>
> I am trying to implement a simple load 8 bytes instruction.
> I tried to use movdi so that it would allocate two sequential
> registers for the load.
> It starts well but in pass subreg1 the insns are decomposed and all DI
> operands are
Hi,
I was having trouble with building gcc and found that the problem i
was having had been reported earlier and a patch to fix that had been
submitted in feb 2004.
However when i try to access the mailing list archives i am able to
reach the index page for feb 2004. the link to which is given as:
Hi,
I am writing about a problem I noticed with the code generated for
memcpy by arm-none-eabi-gcc.
Now, memcpy has three distinct loops - one that copies (4 *sizeof
(long) ) bytes per iteration, one that copies sizeof (long) bytes per
iteration and the last one that copies one byte per iteration
Hi,
Consider the attached testcase.
Working on a private port (Infact I see this problem on
arm-none-eabi-gcc too). I see the following in test.c.003t.original
fail = (short int) usi <= ssi;
And then in test.c.025t.ssa
usi.2_5 = (short int) usi_4;
fail.3_6 = usi.2_5 <= ssi_2;
Now ccp1 does c
> Btw, I have a fix.
oh gr8. I just saw your post on the gcc-patches. Do you still want me
to add this to PR35163 for the record ?
Cheers!
Pranav
Hi,
I have a case where the code looks roughly like
foo = i1 i2;
if (test1) bar1 = i1 i2;
if (test2) bar2 = i1 i2;
This can get converted into
reg = i1 i2
foo = reg
if (test1) bar1 = reg
if (test2) bar2 = reg
GCC 4.3 does fine here except when the operator is "logical and" (see
attached. tes
Hi Mohammed,
> But how can i handle instances like this? Should i be doing insertion
> of nops in reorg pass?
FWIW, I had worked on a port for VLIW processor about three years back
and IIRC we had used the reorg pass for inserting the nops. I think
if you look at the scheduler dumps you will
Hi,
I may not have correctly understood your questions but from what I
understand I think you mean to ask how you could easily plug in your
optimization pass into GCC so as to test your implementation of some
optimization.
Well, the way to do that would be to understand the pass structure and
dec
kerneltest.c:22: error: unrecognizable insn:
(jump_insn 26 25 29 3 (set (pc)
(create_body_after (cre (reg:DI 75)
(const_int 0 [0x0]))
(label_ref 13)
(pc))) -1 (nil)
(nil))
kerneltest.c:22: internal compiler error: in extract_insn, at recog.c:2096
On 7/18/07, Venkatesan Jeevanandam <[EMAIL PROTECTED]> wrote:
I am working on the testsuite for a new crosscompiler hosted on x86
Platform,
While performing execute test using gcc testsuite,
I am getting the error message in execute test
/tmp/2112-1.x0: /tmp/2112-1.x0: cannot execute
Hi All,
I am working on a private port and am seeing the following problem.
For a function returning a double the value is stored by the function
in memory. cse removes one of the two loads (to retrieve this returned
value) after the function is called.
To elaborate, the following is the dump just
> Where does reg 178 come from? It does not appear in the other insns
> you listed.
I am sorry, my mistake. I meant to say that the dump was only a part
of the entire dump of the function. reg 178 is the result of a
previous call to __floatsidf and is defined by the following insn.
(insn 19 18 2
Hi,
> Or perhaps this could be another manifestation of the "cse gets confused by
> reg_equal notes on subparts of dimode pseudos if no movdi pattern is defined
> in the backend" bug[*]? Pranav, is there a movdi pattern in your backend?
> There needs to be one, gcc does get it wrong if you rely
Hi,
I am working on a private port and getting an ICE in valid code. This
mainly is because of the following ( which is a part of the entire
dump of RTL of the source file)
(insn 13 8 14 2 /fc3/testcases/reduce/testcase-min.i:8 (set (reg:SI 138)
(const_int 0 [0x0])) 44 {*movsi} (expr_list:
> Who is calling CONST_DOUBLE_LOW on this value?
plus_constant calls CONST_DOUBLE_LOW on this value.
simplify_binary_operation_1 calls plus_constant ( while trying to
simplify PLUS on (const_double:SF 0 [0x0] 0.0 [0x0.0p+0]) & (const_int
-2147483648 [0x8000]) ), which in turn calls CONST_DOUBL
> How can we have a PLUS on a CONST_DOUBLE and a CONST_INT? That does
> not make sense, as there is no MODE argument that could make this work
> correctly. From your description, MODE must be some integer mode, in
> which case it is wrong to be using a CONST_DOUBLE in SFmode.
>
> (I don't know wh
> reg:SI 140 is known to have the constant value
> (const_int -2147483648 [0x8000]))
Wasnt clear maybe in my previous post. reg:SI 140 is known to have
this const_int value from a previous copy into it - here
(insn 19 17 20 2 /fc3/scratchpad/testcase-min.i:8 (set (reg:SI 140)
(const_in
> (reg:SF 139) can hold the value (const_double:SF 0) but (subreg:SI
> (reg:SF 139)) should be the value (const_int 0). Perhaps the problem
> is how we handle a REG_EQUAL note when the destination of the set is a
> SUBREG.
(subreg:SI (reg:SF 139), 0) shouldnt be able to hold the value
(float:SF (
Hi,
> Pranav, although there is indeed a bug in the mid-end here, from your point
> of view the simple and effective workaround should be to implement a movdi
> pattern (and movsf and movdf if you don't have them yet: it's an absolute
> requirement to implement movMM for any modes you expect you
On 8/23/07, petruk_gile <[EMAIL PROTECTED]> wrote:
>
> Hi all ..
>
> I'm currently porting GCC into a new processor, and I have a problem in
> instruction scheduling ...
>
> The case is like this:
> In the machine description (*.md) file, sometimes I emit a single RTL
> instruction into multiple AS
Hi,
consider the following code,
struct x { int a; int b; int c; int d; int e[120];};
struct x *a, *b;
void foo ( )
{
*a = *b;
}
Now for the stmt int the function foo a memcpy will be generated.
However, this can be tail call optimized. My aim is to identify such
opportunities in find_tail_ca
On 10/9/07, Daniel Berlin <[EMAIL PROTECTED]> wrote:
> Yes
> we do not create subvars for non-named memory locations. IE random
> pointer dereferences.
>
> This is mainly because it would require a lot of time and memory in
> the compiler.
>
> It was done because most optimizers rely solely on vde
Hi,
In the attached testcase due to an ivopts modification, while
rewriting the uses the compiler crashes in tree-ssa-operands.c because
the number of virtual operands of the modified stmt is much greater
than the thresholds controlled by OP_SIZE_{1,2,3} in
tree-ssa-operands.c.
I went through
http
Hi,
Working on a private port I am seeing a problem with reload clobbering
a live register and thus causing havoc.
Consider the following snippet of the code dump.
(note:HI 85 84 86 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(note:HI 86 85 89 5 NOTE_INSN_DELETED)
(insn:HI 89 86 87 5 cor_h.c:129 (set (reg:S
On 06 Nov 2007 21:50:09 -0800, Ian Lance Taylor <[EMAIL PROTECTED]> wrote:
> Li Wang <[EMAIL PROTECTED]> writes:
>
> > I wonder if any efforts have been made to retarget GCC to VLIW
> > backend.Is there any project trying to do that? Is it included in the
> > GCC mainstream? Thanks.
Dr. Baumgartl,
> I am interesting in it. How about the current status, is it ongoing
> developing? Is it included in GCC official release?
Unfortunately our group is not actively working on that right now.
Because of some reasons
( mainly the paucity of time) we couldnt release it to the GCC
community then ( ab
Hi Eric,
Thanks for the response
> Of course, it goes to great length to do so but there can be bugs. You didn't
> specify which version of the compiler you're using though; they may have been
> already fixed on the mainline.
Oh, I am using quite a new version of the compiler - rev 129547,
DATES
> Even though the other 2 addressing modes are implemented, the
> attributes could not be checked in the other 2 modes. These 2 modes
> are "disp with register" and "register indirect" addressing modes. The
> tree structure in these addressing modes could not be checked for
> attributes using the R
> Did you test for large programs? Such as applications from SPEC 2006? or
> the equal size of programs. Thanks.
Oh no, we didnt. We stopped when we achieved fair stability purely on
the basis of
the number of testsuite failures ( less than 100).
cheers!
Pranav
> OK. AFAICS there is nothing glaring in the RTL you posted so you'll have to
> put a watchpoint and find out who has set reg_rtx for this particular reload.
reg_rtx gets set due to a call to choose_reload_regs which in turn
calls allocate_reload_reg to set reg_rtx.
Also, just to confirm if I am
Hi,
> > (call_insn:HI 91 270 92 5 cor_h.c:129 (parallel [
> >(set (reg:SI 1 $c1)
> >(call (mem:SI (symbol_ref:SI
> > ("DotProductWithoutShift") [flags 0x41] > DotProductWithoutShift>) [0 S4 A32])
> >(const_int 0 [0x0])))
> >(use (const_i
Hi,
>
> DF is supposed to be out of the game at this point, it has handed over the
> control since global.c:build_insn_chain as far as liveness info is concerned.
Oh I used DF and it worked for me. But I think that is because this is
the first new instruction to be inserted and nothing really must
> Hi,
> For the backend TI DSP TMS320C6x, There are four types of functional
> units which are .L unit, .M unit, .S unit and .D unit, and each type
> consists of two units named .X1 and .X2 respectively. Namely, there are
> total 8 units. Except the .M units surve only for multiply, other units
> s
On Dec 9, 2007 2:19 AM, Thomas Sailer <[EMAIL PROTECTED]> wrote:
> > Has anyone faced a similar problem before? Are there targets for which
> > both VLIW and DBR are enabled? Perhaps ia64?
>
Ok, this was a long time back, but Yes I have faced a similar problem.
We disabled
delayed branch schedulin
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