Re: On-Demand range technology [1/5] - Executive Summary

Hi Andrew, Thanks for working on this. Enable elimination of zext/sext with VRP patch had to be reverted in (https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00672.html) due to the need for value ranges in PROMOTED_MODE precision for at least 1 test case for alpha. Playing with ranger suggest that

Re: On-Demand range technology [1/5] - Executive Summary

precision, the patch would be correct and used to eliminate redundant zero/sign extensions. Please let me know if my explanation is not clear and I will show it with more examples. Thanks, Kugan On Fri, 21 Jun 2019 at 23:27, Andrew MacLeod wrote: > > On 6/19/19 11:04 PM, Kugan Vivekanandarajah

Re: Duplicating loops and virtual phis

Hi Bin and Steve, On 17 May 2017 at 19:41, Bin.Cheng wrote: > On Mon, May 15, 2017 at 7:32 PM, Richard Biener > wrote: >> On May 15, 2017 6:56:53 PM GMT+02:00, Steve Ellcey >> wrote: >>>On Sat, 2017-05-13 at 08:18 +0200, Richard Biener wrote: On May 12, 2017 10:42:34 PM GMT+02:00, Steve E

Loop reversal

I am looking into reversing loop to increased efficiency. There is already a PR22041 for this and an old patch https://gcc.gnu.org/ml/gcc-patches/2006-01/msg01851.html by Zdenek which never made it to mainline. For constant loop count, ivcanon pass is adding reverse iv but this not selected by ivo

Re: [RFC] type promotion pass

Hi Richard, On 16 September 2017 at 06:12, Richard Biener wrote: > On September 15, 2017 6:56:04 PM GMT+02:00, Jeff Law wrote: >>On 09/15/2017 10:19 AM, Segher Boessenkool wrote: >>> On Fri, Sep 15, 2017 at 09:18:23AM -0600, Jeff Law wrote: WORD_REGISTER_OPERATIONS works with PROMOTE_MODE.

Re: [RFC] type promotion pass

Hi Steve, On 19 September 2017 at 05:45, Steve Ellcey wrote: > On Mon, 2017-09-18 at 23:29 +0530, Prathamesh Kulkarni wrote: >> >> Hi Steve, >> The patch is currently based on r249469. I will rebase it on ToT and >> look into the build failure. >> Thanks for pointing it out. >> >> Regards, >> Pra

Handling prefetcher tag collisions while allocating registers

Hi All, I am wondering if there is anyway we can prefer certain registers in register allocations. That is, I want to have some way of recording register allocation decisions (for loads in loop that are accessed in steps) and use this to influence register allocation of other loads (again that are

Re: Handling prefetcher tag collisions while allocating registers

Hi Bin, On 24 October 2017 at 18:29, Bin.Cheng wrote: > On Tue, Oct 24, 2017 at 12:44 AM, Kugan Vivekanandarajah > wrote: >> Hi All, >> >> I am wondering if there is anyway we can prefer certain registers in >> register allocations. That is, I want to have som

Re: Global analysis of RTL

Hi, On 26 October 2017 at 14:13, R0b0t1 wrote: > On Thu, Oct 19, 2017 at 8:46 AM, Geoff Wozniak wrote: >> R0b0t1 writes: >>> >>> When I first looked at the GCC codebase, it seemed to me that most >>> operations should be done on the GIMPLE representation as it contains the >>> most information.

Re: Problems in IPA passes

Hi Jeff, On 28 October 2017 at 18:28, Jeff Law wrote: > > Jan, > > What's the purpose behind calling vrp_meet and > extract_range_from_unary_expr from within the IPA passes? This is used such that when we have an argument to a function and this for which we know the VR and this intern is passed

Re: Problems in IPA passes

Hi Jeff, On 31 October 2017 at 14:47, Jeff Law wrote: > On 10/29/2017 03:54 PM, Kugan Vivekanandarajah wrote: >> Hi Jeff, >> >> On 28 October 2017 at 18:28, Jeff Law wrote: >>> >>> Jan, >>> >>> What's the purpose behind calling vrp_

Re: poly_uint64 / TYPE_VECTOR_SUBPARTS question

Hi, On 9 February 2018 at 09:08, Steve Ellcey wrote: > I have a question about the poly_uint64 type and the TYPE_VECTOR_SUBPARTS > macro. I am trying to copy some code from i386.c into my aarch64 build > that is basically: > > int n; > n = TYPE_VECTOR_SUBPARTS (type_out); > > And it is not compi

Generating gimple assign stmt that changes sign

Hi, I am looking to introduce ABSU_EXPR and that would create: unsigned short res = ABSU_EXPR (short); Note that the argument is signed and result is unsigned. As per the review, I have a match.pd entry to generate this as: (simplify (abs (convert @0)) (if (ANY_INTEGRAL_TYPE_P (TREE_TYPE (@0)))

Re: Generating gimple assign stmt that changes sign

Hi Jeff, Thanks for the prompt reply. On 22 May 2018 at 09:10, Jeff Law wrote: > On 05/21/2018 04:50 PM, Kugan Vivekanandarajah wrote: >> Hi, >> >> I am looking to introduce ABSU_EXPR and that would create: >> >> unsigned short res = ABSU_EXPR (short); >>

Sched1 stability issue

Hi, We noticed a difference in the code generated for aarch64 gcc 7.2 hosted in Linux vs mingw. AFIK, we are supposed to produce the same output. For the testacse we have (quite large and I am trying to reduce), the difference comes from sched1 pass. If I disable sched1 the difference is going aw