Hi Alexandre,
I was having some trouble with dwarf sections in picochip port. I am not
a dwarf expert, but when i looked at the changes in r151312, file
dwarf2out.c, function dwarf2out_var_location on line 17965, we have
sprintf (loclabel, "%s-1", last_label);
...
What is la
Thanks for the pointer, Jakub.
Cheers
Hari
Jakub Jelinek wrote:
On Mon, Sep 21, 2009 at 05:04:27PM +0100, Hariharan wrote:
Hi Alexandre,
I was having some trouble with dwarf sections in picochip port. I am not
a dwarf expert, but when i looked at the changes in r151312, file
sn't very clear.
You need to use -fprofile-use - the typical usage scenario is to
compile with -fprofile-generate
to build an executable to do profile collection, and then compile with
-fprofile-use
to build optimized code using the profile data.
Seongbae
On Thu, Jan 8, 2009 at 6:30 AM, Harihar
Seongbae Park ??? ??? wrote:
On Thu, Jan 8, 2009 at 10:11 AM, Hariharan wrote:
Hi Seongbae,
Does that mean that someone cant use the profile just to annotate branches
(and get better code by that), without having to get the additional baggage
of "unroll-loops", "peel-loops&quo
Hi,
I just wanted to see if there are others out there who get profile
information from a simulator and feed that information back for GCC's
PBO, in the .gcda format.
I had tried this on picoChip, by changing the instrumentation code in
GCC for fprofile-arcs and got edge profile working quite
Hi,
I ran into some code-size/stack size bloat using -Os for a piece of
code. This seemed to happen only when certain single call-site functions
are defined "static" and not otherwise. On investigating further on
this, i see that the inline_functions_called_once seems to rely only on
"cgraph_c
Hello,
I saw a bug in sched1 where it reorders two unspec_volatile
instructions. These instructions do port communications (from the same
port) and doing them in the wrong order is unacceptable. I digged a bit
deeper to see what is happening. Going into sched1, the relevant bit of
basic block
Hello all,
Picochip has communication instructions that allow one array element to
pass data to another. There are 3 such instructions PUT/GET/TSTPORT.
Currently, all three of these use UNSPEC_VOLATILE side-effect
expressions to make sure they don't get reordered. But, i wonder if it
is an ove
Hello all,
I found something a little odd with delay slot scheduling. If i had the
following bit of code (Note that "get" builtin functions in picochip
stand for port communication)
int mytest ()
{
int a[5];
int i;
for (i = 0; i < 5; i++)
{
a[i] = (int) getctrlIn();
}
switch (a[3])
{
Hi Jakub,
I have not had any response from Alexandre on this yet and i haven't had
much luck in mailing list either
(http://gcc.gnu.org/ml/gcc/2010-04/msg00917.html). Is there anyone else
who is familiar with VTA who could help?
Thanks
Hari
jakub at gcc dot gnu dot org wrote:
Thanks to the GCC SC for accepting the picochip port.
Regards
Hari
David Edelsohn wrote:
I am pleased to announce that the GCC Steering Committee has
accepted the picoChip port for inclusion in GCC and appointed
Hariharan Sandanagobalane and Daniel Towner as port maintainers.
The
usion in GCC and appointed
Hariharan Sandanagobalane and Daniel Towner as port maintainers.
The initial patch needs approval from a GCC GWP maintainer before it may
be committed.
Please join me in congratulating Hari and Daniel on their new role.
Please update your listing in the MAINTA
Hi Joel,
I ran into a similar problem moving from 4.2.2 to 4.3.0. I looked a bit
into it and found that 4.3 compiler inlines more aggressively than 4.2.x
compiler. The reason was that the following two lines were removed from
opts.c
set_param_value ("max-inline-insns-single", 5);
Hello,
I see that in x86 GCC, you can define a structure with
struct trial
{
long a[10];
};
Whereas in a 16-bit target (picochip), you cannot define,
struct trial
{
long a[1];
};
In the case above, i get a
"size of array ‘a’ is too large" error.
The thing that took me by surp
Hello,
I found something rather strange with the unsigned comparison warnings
in GCC.
If i had,
unsigned char
a;
Thanks Ian. I will raise this in gcc-help mailing list.
Cheers
Hari
Ian Lance Taylor wrote:
Hariharan <[EMAIL PROTECTED]> writes:
I found something rather strange with the unsigned comparison warnings
in GCC.
This is the wrong mailing list. The mailing list gcc@gcc.gnu.org is
f
Hi Seongbae,
I was doing some work on profiling for picochip, when i noticed what
looks to me like a bug. It looks to me that using fbranch-probabilities
on the commandline (after a round of profile-generate or profile-arcs)
would just not work on any target. Reason..
Coverage.c:1011
if (f
Hi,
Since r144598, pr39339.c has been failing on picochip. On investigation,
it looks to me that the testcase is illegal.
Relevant source code:
struct C
{
unsigned int c;
struct D
{
unsigned int columns : 4;
unsigned int fore : 9;
unsigned int back : 9;
unsigned int fragme
Yes, if i change the structure to bring the 3 1-bit members forward, to
avoid padding, the testcase does pass.
Thanks to both of you for your help.
Cheers
Hari
Jakub Jelinek wrote:
On Tue, Mar 10, 2009 at 01:44:11PM +, Hariharan Sandanagobalane wrote:
Since r144598, pr39339.c has been
e-use
to build optimized code using the profile data.
Seongbae
On Thu, Jan 8, 2009 at 6:30 AM, Hariharan Sandanagobalane
wrote:
Hi Seongbae,
I was doing some work on profiling for picochip, when i noticed what looks
to me like a bug. It looks to me that using fbranch-probabilities on the
comman
vent some wrong optimizations.
Cheers,
Bingfeng
-Original Message-
From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On
Behalf Of Hariharan
Sent: 12 May 2010 11:18
To: gcc@gcc.gnu.org
Subject: Machine description question
Hello all,
Picochip has communication instructions
that i was using for GET, which was inside a loop, was being
hoisted out of the loop by the loop optimizer. I guess i should have
seen this coming, since unspec is just "machine-specific" operation and
the optimizer probably rightly assumes that multiple execution of this
ll porivate and not in mainline.
Cheers,
Bingfeng
-Original Message-
From: Hariharan Sandanagobalane [mailto:harihar...@picochip.com]
Sent: 13 May 2010 10:17
To: Bingfeng Mei
Cc: gcc@gcc.gnu.org
Subject: Re: Machine description question
The patterns for PUT/GET were
; Scalar Pu
instruction that should be
moved but not?
Cheers,
Bingfeng
-Original Message-
From: Hariharan Sandanagobalane [mailto:harihar...@picochip.com]
Sent: 14 May 2010 12:26
To: Bingfeng Mei
Cc: gcc@gcc.gnu.org
Subject: Re: Machine description question
Hi Bengfeng,
Changing my instruction patterns
Jeff Law wrote:
On 05/24/10 05:46, Hariharan wrote:
Hello all,
I found something a little odd with delay slot scheduling. If i had
the following bit of code (Note that "get" builtin functions in
picochip stand for port communication)
int mytest ()
{
int a[5];
int i;
for (i
Hello all,
Is it possible to use rtl vector patterns like vec_extractm, vec_setm
from C code? It looks like C subscipting for vector variables was
allowed at some point and then removed. So, can these rtl patterns only
be used from languages other than C?
Of course, i can use these in target
Hi Ian,
Thanks for your help.
I switched to mainline and the vector extract works a treat. When i
tried vector set, it was still generating suboptimal code. Is this bit
of code still work in progress?
Cheers
Hari
On 04/11/10 19:23, Ian Lance Taylor wrote:
Hariharan Sandanagobalane writes
Dear SC members,
I used to maintain the picochip port of GCC, but I have not been
active on the picochip port over the last 8 months. This is unlikely
to change in the future, so I would like my name to be removed from
the maintainers list as picochip maintainer. I am still actively
working on GCC,
Hello,
I looked at an inefficient code sequence for a simple program using
GCC's picochip port (not yet submitted to mainline). Basically, a
program like
long carray[10];
void fn (long c, int i)
{
carray[i] = c;
}
produces good assembly code. But, if i were to do
struct complex16
{
int re,i
Ian Lance Taylor wrote:
Hariharan Sandanagobalane <[EMAIL PROTECTED]> writes:
I looked at an inefficient code sequence for a simple program using
GCC's picochip port (not yet submitted to mainline).
Are you working with mainline sources?
I was not. I tried the same with gcc
Hello,
I am implementing support for PBO on picochip port of GCC (not yet
submitted to mainline).
I see that GCC generates 2 files, xx.gcno and xx.gcda, containing the
profile information, the former containing the flow graph
information(compile-time) and later containing the edge profile
in
Seongbae Park (???, ???) wrote:
On 9/27/07, Hariharan Sandanagobalane <[EMAIL PROTECTED]> wrote:
Hello,
I am implementing support for PBO on picochip port of GCC (not yet
submitted to mainline).
I see that GCC generates 2 files, xx.gcno and xx.gcda, containing the
profile informatio
Hi,
I am trying to enable delayed branch scheduling on our port of Gcc for
picochip (16-bit VLIW DSP). I understand that delayed-branch is run as a
seperate pass after the DFA scheduling is done. We basically depend on
the TImode set on the cycle-start instructions to decide what
instructions
Hi thomas,
Thanks for your reply. A couple of questions below.
Thomas Sailer wrote:
Has anyone faced a similar problem before? Are there targets for which
both VLIW and DBR are enabled? Perhaps ia64?
I did something similar a few months ago.
What was your target? Is the target code available
Hello,
I see quite a few instances when i get the following RTL. A conditional
branch, followed by a BASIC_BLOCK note, followed by a non-TImode
instruction. Theoretically, i should be allowed to package the non-TI
instruction along with the conditional branch, but doing so seems to be
produce
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