On Wed, 2007-09-26 at 08:11 +0800, 吴曦 wrote:
> Truly thanks, I have discovered this problem after I sent the first
> mail, and I found itanium1.md and itanium2.md describe the pipeline
> hazard, but they are really complex... :-(. Is there any guide or docs
> on this? thanks
There is Itanium micro
2007/9/26, Jim Wilson <[EMAIL PROTECTED]>:
> ÎâêØ wrote:
> > [(set_attr "itanium_class" "tnat")])
>
> The itanium_class names are based on info from the Itanium Processor
> Microprocessor Reference by the way.
>
> I believe the problem is that you didn't add info to the DFA scheduler
> dscr
ÎâêØ wrote:
[(set_attr "itanium_class" "tnat")])
The itanium_class names are based on info from the Itanium Processor
Microprocessor Reference by the way.
I believe the problem is that you didn't add info to the DFA scheduler
dscriptions in the itanium1.md and itanium2.md files fo
Hi
I am working on IA-64 and GCC-4.1.1
I modify ia64.md to support tnat instruction. More specifically, I add
the following define_insn:
(define_insn "shift_tnat"
[(set (match_operand:BI 0 "register_operand" "=c")
(unspec:BI [(match_operand:DI 1 "gr_regist
