[ was: Re: combination of read/write and earlyclobber constraint modifier ]
On 02-07-14 17:52, Jeff Law wrote:
(by the way, in the same aarch64-simd.md file, I noticed some
define_expand with constraints, that looks strange)
It sometimes happens when a define_insn is converted into a
mbay, Powai, Mumbai 400 076, India.
email : u...@cse.iitb.ac.in
homepage: http://www.cse.iitb.ac.in/~uday
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--
> (define_expand
(define_expand "movsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(match_operand:SI 1 "general_operand" "")
)]
""
{
if(GET_CODE(operands[0])==MEM && GET_CODE(operands[1])!=REG)
{
Hello, Dr. Uday Khedker:
I just found that emit_move_insn function can't be used in define_expand
pattern in the spim gcc4.0.2 platform. It will cause the Segmentation Fault.
Something like recursion happened.
I changed the define_expand "movsi" from:
(define_expand "
(define_expand "negsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT"
"")
(define_insn "*negsf2"
[(set (match_operand:S
On Tue, Aug 15, 2006 at 10:52:01AM -0700, Michael Eager wrote:
> (define_expand "negsf2"
> [(set (match_operand:SF 0 "gpc_reg_operand" "")
> (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
> "TARGET_HARD_FLOAT"
I'm having trouble understanding part of the machine description
for PowerPC floating point operations.
There are a number of places where there are pairs of templates,
one with define_expand, the other with define_insn or
define_insn_and_split. For example, the fp negate temp
Hey,
It's very sorry. I have just found the answer just in the context.
It's a so stupid question.
DONE
Use the DONE macro to end RTL generation for the pattern. The only RTL
insns resulting from the pattern on this occasion will be those
already emitted by explicit calls to emit_insn within the
Hello,
I have a doubt here about define_expand and would be appreciated for
your any help. The internals say,
Usually these statements prepare temporary registers for use as
internal operands in the RTL template, but they can also generate RTL
insns directly by calling routines such as emit_insn
Hi,
I am trying to separate move immediates that require more than 16 bits
into two instructions that set the high and low 16 bits of a register
respectively. Here is my define_expand:
(define_expand "movsi"
[(set (match_operand:SI 0 "nonimmediate_operand" ""
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