yazdanbakhsh writes:
> I'm working with GCC 2.7.
I think I see your problem.
> I think, It doesn't support define_predict.
> I define a c function in the mips.c file and add the following lines:
>
> int
> new_arith_operand (op, mode)
> rtx op;
> enum machine_mode mode;
> {
> if (GE
Actually, I'm working with simplescalar and it only supports gcc 2.9.
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On 15 June 2010 14:01, yazdanbakhsh wrote:
>
> I'm working with GCC 2.7. I think, It doesn't support define_predict.
> I define a c function in the mips.c file and add the following lines:
[...]
> I appreciate any help.
I think the best advice I can give you is: Use a recent GCC version.
GCC 2.7
Hi,
I'm working with GCC 2.7. I think, It doesn't support define_predict.
I define a c function in the mips.c file and add the following lines:
int
new_arith_operand (op, mode)
rtx op;
enum machine_mode mode;
{
if (GET_CODE (op) == CONST_INT)
if(NEW_INT_UNSIGNED (op))
Hello,
> I want to limit the size of immediate field of some operation.
I think you can look at SIGNED_INT_FITS_N_BITS definition at
config/crx/crx.c
for such example.
You can write a predicate like the following; and use it when describing
the immediate
operand in the md file.
(define_predicate
Hi,
I want to limit the size of immediate field of some operation. For example
somehow modify the machine description that the compiler supports only 0-255
for immediate operand.
I also want to change the compiler to the 2-address operand.
do you have any ideas?
I just need some hint
Best Regard
yazdanbakhsh writes:
> I did what you said, and the same error happened :(
I'm sorry you're having trouble, but if you want us to be able to help
you you need to show us precisely what you did, precisely what
happened, and what you expected to happen.
Ian
I did what you said, and the same error happened :(
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yazdanbakhsh writes:
> I want to exclude all immediate or instruction. I did this by the following
> define_insn
>
> /--
> (define_insn "iorsi3"
> [(set (match_operand:SI 0 "register_operand" "=d,d")
> (ior:SI (m
Hi,
I want to exclude all immediate or instruction. I did this by the following
define_insn
/--
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(ior:SI (match_operand:SI 1 "uns_arith
yazdanbakhsh writes:
> I want to exclude XORI from the instruction set of a cpu. I deleted all the
> XORI in md file. But when I compiled my program some XORI operation still
> exist. how this would be possible?
It could be printed directly from a .c file in your config/CPU
directory.
Ian
Hi,
I want to exclude XORI from the instruction set of a cpu. I deleted all the
XORI in md file. But when I compiled my program some XORI operation still
exist. how this would be possible?
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yazdanbakhsh writes:
> (define_insn "*bltdf"
> [(set (pc)
> (if_then_else (lt:SI (match_operand:DF 1 "" "")
>(match_operand:DF 2 "" ""))
> (match_operand 3 "pc_or_label_operand" "")
> (match_operand 4 "pc_or_label_operand" "")))]
> ""
>
> "*
> {
Hi,
I found an strategy that would solve my problem.
I changed .md with the following paragraph...
(define_expand "blt"
[(set (pc)
(if_then_else (lt:SI (match_dup 1)
yazdanbakhsh writes:
> (define_expand "cbranchsi4"
> [(set (pc)
> (if_then_else: SI (le:SI (match_operand:SI 0 "register_operand" "=d,d")
> (match_operand:SI 1 "register_operand" "=d,d"))
> (label_ref (match_operand 2 "" ""))
> (pc)))]
> ""
> "
Hi,
I changed the .md and .c file:
I add these lines to the .md file:
-
(define_insn "ble1"
[(set (pc)
(if_then_else: SI (le:SI (match_operand:SI 0 "register_operand" "=d,d")
(match_operand:SI 1 "register_operand" "=d,d")
Hi,
As I told I want to add "ble" intruction in MIPS that works like "beq".
I used from the available branch_equality instruction that shows in the
following paragraph:
--
(define_insn "branch_equal
yazdanbakhsh writes:
> I have read all the documents, and changed some lines but nothing happened :(
That is good, but to get help you really need to ask specific
questions. Show us an insn pattern, tell us what you are trying to
do, tell us what you did, tell us what happened.
Ian
> Ian Lanc
I have read all the documents, and changed some lines but nothing happened :(
Ian Lance Taylor-3 wrote:
>
> yazdanbakhsh writes:
>
>> I want to change instruction blez to ble. ble compare two registers and
>> jump
>> to the target address if the condition is true.
>
> Read the internals manua
yazdanbakhsh writes:
> I want to change instruction blez to ble. ble compare two registers and jump
> to the target address if the condition is true.
Read the internals manual to understand how operand predicates and
constraints work. See the hundreds of existing examples. Ask if you
have spec
Hi,
I want to change instruction blez to ble. ble compare two registers and jump
to the target address if the condition is true.
thanks in advance,
Ian Lance Taylor-3 wrote:
>
> yazdanbakhsh writes:
>
>> Please assume I'm working with the MIPS. There is a little difference
>> between the MIP
yazdanbakhsh writes:
> This is the newer version. It works correctly. I just want know is there any
> other way.
Did you read what I wrote earlier?
http://gcc.gnu.org/ml/gcc/2010-05/msg00048.html
Ian
This is the newer version. It works correctly. I just want know is there any
other way.
thanks
***
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
I forget to thank you for your help.
But if I do write your code how compiler knows that it should be put two
instructions instead immediate shift?
I write this piese of code:
###33
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "re
Is it any way that we can chat?
I'm working on my thesis project and a paper. I appreciate it if you would
cooperate in this project.
I have gmail Id "amir.yazdanbakhsh"
and also skype "amir.yazdanbakhsh"
best regards,
yazdanbakhsh wrote:
>
> Hi,
>
> Please assume I'm working with the MIPS. Th
yazdanbakhsh writes:
> Please assume I'm working with the MIPS. There is a little difference
> between the MIPS and what I'm actually working on it. How can I remove
> immediate logical shift right/left from the compiler?
> I mean If I want the programmer writes an immediate shift, It is compiled
Hi,
Please assume I'm working with the MIPS. There is a little difference
between the MIPS and what I'm actually working on it. How can I remove
immediate logical shift right/left from the compiler?
I mean If I want the programmer writes an immediate shift, It is compiled to
the two instructions:
yazdanbakhsh writes:
> I'm working on my a gcc compiler for my own written processor with the help
> of SimpleScalar.
> I want to remove "srav/slav" (immediate arithmetic shift) from the
> instruction set. I explore ss.md file but I didn't see any define_ins for
> the mentioned instructions, but
Dear all,
I'm working on my a gcc compiler for my own written processor with the help
of SimpleScalar.
I want to remove "srav/slav" (immediate arithmetic shift) from the
instruction set. I explore ss.md file but I didn't see any define_ins for
the mentioned instructions, but they are used in othe
Ian Lance Taylor writes:
> This kind of error generally means that the operand predicate accepts
> an operand which no constraint matches. If the predicate (e.g.,
> register_operand) accepts an operand, then there must be a constraint
> that matches it. Otherwise you will get an error in
> const
"Balaji V. Iyer" <[EMAIL PROTECTED]> writes:
> Thank you very much Ian and Shreyas for your quick response. So I guess,
> my question now would be, what would be an exmple that matches this
> constraint below?
>
> ((insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
> (co
Thank you very much Ian and Shreyas for your quick response. So I guess,
my question now would be, what would be an exmple that matches this
constraint below?
((insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
(const_int -137 [0xff77])) [72 S1 A8])
(le:BI (r
"Balaji V. Iyer" <[EMAIL PROTECTED]> writes:
No need to send to both gcc@gcc.gnu.org and [EMAIL PROTECTED] I
removed gcc-help in this reply. Thanks.
>I am currently developing a GCC port for my own generic 32 bit
> processor. I have this following error when I tried to compile a
> benchmark
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